mk: report an error when the CFG_ARM64{32}_core both missing

When the CFG_ARM64_core and CFG_ARM32_core are both missing defined by
the platform, it will raise unexpected compile errors. In this pat

mk: report an error when the CFG_ARM64{32}_core both missing

When the CFG_ARM64_core and CFG_ARM32_core are both missing defined by
the platform, it will raise unexpected compile errors. In this patch,
report an compile error when neither the CFG_ARM64_core nor
CFG_ARM32_core is defined.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Zeng Tao <prime.zeng@hisilicon.com>

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Fix FIQ mask for the native interrupt handler for arm32

In Arm aarch32 mode, FIQ is not masked by hardware in IRQ mode.
For GICv2, IRQ is for foreign interrupt and already masked by hardware
in FIQ

Fix FIQ mask for the native interrupt handler for arm32

In Arm aarch32 mode, FIQ is not masked by hardware in IRQ mode.
For GICv2, IRQ is for foreign interrupt and already masked by hardware
in FIQ mode which is used for native interrupt.
For GICv3, FIQ is for foreign interrupt. It's not masked by hardware in
IRQ mode which is used for natvie interrupt. We need to mask it explicitly.

Signed-off-by: David Wang <david.wang@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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Disable IRQ and FIQ in IRQ/ABT/SVC/UND thread handlers for arm32

Disable native and foreign interrupts in thread handlers for arm32.
The tee handlers can decide when the native interrupts can be ena

Disable IRQ and FIQ in IRQ/ABT/SVC/UND thread handlers for arm32

Disable native and foreign interrupts in thread handlers for arm32.
The tee handlers can decide when the native interrupts can be enabled.

Signed-off-by: David Wang <david.wang@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-sam: Add support for Atmel-Microchip SAMA5D2-XULT board

Add basic support to get op-tee to run on SAMA5D2-XULT board.

The SoC is based on single core ARM Cortex-A5 and supports:
ARM TrustZone

plat-sam: Add support for Atmel-Microchip SAMA5D2-XULT board

Add basic support to get op-tee to run on SAMA5D2-XULT board.

The SoC is based on single core ARM Cortex-A5 and supports:
ARM TrustZone with support for configuring memory/peripherals as secure
Secure RTC
Secure boot
On-the-fly encryption/decryption of DDR bus
Tamper protection

Link: http://www.atmel.com/Images/Atmel-11267-32-bit-Cortex-A5-Microcontroller-SAMA5D2_Datasheet.pdf
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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arm: pl310: Support processors without SCU

Not all processors might have a SCU unit. So conditionally include code
that configures SCU.

Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Acked-by

arm: pl310: Support processors without SCU

Not all processors might have a SCU unit. So conditionally include code
that configures SCU.

Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: plat-hikey: increase CFG_TEE_RAM_VA_SIZE

Increases CFG_TEE_RAM_VA_SIZE to 2 MiB for the plat-hikey platform.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jens Wiklander

core: plat-hikey: increase CFG_TEE_RAM_VA_SIZE

Increases CFG_TEE_RAM_VA_SIZE to 2 MiB for the plat-hikey platform.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Hikey)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: plat-vexpress: increase CFG_TEE_RAM_VA_SIZE

Increases CFG_TEE_RAM_VA_SIZE to 2 MiB for the plat-vexpress platforms.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jens

core: plat-vexpress: increase CFG_TEE_RAM_VA_SIZE

Increases CFG_TEE_RAM_VA_SIZE to 2 MiB for the plat-vexpress platforms.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU v7)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pager: deal with large CFG_TEE_RAM_VA_SIZE

Deals with CFG_TEE_RAM_VA_SIZE > CORE_MMU_PGDIR_SIZE. This is a special
problem as the pages managed by the pager then spans several translation
tabl

core: pager: deal with large CFG_TEE_RAM_VA_SIZE

Deals with CFG_TEE_RAM_VA_SIZE > CORE_MMU_PGDIR_SIZE. This is a special
problem as the pages managed by the pager then spans several translation
tables.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pager: free pages across multiple areas

Changes tee_pager_release_phys() to handle freeing a range of pages spanning
multiple areas.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org

core: pager: free pages across multiple areas

Changes tee_pager_release_phys() to handle freeing a range of pages spanning
multiple areas.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pager: move some internal functions

Moves some internal functions inside the pager code to prepare for a
future commit.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-

core: pager: move some internal functions

Moves some internal functions inside the pager code to prepare for a
future commit.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add MEM_AREA_PAGER_VASPACE

Adds MEM_AREA_PAGER_VASPACE which is used to create empty translation
tables as needed for the pager.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Si

core: add MEM_AREA_PAGER_VASPACE

Adds MEM_AREA_PAGER_VASPACE which is used to create empty translation
tables as needed for the pager.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pager: update tee_pager_add_core_area()

All failures in tee_pager_add_core_area() are fatal. Replaces return
code with void and panics on errors instead.

Reviewed-by: Etienne Carriere <etienn

core: pager: update tee_pager_add_core_area()

All failures in tee_pager_add_core_area() are fatal. Replaces return
code with void and panics on errors instead.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pager: hide tee_pager_tbl_info

Hides tee_pager_tbl_info and provides new needed functions.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wikl

core: pager: hide tee_pager_tbl_info

Hides tee_pager_tbl_info and provides new needed functions.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add CORE_MMU_PGDIR_LEVEL

Adds the define CORE_MMU_PGDIR_LEVEL which indicates the level used for
page directories.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: J

core: add CORE_MMU_PGDIR_LEVEL

Adds the define CORE_MMU_PGDIR_LEVEL which indicates the level used for
page directories.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: make tee_mm_vcore cover TEE_RAM only

Prior to this patch was tee_mm_vcore initialized to cover the complete
page directories covering TEE_RAM. With this patch tee_mm_vcore will
only cover TEE_

core: make tee_mm_vcore cover TEE_RAM only

Prior to this patch was tee_mm_vcore initialized to cover the complete
page directories covering TEE_RAM. With this patch tee_mm_vcore will
only cover TEE_RAM in order to avoid returning unexpected addresses when
allocating.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-vextpress: fvp: map tzcdram

Map part of DRAM as TZCDRAM in sync with ARM-TF. This is needed to be
able to read pageable part supplied by ARM-TF when pager is enabled.

Reviewed-by: Joakim Bech

plat-vextpress: fvp: map tzcdram

Map part of DRAM as TZCDRAM in sync with ARM-TF. This is needed to be
able to read pageable part supplied by ARM-TF when pager is enabled.

Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (FVP)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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Add support for compressed early TAs

Add decompression code to the early TA loader and update the Python
script accordingly. The compression algorithm is "deflate", which is
used by zlib and gzip in

Add support for compressed early TAs

Add decompression code to the early TA loader and update the Python
script accordingly. The compression algorithm is "deflate", which is
used by zlib and gzip in particular. It allows for compression ratios
comprised between 3 (for bigger TAs) and 4.7 (for smaller ones). Those
numbers were observed with 32-bit TAs (QEMU).

On QEMU (armv7), the code size overhead when CFG_EARLY_TA=y, including
the decompressor, is 12K when DEBUG=0 or 20K when DEBUG=1. The
decompressor allocates about 39K of heap.

Another library compatible with zlib was tried for comparison [1].
The code size overhead with miniz was 8K (DEBUG=0) or 16K (DEBUG=1).
On the other hand, the dynamic allocation was about 43K, so the total
memory required was about same. Speed was not compared. In the end,
zlib was preferred for licensing reasons and because it is widely used.

Link: [1] https://github.com/richgel999/miniz
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (QEMU)
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (QEMUv8, pager)
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (D02 32/64 bits)
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (D02 32/64 bits, pager)
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: link.mk: force link of tee.elf when object list has changed

Since the parent commit ("Add support for early Trusted Applications"),
the link step of tee.elf may pull object files generated fro

core: link.mk: force link of tee.elf when object list has changed

Since the parent commit ("Add support for early Trusted Applications"),
the link step of tee.elf may pull object files generated from Trusted
Application binaries. This is controlled by $(EARLY_TA_PATHS). Adding
or removing files should cause tee.elf to be re-linked, even when no
re-compilation or change in the configuration variables occur. This is
not the case currently. For example:
$ make EARLY_TA_PATHS="a.elf b.elf"
$ make EARLY_TA_PATHS="a.elf" # Should re-link without b.elf

The link recipe is modified so that the link step is forced when the
object list changes.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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Add support for early Trusted Applications

Early TAs are user-mode Trusted Applications that are embedded at link
time in the TEE binary. A special read-only data section is used to
store them (.rod

Add support for early Trusted Applications

Early TAs are user-mode Trusted Applications that are embedded at link
time in the TEE binary. A special read-only data section is used to
store them (.rodata.early_ta). A Python script takes care of converting
the TAs into a C source file with the proper linker section attribute.

The feature is disabled by default. To enable it, the paths to the TA
binaries have to be given in $(EARLY_TA_PATHS). They should be ELF
files. Typical build steps:
$ make ... CFG_EARLY_TA=y ta_dev_kit # (1)
$ # ... build the TAs ... # (2)
$ make ... EARLY_TA_PATHS=path/to/<uuid>.stripped.elf # (3)
Notes:
- Setting CFG_EARLY_TA=y during the first step (1) is not necessary,
but it will avoid rebuilding libraries during the third step (3)
- CFG_EARLY_TA is automatically enabled when EARLY_TA_PATHS is non-empty
in step (3)
- Several TAs may be given in $(EARLY_TA_PATHS) (3)

Early TAs are given a higher load priority than REE FS TAs, since they
should be available even before tee-supplicant is ready.

Suggested-by: Zeng Tao <prime.zeng@hisilicon.com>
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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Add support for several user TA stores

Replace the pointer to the user-mode TA load operations with a list
so that several implementations may be used simultaneously. Each store
has its own priority

Add support for several user TA stores

Replace the pointer to the user-mode TA load operations with a list
so that several implementations may be used simultaneously. Each store
has its own priority.
Make tee_ta_init_user_ta_session() iterate on the list and stop as
soon as a matching TA is found.
This is preparatory work for the introduction of a new TA store.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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Add description string to user_ta_store_ops

In preparation for the introduction of a new TA store type, add a
description string to the user_ta_store_ops structure and print it when
a user-mode TA i

Add description string to user_ta_store_ops

In preparation for the introduction of a new TA store type, add a
description string to the user_ta_store_ops structure and print it when
a user-mode TA is being loaded.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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Remove leading spaces and dots in DMSG() messages

Some debug messages have various amounts of leading spaces and dots
(.) probably in an attempt to better align the text. It is unreliable
because de

Remove leading spaces and dots in DMSG() messages

Some debug messages have various amounts of leading spaces and dots
(.) probably in an attempt to better align the text. It is unreliable
because debug traces include function names and line numbers, which
introduce random offsets. Remove these characters.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: fix unwind in PSCI

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

core: add matches operation to mobj_paged_ops

Adds the matches operation to mobj_paged_ops in order to correctly
classify paged MOBJs.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Te

core: add matches operation to mobj_paged_ops

Adds the matches operation to mobj_paged_ops in order to correctly
classify paged MOBJs.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add matches operation to mobj_reg_shm_ops

Adds the matches operation to mobj_reg_shm_ops in order to correctly
classify reg_shm MOBJs.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.o

core: add matches operation to mobj_reg_shm_ops

Adds the matches operation to mobj_reg_shm_ops in order to correctly
classify reg_shm MOBJs.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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