core: remove CFG_ prefix from CFG_TEE_LOAD_ADDR

TEE_LOAD_ADDR is now local to source files. It is set to CFG_TEE_LOAD_ADDR
value if defined only for the platforms that previously allowed build
to ov

core: remove CFG_ prefix from CFG_TEE_LOAD_ADDR

TEE_LOAD_ADDR is now local to source files. It is set to CFG_TEE_LOAD_ADDR
value if defined only for the platforms that previously allowed build
to override the value. Few platform did hardcod CFG_TEE_LOAD_ADDR, this
change preserve these configurations.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: remove CFG_ prefix from CFG_SHMEM_START/_SIZE

Almost platform currently define these directives from within the
source code, through platform_config.h. These values do not need to
be configura

core: remove CFG_ prefix from CFG_SHMEM_START/_SIZE

Almost platform currently define these directives from within the
source code, through platform_config.h. These values do not need to
be configuration directive with the CFG_ prefix.

This change renames the CFG_SHMEM_xxx into TEE_SHMEM_xxx so that they
do not mess with the platform configuration directives. Yet, the old
CFG_SHMEM_START/SIZE directives can still be used by platform_config.h
to set TEE_SHMEM_START/SIZE if the platform supports it (i.e plat-stm).

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: remove CFG_ prefix from TA_RAM_START/TA_RAM_SIZE

Almost platform currently define these directives from within the
source code, through platform_config.h. These values do not need to
be config

core: remove CFG_ prefix from TA_RAM_START/TA_RAM_SIZE

Almost platform currently define these directives from within the
source code, through platform_config.h. These values do not need to
be configuration directive with the CFG_ prefix.

This change renames these macros so that they do not mess with the
platform configuration directives.

Old macro label New macro label
CFG_TA_RAM_START TA_RAM_START
CFG_TA_RAM_SIZE TA_RAM_SIZE

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: remove CFG_ prefix from TEE_RAM_START/VA_SIZE/PH_SIZE

Almost platform currently define these directives from within the
source code, through platform_config.h. These values do not need to
be c

core: remove CFG_ prefix from TEE_RAM_START/VA_SIZE/PH_SIZE

Almost platform currently define these directives from within the
source code, through platform_config.h. These values do not need to
be configuration directive with the CFG_ prefix.

This change renames these macros so that they do not mess with the
platform configuration directives.

Old macro label New macro label
CFG_TEE_RAM_START TEE_RAM_START
CFG_TEE_RAM_VA_SIZE TEE_RAM_VA_SIZE
CFG_TEE_RAM_PH_SIZE TEE_RAM_PH_SIZE

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-poplar: fix comments layout that hurts checkpatch

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

core: split SDP memory CFG_ and non-CFG_ configuration directives

This change aim at removing definition of CFG_ directive (here related
to SDP) from the platform_config.h files.

CFG_TEE_SDP_MEM_BA

core: split SDP memory CFG_ and non-CFG_ configuration directives

This change aim at removing definition of CFG_ directive (here related
to SDP) from the platform_config.h files.

CFG_TEE_SDP_MEM_BASE/_SIZE is a generic configuration directive to
register a SDP memory.

Some platforms define a SDP test memory when SDP is enable. This SDP
memory is located at the end of the TA_RAM. Introduce platform settings
TEE_SDP_TEST_MEM_BASE/_SIZE to register a SDP test buffer, independently
from the generic CFG_TEE_SDP_MEM_BASE/_SIZE.

Platforms marvel, stm, ti and vexpress updated.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: mmu: lpae: copy table of actual primary core

SOC has configurable core settings (e.g., Juno) does not
take core-0 as primary core. Copying mapping table of core-0
to other cores causes boot fa

core: mmu: lpae: copy table of actual primary core

SOC has configurable core settings (e.g., Juno) does not
take core-0 as primary core. Copying mapping table of core-0
to other cores causes boot failure on such configured SOC.
Fix this problem by taking mapping table of actual primary
core as copy source.

Signed-off-by: Ken Liu <ken.liu@arm.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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qemu: discard legacy bios mailbox and support arm-tf boot scheme

Replace the unused bios_qemu_tz_arm mailbox for waking secondary boot
cores with the mailbox used by the Arm trusted firmware.

Signe

qemu: discard legacy bios mailbox and support arm-tf boot scheme

Replace the unused bios_qemu_tz_arm mailbox for waking secondary boot
cores with the mailbox used by the Arm trusted firmware.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org>

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qemu_virt: move core location to match qemu_armv8

Moving qemu_virt core to the same location as the core for qemu_armv8
allows to use the same arm-trusted-firmware configuration for ARMv7
and ARMv8

qemu_virt: move core location to match qemu_armv8

Moving qemu_virt core to the same location as the core for qemu_armv8
allows to use the same arm-trusted-firmware configuration for ARMv7
and ARMv8 Qemu support.

Qemu_virt Kasan offset is updated since new memory layout.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: 32bit generic entry executes in cpu Supervisor mode.

This change aims at supporting some bootloaders as the Aarch32
Arm trusted firmware that may boot cores in Monitor mode.

Signed-off-by: Et

core: 32bit generic entry executes in cpu Supervisor mode.

This change aims at supporting some bootloaders as the Aarch32
Arm trusted firmware that may boot cores in Monitor mode.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: generic_entry_a64.S: use adr_l to allow bigger data sections

Fixes the following linker errors which happens when adding a big
global array of data:

.../generic_entry_a64.o: In function `_sta

core: generic_entry_a64.S: use adr_l to allow bigger data sections

Fixes the following linker errors which happens when adding a big
global array of data:

.../generic_entry_a64.o: In function `_start`:
.../generic_entry_a64.S:95:(.text._start+0x30): relocation truncated to fit: R_AARCH64_ADR_PREL_LO21 against symbol `__bss_start` defined in .bss.__malloc_spinlock section in all_objs.o
.../generic_entry_a64.S:96:(.text._start+0x34): relocation truncated to fit: R_AARCH64_ADR_PREL_LO21 against symbol `__bss_end` defined in .bss.__malloc_spinlock section in all_objs.o
.../generic_entry_a64.o: In function `clear_bss`:
.../generic_entry_a64.S:108:(.text._start+0x84): relocation truncated to fit: R_AARCH64_ADR_PREL_LO21 against symbol `__text_start` defined in .bss.__malloc_spinlock section in all_objs.o
.../generic_entry_a64.S:139:(.text._start+0xc4): relocation truncated to fit: R_AARCH64_ADR_PREL_LO21 against symbol `__text_start` defined in .bss.__malloc_spinlock section in all_objs.o

The root cause is the 'adr x0, symbol' instructions. They generate a
relocation of type R_AARCH64_ADR_PREL_LO21, therefore 'symbol' can
only be +/-1MB away from the current PC (otherwise the linker emits the
above error). The problem is, in _start() and clear_bss() there is no
guarantee that the referenced symbols are in the allowed range.

The linker script core/arch/arm/kernel/link_dummy.ld, which is used
to generate all_objs.o, places __bss_start, __bss_end, __text_start
etc. at the end of the binary. The _start() and clear_bss() functions,
on the other hand, are near the start. If the total size of the binary
is sufficiently increased (for instance by adding global data), the
error will occur.

The __text_start error could probably be avoided by modifying
link_dummy.ld -- the actual location of the __* symbols does not matter
much in this phase of the build. However, the references to __bss_start
and __bss_end are still likely to be problematic in the final link
phase, because .bss can very well be more than 1MB away from .text
(with .rodata and .data between them).

So, let's use the adr_l macro which splits 'adr x0, symbol' in two
steps: 'adrp x0, symbol' (which generates a relocation of type
R_AARCH64_ADR_PREL_PG_HI21 for the 4K page offset) followed by
'add x0, x0, :lo12:symbol' (which generates a R_AARCH64_ADD_ABS_LO12
relocation for the offset into the page). The accessible range becomes
+/- 4GB.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reported-by: Guanchao Liang <liangguanchao1@huawei.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm64: add adr_l assembly macro

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

plat-ti: Restore GIC context on resume

The resume path may need to re-setup the GIC. This is cleared in
some suspend paths and so should be restored.

Signed-off-by: Andrew F. Davis <afd@ti.com>

hikey: register additional dyn shm

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

hikey: fix typo

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

core: calculate size of special rx map at EL0

Calculate the required size the read-only executable mapping of kernel
mode code while in user mode (EL0) instead of the old hard coded 8k
size.

Review

core: calculate size of special rx map at EL0

Calculate the required size the read-only executable mapping of kernel
mode code while in user mode (EL0) instead of the old hard coded 8k
size.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm64: use SMCCC_ARCH_WORKAROUND_1

Use SMCCC_ARCH_WORKAROUND_1 to implement CVE-2017-5715 in AArch64.
Previous workarounds for CVE-2017-5715 haven't been fully effective.

Fixes CVE-2017-5715

core: arm64: use SMCCC_ARCH_WORKAROUND_1

Use SMCCC_ARCH_WORKAROUND_1 to implement CVE-2017-5715 in AArch64.
Previous workarounds for CVE-2017-5715 haven't been fully effective.

Fixes CVE-2017-5715
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey960)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm64: provide special rw kernel page at EL0

Provide a special kernel read/write mapped page while in EL0 if compiled
with CFG_CORE_UNMAP_CORE_AT_EL0 and CFG_CORE_WORKAROUND_SPECTRE_BP_SEC.
Th

core: arm64: provide special rw kernel page at EL0

Provide a special kernel read/write mapped page while in EL0 if compiled
with CFG_CORE_UNMAP_CORE_AT_EL0 and CFG_CORE_WORKAROUND_SPECTRE_BP_SEC.
This page will later be used as a temporary replacement of
thread_core_local. thread_core_local is not completely replaced, the new
memory is only used for temporary storage of registers via the stack
pointer.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: add thread_smc()

Adds thread_smc() for simple SMC calls to dispatcher in EL3

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@l

core: arm: add thread_smc()

Adds thread_smc() for simple SMC calls to dispatcher in EL3

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add smccc.h

Adds <smccc.h> introducing new features in SMC calling convention v1.1

See also
Link: https://developer.arm.com/-/media/developer/pdf/ARM_DEN_0070A_Firmware_interfaces_for_mitigat

core: add smccc.h

Adds <smccc.h> introducing new features in SMC calling convention v1.1

See also
Link: https://developer.arm.com/-/media/developer/pdf/ARM_DEN_0070A_Firmware_interfaces_for_mitigating_CVE-2017-5715.pdf

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core/arch/arm/pta/sdp_pta.c: Fix compile error

There will be a "format" compile error when using gcc 6.2.1.
It is not allowed to change type from "struct" to "void *"
in gcc 6.2.1.

Signed-off-by: E

core/arch/arm/pta/sdp_pta.c: Fix compile error

There will be a "format" compile error when using gcc 6.2.1.
It is not allowed to change type from "struct" to "void *"
in gcc 6.2.1.

Signed-off-by: Edison Ai <edison.ai@arm.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: minor cleanup related to pseudo TAs

tee_kta_trace.h is unused and useless.
Reword "static TA" into "pseudo TA" in comments.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Revie

core: minor cleanup related to pseudo TAs

tee_kta_trace.h is unused and useless.
Reword "static TA" into "pseudo TA" in comments.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: deprecate TA property flags EXEC_DDR and USER_MODE

TA property flags TA_FLAG_EXEC_DDR and TA_FLAG_USER_MODE were
not really useful in the OP-TEE and now they are meaningless.

Define the mask

core: deprecate TA property flags EXEC_DDR and USER_MODE

TA property flags TA_FLAG_EXEC_DDR and TA_FLAG_USER_MODE were
not really useful in the OP-TEE and now they are meaningless.

Define the mask of flags a TA may pretend to and assert loaded
TAs do not expect flags set outside of the defined supported bit
flags.

Fix gmon.h against duplicate round macros.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: deprecate TA_FLAG_USER_MODE

Differentiate user TA and pseudo TA contexts based on the TA operation
structure registered in the TA context and specific to each.

Change gprof pTA to test uTA at

core: deprecate TA_FLAG_USER_MODE

Differentiate user TA and pseudo TA contexts based on the TA operation
structure registered in the TA context and specific to each.

Change gprof pTA to test uTA attribute when targeting uTA client instead
of testing !pTA attribute.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-ls: Add support for fetching SSK from armv8 platform flavour.

- PLATFORM = ls-ls1046ardb, ls-ls1043ardb, ls-ls1012ardb

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Reviewed-by: Sumit

plat-ls: Add support for fetching SSK from armv8 platform flavour.

- PLATFORM = ls-ls1046ardb, ls-ls1043ardb, ls-ls1012ardb

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Reviewed-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
[jf: s/?=y/?= y/]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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