drivers: caam: implement NXP CAAM Driver - RSA

Add the NXP CAAM drivers:
- Asymmetric RSA:
- Encrypt/Decrypt
- Sign/Verify
- Mathematical operation XOR (mod N)

Signed-off-by: Cedric Neveux <cedric.

drivers: caam: implement NXP CAAM Driver - RSA

Add the NXP CAAM drivers:
- Asymmetric RSA:
- Encrypt/Decrypt
- Sign/Verify
- Mathematical operation XOR (mod N)

Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: crypto: generic resources for crypto device driver - RSA

TEE Crypto generic APIs to HW driver interface

Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Acked-by: Jens Wiklander <jens.

drivers: crypto: generic resources for crypto device driver - RSA

TEE Crypto generic APIs to HW driver interface

Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: caam: change CAAM debug trace method

Change the method to enable the CAAM debug.
Split the debug compilation 32 bits word to 3x32 bits words, one for the
trace, one for the descriptor dump

drivers: caam: change CAAM debug trace method

Change the method to enable the CAAM debug.
Split the debug compilation 32 bits word to 3x32 bits words, one for the
trace, one for the descriptor dump and one for the buffer dump.

Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: use adr_l to allow bigger data sections

Compiling for NXP lx2160ardb with debug enabled fails with:

$ make -j32 CFG_ARM64_core=y PLATFORM=ls-lx2160ardb DEBUG=1
...
LD out/arm-plat-l

core: use adr_l to allow bigger data sections

Compiling for NXP lx2160ardb with debug enabled fails with:

$ make -j32 CFG_ARM64_core=y PLATFORM=ls-lx2160ardb DEBUG=1
...
LD out/arm-plat-ls/core/all_objs.o
out/arm-plat-ls/core/arch/arm/kernel/thread_a64.o: in function `el0_sync_a64':
core/arch/arm/kernel/thread_a64.S:271:(.text.thread_excp_vect+0x424): relocation truncated to fit: R_AARCH64_ADR_PREL_LO21 against symbol `thread_user_kcode_offset' defined in COMMON section in out/arm-plat-ls/core/arch/arm/kernel/thread.o
core/arch/arm/kernel/thread_a64.S:271:(.text.thread_excp_vect+0x43c): relocation truncated to fit: R_AARCH64_ADR_PREL_LO21 against symbol `thread_user_kdata_sp_offset' defined in COMMON section in out/arm-plat-ls/core/arch/arm/kernel/thread.o
out/arm-plat-ls/core/arch/arm/kernel/thread_a64.o: in function `el0_irq_a64':
core/arch/arm/kernel/thread_a64.S:283:(.text.thread_excp_vect+0x4a4): relocation truncated to fit: R_AARCH64_ADR_PREL_LO21 against symbol `thread_user_kcode_offset' defined in COMMON section in out/arm-plat-ls/core/arch/arm/kernel/thread.o
core/arch/arm/kernel/thread_a64.S:283:(.text.thread_excp_vect+0x4bc): relocation truncated to fit: R_AARCH64_ADR_PREL_LO21 against symbol `thread_user_kdata_sp_offset' defined in COMMON section in out/arm-plat-ls/core/arch/arm/kernel/thread.o
out/arm-plat-ls/core/arch/arm/kernel/thread_a64.o: in function `el0_fiq_a64':
core/arch/arm/kernel/thread_a64.S:290:(.text.thread_excp_vect+0x524): relocation truncated to fit: R_AARCH64_ADR_PREL_LO21 against symbol `thread_user_kcode_offset' defined in COMMON section in out/arm-plat-ls/core/arch/arm/kernel/thread.o
core/arch/arm/kernel/thread_a64.S:290:(.text.thread_excp_vect+0x53c): relocation truncated to fit: R_AARCH64_ADR_PREL_LO21 against symbol `thread_user_kdata_sp_offset' defined in COMMON section in out/arm-plat-ls/core/arch/arm/kernel/thread.o
out/arm-plat-ls/core/arch/arm/kernel/thread_a64.o: in function `el0_sync_a32':
core/arch/arm/kernel/thread_a64.S:306:(.text.thread_excp_vect+0x624): relocation truncated to fit: R_AARCH64_ADR_PREL_LO21 against symbol `thread_user_kcode_offset' defined in COMMON section in out/arm-plat-ls/core/arch/arm/kernel/thread.o
core/arch/arm/kernel/thread_a64.S:306:(.text.thread_excp_vect+0x63c): relocation truncated to fit: R_AARCH64_ADR_PREL_LO21 against symbol `thread_user_kdata_sp_offset' defined in COMMON section in out/arm-plat-ls/core/arch/arm/kernel/thread.o
out/arm-plat-ls/core/arch/arm/kernel/thread_a64.o: in function `el0_irq_a32':
core/arch/arm/kernel/thread_a64.S:318:(.text.thread_excp_vect+0x6a4): relocation truncated to fit: R_AARCH64_ADR_PREL_LO21 against symbol `thread_user_kcode_offset' defined in COMMON section in out/arm-plat-ls/core/arch/arm/kernel/thread.o
core/arch/arm/kernel/thread_a64.S:318:(.text.thread_excp_vect+0x6bc): relocation truncated to fit: R_AARCH64_ADR_PREL_LO21 against symbol `thread_user_kdata_sp_offset' defined in COMMON section in out/arm-plat-ls/core/arch/arm/kernel/thread.o
out/arm-plat-ls/core/arch/arm/kernel/thread_a64.o: in function `el0_fiq_a32':
core/arch/arm/kernel/thread_a64.S:325:(.text.thread_excp_vect+0x724): additional relocation overflows omitted from the output

So let's replace adr with adr_l and apply a similar fix as
commit 82d398c0e05c ("core: generic_entry_a64.S: use adr_l to allow
bigger data sections") suggests.

Suggested-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
[jf: reformat commit description]
Signed-off-by: Jerome Forissier <jerome@forissier.org>

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core: save_panic_stack(): make sure tsd is initialized

If a TA fails to load due to an assertion failure in ldelf, the user
stack might be inaccessible. save_panic_stack() detects this situation
but

core: save_panic_stack(): make sure tsd is initialized

If a TA fails to load due to an assertion failure in ldelf, the user
stack might be inaccessible. save_panic_stack() detects this situation
but fails to set abort information in the thread specific data (tsd).
As a result, the stack unwinding code can erroneously execute kernel
unwinding code and trigger an assertion:

E/TC:? 0 assertion 'thread_get_exceptions() & THREAD_EXCP_FOREIGN_INTR' failed at core/arch/arm/include/kernel/misc.h:22 <get_core_pos>

The fix consists in moving the tsd initialization above the user stack
accessibility check.

Suggested-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: exclude generic_boot_init_primary() from unpaged part

Excludes generic_boot_init_primary() from unpaged part and makes sure
it's still in the init part.

Reviewed-by: Jerome Forissier <jerome@

core: exclude generic_boot_init_primary() from unpaged part

Excludes generic_boot_init_primary() from unpaged part and makes sure
it's still in the init part.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: exclude core_init_mmu_map() from unpaged part

Excludes core_init_mmu_map() from unpaged part and makes sure it's still
in the init part.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
S

core: exclude core_init_mmu_map() from unpaged part

Excludes core_init_mmu_map() from unpaged part and makes sure it's still
in the init part.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: exclude get_aslr_seed() from unpaged part

Excludes get_aslr_seed() from unpaged part and makes sure it's still in
the init part.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-of

core: exclude get_aslr_seed() from unpaged part

Excludes get_aslr_seed() from unpaged part and makes sure it's still in
the init part.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: ree_fs_ta: fix bootstrap header size check

This change fix bootstrap header size check. Before it use
sizeof(bs_hdr) but bs_hdr is a struct pointer. Correct it
to sizeof(*bs_hdr)

Fixes: 18339

core: ree_fs_ta: fix bootstrap header size check

This change fix bootstrap header size check. Before it use
sizeof(bs_hdr) but bs_hdr is a struct pointer. Correct it
to sizeof(*bs_hdr)

Fixes: 183398139c9c ("core: enable rollback protection for REE-FS TAs")
Signed-off-by: Khoa Hoang <admin@khoahoang.com>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: mmu: fix check of memory physical end address

Correct test on memory physical end address that was not consistent
in use of core_mmu_check_end_pa().

This change fixes core_mmu_set_discovered_

core: mmu: fix check of memory physical end address

Correct test on memory physical end address that was not consistent
in use of core_mmu_check_end_pa().

This change fixes core_mmu_set_discovered_nsec_ddr() where
core_mmu_check_end_pa() was called with a byte length argument
decreased by one whereas it should provide the effective byte size
of the memory area.

This change fixes core_mmu_check_end_pa() so that it computes
the end address as start address plus byte size minus one to
obtain the inclusive end address core_mmu_check_max_pa() expects
as input argument.

Fixes: 4518cdc1ff64 ("core: arm64: introduce CFG_CORE_ARM64_PA_BITS")
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: add plat_rpmb_ready for i.MX6/7

For i.MX6/7 RPMB key writes should only be allowed if the device is in
the closed configuration and in the trusted or secure state.

Signed-off-by: Rouven

core: imx: add plat_rpmb_ready for i.MX6/7

For i.MX6/7 RPMB key writes should only be allowed if the device is in
the closed configuration and in the trusted or secure state.

Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Cedric Neveux <cedric.neveux@nxp.com>

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core: Add support to access a TPM event log in secure memory.

Support for OPTEE to be able to receive a TPM event log through
a DTB so it can forward it to a TA (such as a TPM service)
in order to e

core: Add support to access a TPM event log in secure memory.

Support for OPTEE to be able to receive a TPM event log through
a DTB so it can forward it to a TA (such as a TPM service)
in order to extend the measurements.

CFG_CORE_TPM_EVENT_LOG enables this feature.
CFG_TPM_LOG_BASE_ADDR hardcodes the phys address of the event log
in case CFG_DT is not set.
CFG_TPM_MAX_LOG_SIZE harcodes the size of the event log in case
CFG_DT is not set.

When this feature is enabled, the PTA_SYSTEM_GET_TPM_EVENT_LOG
command is available to any TA.

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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imx: enable CFG_TZC380 for supported SoCs

Enable the region autoconfiguration for supported SoCs by default.

Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Reviewed-by: Clement Faur

imx: enable CFG_TZC380 for supported SoCs

Enable the region autoconfiguration for supported SoCs by default.

Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Reviewed-by: Clement Faure <clement.faure@nxp.com>

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imx: tzc380: move to driver_init() initcall

Instead of configuring the tzc380 in plat_primary_init_early, handle the
configuration similar to all other drivers by using a driver_init()
initcall.

Si

imx: tzc380: move to driver_init() initcall

Instead of configuring the tzc380 in plat_primary_init_early, handle the
configuration similar to all other drivers by using a driver_init()
initcall.

Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Reviewed-by: Clement Faure <clement.faure@nxp.com>

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imx: tzc380: dump state

Instead of only showing the access register, dump the whole
configuration state of the TZC380.

Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Reviewed-by: Cl

imx: tzc380: dump state

Instead of only showing the access register, dump the whole
configuration state of the TZC380.

Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Reviewed-by: Clement Faure <clement.faure@nxp.com>

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imx: tzc380: perform a region lockdown

Lockdown the region configuration after the auto configuration of
regions.

Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Reviewed-by: Clement

imx: tzc380: perform a region lockdown

Lockdown the region configuration after the auto configuration of
regions.

Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Reviewed-by: Clement Faure <clement.faure@nxp.com>

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core: plat-ls: Fix gic offsets for platform LS1046ARDB

Fix GIC offsets for platform LS1046ARDB

Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com>
Signed-off-by: Sahil Malhotra <sahil.malhotra@n

core: plat-ls: Fix gic offsets for platform LS1046ARDB

Fix GIC offsets for platform LS1046ARDB

Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com>
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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core: plat-ls: Enable caam support for platform LS1046ARDB

Enable CAAM support for platform LS1046ARDB

Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com>
Signed-off-by: Sahil Malhotra <sahil.ma

core: plat-ls: Enable caam support for platform LS1046ARDB

Enable CAAM support for platform LS1046ARDB

Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com>
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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plat-stm32mp1: fix platform regarding ASLR

Remove assertion on MMU disable state in console_init() since
the function can be called from generic_boot.c after MMU is
enabled when ASLR support in Core

plat-stm32mp1: fix platform regarding ASLR

Remove assertion on MMU disable state in console_init() since
the function can be called from generic_boot.c after MMU is
enabled when ASLR support in Core is enabled.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: enable dynamic shared memory

Register dynamic shared memory allowed by the platform that is
the DRAM address ranges below and above the secure DRAM (TZDRAM).

Signed-off-by: Etienne C

plat-stm32mp1: enable dynamic shared memory

Register dynamic shared memory allowed by the platform that is
the DRAM address ranges below and above the secure DRAM (TZDRAM).

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: aslr: fix cached_mem_end update

Fix update of cache_mem_end that corrupts CPU register R4 used to
store a boot argument in Aarch32.

Fixes: 487fd6828322 ("core: aslr: apply load offset to cach

core: aslr: fix cached_mem_end update

Fix update of cache_mem_end that corrupts CPU register R4 used to
store a boot argument in Aarch32.

Fixes: 487fd6828322 ("core: aslr: apply load offset to cached_mem_end")
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: generic_entry: fix aarch32 lpae mmu configuration

Correct configuration of the MMU registers TTBR0/TTBR1 for
Aarch32/LPAE that omitted to load a zero value in the 32bit upper
part of the regis

core: generic_entry: fix aarch32 lpae mmu configuration

Correct configuration of the MMU registers TTBR0/TTBR1 for
Aarch32/LPAE that omitted to load a zero value in the 32bit upper
part of the registers.

Fixes: 520860f658be ("core: generic_entry: add enable_mmu()")
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: aslr: set tee_svc_uref_base to VCORE_START_VA

tee_svc_uref_base was using hardcoded TEE_TEXT_VA_START define value.
This value isn't valid after TEE core relocation. Switch to use
VCORE_START_

core: aslr: set tee_svc_uref_base to VCORE_START_VA

tee_svc_uref_base was using hardcoded TEE_TEXT_VA_START define value.
This value isn't valid after TEE core relocation. Switch to use
VCORE_START_VA which is linker variable that should get update after
relocation code executed.

Signed-off-by: Khoa Hoang <admin@khoahoang.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: aslr: apply load offset to cached_mem_end

cached_mem_end was calculated before relocation and use later for D$
flush. Add code to update cached_mem_end with ASLR load offset.

Signed-off-by: K

core: aslr: apply load offset to cached_mem_end

cached_mem_end was calculated before relocation and use later for D$
flush. Add code to update cached_mem_end with ASLR load offset.

Signed-off-by: Khoa Hoang <admin@khoahoang.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: imx: add imx6ulzevk platform flavor

Add imx6ulzevk platform flavor.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>