1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2017-2018, STMicroelectronics 4 * Copyright (c) 2016-2018, Linaro Limited 5 */ 6 7 #include <boot_api.h> 8 #include <console.h> 9 #include <drivers/gic.h> 10 #include <drivers/stm32_etzpc.h> 11 #include <drivers/stm32mp1_etzpc.h> 12 #include <drivers/stm32_uart.h> 13 #include <dt-bindings/clock/stm32mp1-clks.h> 14 #include <kernel/dt.h> 15 #include <kernel/generic_boot.h> 16 #include <kernel/interrupt.h> 17 #include <kernel/misc.h> 18 #include <kernel/panic.h> 19 #include <kernel/pm_stubs.h> 20 #include <kernel/spinlock.h> 21 #include <mm/core_memprot.h> 22 #include <platform_config.h> 23 #include <sm/psci.h> 24 #include <stm32_util.h> 25 #include <tee/entry_fast.h> 26 #include <tee/entry_std.h> 27 #include <trace.h> 28 29 #ifdef CFG_WITH_NSEC_GPIOS 30 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, GPIOS_NSEC_BASE, GPIOS_NSEC_SIZE); 31 #endif 32 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, I2C4_BASE, SMALL_PAGE_SIZE); 33 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, I2C6_BASE, SMALL_PAGE_SIZE); 34 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, RNG1_BASE, SMALL_PAGE_SIZE); 35 #ifdef CFG_WITH_NSEC_UARTS 36 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART1_BASE, SMALL_PAGE_SIZE); 37 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART2_BASE, SMALL_PAGE_SIZE); 38 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART3_BASE, SMALL_PAGE_SIZE); 39 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART4_BASE, SMALL_PAGE_SIZE); 40 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART5_BASE, SMALL_PAGE_SIZE); 41 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART6_BASE, SMALL_PAGE_SIZE); 42 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART7_BASE, SMALL_PAGE_SIZE); 43 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART8_BASE, SMALL_PAGE_SIZE); 44 #endif 45 46 register_phys_mem_pgdir(MEM_AREA_IO_SEC, BSEC_BASE, SMALL_PAGE_SIZE); 47 register_phys_mem_pgdir(MEM_AREA_IO_SEC, ETZPC_BASE, SMALL_PAGE_SIZE); 48 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, GIC_SIZE); 49 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GPIOZ_BASE, SMALL_PAGE_SIZE); 50 register_phys_mem_pgdir(MEM_AREA_IO_SEC, I2C4_BASE, SMALL_PAGE_SIZE); 51 register_phys_mem_pgdir(MEM_AREA_IO_SEC, I2C6_BASE, SMALL_PAGE_SIZE); 52 register_phys_mem_pgdir(MEM_AREA_IO_SEC, PWR_BASE, SMALL_PAGE_SIZE); 53 register_phys_mem_pgdir(MEM_AREA_IO_SEC, RCC_BASE, SMALL_PAGE_SIZE); 54 register_phys_mem_pgdir(MEM_AREA_IO_SEC, RNG1_BASE, SMALL_PAGE_SIZE); 55 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TAMP_BASE, SMALL_PAGE_SIZE); 56 register_phys_mem_pgdir(MEM_AREA_IO_SEC, USART1_BASE, SMALL_PAGE_SIZE); 57 58 #if DDR_BASE < CFG_TZDRAM_START 59 register_dynamic_shm(DDR_BASE, CFG_TZDRAM_START - DDR_BASE); 60 #endif 61 62 #define DRAM_END (DDR_BASE + CFG_DRAM_SIZE) 63 #define TZDRAM_END (CFG_TZDRAM_START + CFG_TZDRAM_SIZE) 64 65 #if DRAM_END > TZDRAM_END 66 register_dynamic_shm(TZDRAM_END, DRAM_END - TZDRAM_END); 67 #endif 68 69 static const struct thread_handlers handlers = { 70 .cpu_on = pm_panic, 71 .cpu_off = pm_panic, 72 .cpu_suspend = pm_panic, 73 .cpu_resume = pm_panic, 74 .system_off = pm_panic, 75 .system_reset = pm_panic, 76 }; 77 78 const struct thread_handlers *generic_boot_get_handlers(void) 79 { 80 return &handlers; 81 } 82 83 #define _ID2STR(id) (#id) 84 #define ID2STR(id) _ID2STR(id) 85 86 static TEE_Result platform_banner(void) 87 { 88 #ifdef CFG_EMBED_DTB 89 IMSG("Platform stm32mp1: flavor %s - DT %s", 90 ID2STR(PLATFORM_FLAVOR), 91 ID2STR(CFG_EMBED_DTB_SOURCE_FILE)); 92 #else 93 IMSG("Platform stm32mp1: flavor %s - no device tree", 94 ID2STR(PLATFORM_FLAVOR)); 95 #endif 96 97 return TEE_SUCCESS; 98 } 99 service_init(platform_banner); 100 101 /* 102 * Console 103 * 104 * CFG_STM32_EARLY_CONSOLE_UART specifies the ID of the UART used for 105 * trace console. Value 0 disables the early console. 106 * 107 * We cannot use the generic serial_console support since probing 108 * the console requires the platform clock driver to be already 109 * up and ready which is done only once service_init are completed. 110 */ 111 static struct stm32_uart_pdata console_data; 112 113 void console_init(void) 114 { 115 /* Early console initialization before MMU setup */ 116 struct uart { 117 paddr_t pa; 118 bool secure; 119 } uarts[] = { 120 [0] = { .pa = 0 }, 121 [1] = { .pa = USART1_BASE, .secure = true, }, 122 [2] = { .pa = USART2_BASE, .secure = false, }, 123 [3] = { .pa = USART3_BASE, .secure = false, }, 124 [4] = { .pa = UART4_BASE, .secure = false, }, 125 [5] = { .pa = UART5_BASE, .secure = false, }, 126 [6] = { .pa = USART6_BASE, .secure = false, }, 127 [7] = { .pa = UART7_BASE, .secure = false, }, 128 [8] = { .pa = UART8_BASE, .secure = false, }, 129 }; 130 131 COMPILE_TIME_ASSERT(ARRAY_SIZE(uarts) > CFG_STM32_EARLY_CONSOLE_UART); 132 assert(!cpu_mmu_enabled()); 133 134 if (!uarts[CFG_STM32_EARLY_CONSOLE_UART].pa) 135 return; 136 137 /* No clock yet bound to the UART console */ 138 console_data.clock = DT_INFO_INVALID_CLOCK; 139 140 console_data.secure = uarts[CFG_STM32_EARLY_CONSOLE_UART].secure; 141 stm32_uart_init(&console_data, uarts[CFG_STM32_EARLY_CONSOLE_UART].pa); 142 143 register_serial_console(&console_data.chip); 144 145 IMSG("Early console on UART#%u", CFG_STM32_EARLY_CONSOLE_UART); 146 } 147 148 #ifdef CFG_DT 149 static TEE_Result init_console_from_dt(void) 150 { 151 struct stm32_uart_pdata *pd = NULL; 152 void *fdt = NULL; 153 int node = 0; 154 TEE_Result res = TEE_ERROR_GENERIC; 155 156 fdt = get_embedded_dt(); 157 res = get_console_node_from_dt(fdt, &node, NULL, NULL); 158 if (res == TEE_ERROR_ITEM_NOT_FOUND) { 159 fdt = get_external_dt(); 160 res = get_console_node_from_dt(fdt, &node, NULL, NULL); 161 if (res == TEE_ERROR_ITEM_NOT_FOUND) 162 return TEE_SUCCESS; 163 if (res != TEE_SUCCESS) 164 return res; 165 } 166 167 pd = stm32_uart_init_from_dt_node(fdt, node); 168 if (!pd) { 169 IMSG("DTB disables console"); 170 register_serial_console(NULL); 171 return TEE_SUCCESS; 172 } 173 174 /* Replace early console with the new one */ 175 console_flush(); 176 console_data = *pd; 177 free(pd); 178 register_serial_console(&console_data.chip); 179 IMSG("DTB enables console (%ssecure)", pd->secure ? "" : "non-"); 180 181 return TEE_SUCCESS; 182 } 183 184 /* Probe console from DT once clock inits (service init level) are completed */ 185 service_init_late(init_console_from_dt); 186 #endif 187 188 /* 189 * GIC init, used also for primary/secondary boot core wake completion 190 */ 191 static struct gic_data gic_data; 192 193 void itr_core_handler(void) 194 { 195 gic_it_handle(&gic_data); 196 } 197 198 void main_init_gic(void) 199 { 200 assert(cpu_mmu_enabled()); 201 202 gic_init(&gic_data, get_gicc_base(), get_gicd_base()); 203 itr_init(&gic_data.chip); 204 205 stm32mp_register_online_cpu(); 206 } 207 208 void main_secondary_init_gic(void) 209 { 210 gic_cpu_init(&gic_data); 211 212 stm32mp_register_online_cpu(); 213 } 214 215 #ifndef CFG_EMBED_DTB 216 static TEE_Result init_stm32mp1_drivers(void) 217 { 218 /* Without secure DTB support, some drivers must be inited */ 219 stm32_etzpc_init(ETZPC_BASE); 220 221 return TEE_SUCCESS; 222 } 223 driver_init(init_stm32mp1_drivers); 224 #endif /*!CFG_EMBED_DTB*/ 225 226 /* Platform initializations once all drivers are ready */ 227 static TEE_Result init_late_stm32mp1_drivers(void) 228 { 229 /* Secure internal memories for the platform, once ETZPC is ready */ 230 etzpc_configure_tzma(0, ETZPC_TZMA_ALL_SECURE); 231 etzpc_lock_tzma(0); 232 etzpc_configure_tzma(1, ETZPC_TZMA_ALL_SECURE); 233 etzpc_lock_tzma(1); 234 235 /* Static secure DECPROT configuration */ 236 etzpc_configure_decprot(STM32MP1_ETZPC_STGENC_ID, ETZPC_DECPROT_S_RW); 237 etzpc_configure_decprot(STM32MP1_ETZPC_BKPSRAM_ID, ETZPC_DECPROT_S_RW); 238 etzpc_configure_decprot(STM32MP1_ETZPC_IWDG1_ID, ETZPC_DECPROT_S_RW); 239 etzpc_configure_decprot(STM32MP1_ETZPC_DDRCTRL_ID, ETZPC_DECPROT_S_RW); 240 etzpc_configure_decprot(STM32MP1_ETZPC_DDRPHYC_ID, ETZPC_DECPROT_S_RW); 241 etzpc_lock_decprot(STM32MP1_ETZPC_STGENC_ID); 242 etzpc_lock_decprot(STM32MP1_ETZPC_BKPSRAM_ID); 243 etzpc_lock_decprot(STM32MP1_ETZPC_IWDG1_ID); 244 etzpc_lock_decprot(STM32MP1_ETZPC_DDRCTRL_ID); 245 etzpc_lock_decprot(STM32MP1_ETZPC_DDRPHYC_ID); 246 /* Static non-secure DECPROT configuration */ 247 etzpc_configure_decprot(STM32MP1_ETZPC_I2C4_ID, ETZPC_DECPROT_NS_RW); 248 etzpc_configure_decprot(STM32MP1_ETZPC_RNG1_ID, ETZPC_DECPROT_NS_RW); 249 etzpc_configure_decprot(STM32MP1_ETZPC_HASH1_ID, ETZPC_DECPROT_NS_RW); 250 etzpc_configure_decprot(STM32MP1_ETZPC_CRYP1_ID, ETZPC_DECPROT_NS_RW); 251 /* Release few resource to the non-secure world */ 252 etzpc_configure_decprot(STM32MP1_ETZPC_USART1_ID, ETZPC_DECPROT_NS_RW); 253 etzpc_configure_decprot(STM32MP1_ETZPC_SPI6_ID, ETZPC_DECPROT_NS_RW); 254 etzpc_configure_decprot(STM32MP1_ETZPC_I2C6_ID, ETZPC_DECPROT_NS_RW); 255 256 return TEE_SUCCESS; 257 } 258 driver_init_late(init_late_stm32mp1_drivers); 259 260 vaddr_t get_gicc_base(void) 261 { 262 struct io_pa_va base = { .pa = GIC_BASE + GICC_OFFSET }; 263 264 return io_pa_or_va_secure(&base); 265 } 266 267 vaddr_t get_gicd_base(void) 268 { 269 struct io_pa_va base = { .pa = GIC_BASE + GICD_OFFSET }; 270 271 return io_pa_or_va_secure(&base); 272 } 273 274 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg) 275 { 276 cfg->base = BSEC_BASE; 277 cfg->upper_start = STM32MP1_UPPER_OTP_START; 278 cfg->max_id = STM32MP1_OTP_MAX_ID; 279 cfg->closed_device_id = DATA0_OTP; 280 cfg->closed_device_position = DATA0_OTP_SECURED_POS; 281 } 282 283 bool stm32mp_is_closed_device(void) 284 { 285 uint32_t otp = 0; 286 TEE_Result result = TEE_ERROR_GENERIC; 287 288 /* Non closed_device platform expects fuse well programmed to 0 */ 289 result = stm32_bsec_shadow_read_otp(&otp, DATA0_OTP); 290 if (!result && !(otp & BIT(DATA0_OTP_SECURED_POS))) 291 return false; 292 293 return true; 294 } 295 296 uint32_t may_spin_lock(unsigned int *lock) 297 { 298 if (!lock || !cpu_mmu_enabled()) 299 return 0; 300 301 return cpu_spin_lock_xsave(lock); 302 } 303 304 void may_spin_unlock(unsigned int *lock, uint32_t exceptions) 305 { 306 if (!lock || !cpu_mmu_enabled()) 307 return; 308 309 cpu_spin_unlock_xrestore(lock, exceptions); 310 } 311 312 static vaddr_t stm32_tamp_base(void) 313 { 314 static struct io_pa_va base = { .pa = TAMP_BASE }; 315 316 return io_pa_or_va_secure(&base); 317 } 318 319 static vaddr_t bkpreg_base(void) 320 { 321 return stm32_tamp_base() + TAMP_BKP_REGISTER_OFF; 322 } 323 324 vaddr_t stm32mp_bkpreg(unsigned int idx) 325 { 326 return bkpreg_base() + (idx * sizeof(uint32_t)); 327 } 328 329 vaddr_t stm32_get_gpio_bank_base(unsigned int bank) 330 { 331 static struct io_pa_va gpios_nsec_base = { .pa = GPIOS_NSEC_BASE }; 332 static struct io_pa_va gpioz_base = { .pa = GPIOZ_BASE }; 333 334 /* Get non-secure mapping address for GPIOZ */ 335 if (bank == GPIO_BANK_Z) 336 return io_pa_or_va_nsec(&gpioz_base); 337 338 COMPILE_TIME_ASSERT(GPIO_BANK_A == 0); 339 assert(bank <= GPIO_BANK_K); 340 341 return io_pa_or_va_nsec(&gpios_nsec_base) + (bank * GPIO_BANK_OFFSET); 342 } 343 344 unsigned int stm32_get_gpio_bank_offset(unsigned int bank) 345 { 346 if (bank == GPIO_BANK_Z) 347 return 0; 348 349 assert(bank <= GPIO_BANK_K); 350 return bank * GPIO_BANK_OFFSET; 351 } 352 353 unsigned int stm32_get_gpio_bank_clock(unsigned int bank) 354 { 355 if (bank == GPIO_BANK_Z) 356 return GPIOZ; 357 358 assert(bank <= GPIO_BANK_K); 359 return GPIOA + bank; 360 } 361