plat-rockchip: rk3588: Increase FDT Max Size to 384KiB

Increase the maximum size of the FDT to 384KiB to match the proposed
changes with Arm Trusted Firmware. This allows us to pass and parse
the FD

plat-rockchip: rk3588: Increase FDT Max Size to 384KiB

Increase the maximum size of the FDT to 384KiB to match the proposed
changes with Arm Trusted Firmware. This allows us to pass and parse
the FDT within OP-TEE. When doing this, we also need to allow OP-TEE
to detect the maximum PA bits so that allocating RAM above 4GiB does
not fail.

With these two changes, OP-TEE can parse and add the correct memory
nodes to the devicetree passed to it automatically.

Associated A-TF commit:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/34997

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-stm32mp1: conf: default enable HASH

Default enable HASH compilation.
Enable CFG_STM32_CRYPTO_DRIVERS if any crypto IP is compiled.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>

plat-stm32mp1: conf: default enable HASH

Default enable HASH compilation.
Enable CFG_STM32_CRYPTO_DRIVERS if any crypto IP is compiled.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: enable HASH on stm32mp135f-dk

Sets HASH peripheral status to okay.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

core: imx: enable ELE by default

Enable ELE by default on all ELE supported devices

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked

core: imx: enable ELE by default

Enable ELE by default on all ELE supported devices

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: ele: enable TRUST MU in OP-TEE for i.MX93-EVK/i.MX91-EVK

There is TRUST MU available on i.MX91 and i.MX93 platforms.

TRUST MU can be used to access some HW features of Edgelock Enclave whi

drivers: ele: enable TRUST MU in OP-TEE for i.MX93-EVK/i.MX91-EVK

There is TRUST MU available on i.MX91 and i.MX93 platforms.

TRUST MU can be used to access some HW features of Edgelock Enclave which
Normal MU cannot, but for now it is configured to be used to communicate
with ELE FW.

So Kernel will use Normal MU and OP-TEE will use TRUST MU.

There is special setup needed to write to Trust MU.
* First for TRUST-MU we must write a valid command to TR0 before we can
write any of the remaining registers, and TR15 is reserved for special
USM command.
* The CMD field for TR0 is bits 31:26 and must be greater than
the value of the watermark set in SCM_CR2[31:22]. Typically
if you just set the MSB (bit 31) its enough.
* SIZE must be programmed in bits 19:16 of TR0, we cannot write
TRn past the specified size in this bit field

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm: Remove dummy call_initcalls()

Remove call_initcalls() since we will remove prototype of this function.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jens Wiklander <jen

core: arm: Remove dummy call_initcalls()

Remove call_initcalls() since we will remove prototype of this function.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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core: fix debug event fault value for ARM32 with LPAE

According to ARM documentation, the debug event fault value is indeed
0b100010, which is 0x22, not 0x12. Fix this value in
core_mmu_get_fault_ty

core: fix debug event fault value for ARM32 with LPAE

According to ARM documentation, the debug event fault value is indeed
0b100010, which is 0x22, not 0x12. Fix this value in
core_mmu_get_fault_type().

Fixes: 0eff3e9bf016 ("arm32: Adds LPAE support")
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp2: add platform-specific abort handler

When a data abort occurs and its fault type is FAULT_TYPE_IGNORE, it
may be an abort generated by the SERC hardware block. Check if a
SERC Illegal

plat-stm32mp2: add platform-specific abort handler

When a data abort occurs and its fault type is FAULT_TYPE_IGNORE, it
may be an abort generated by the SERC hardware block. Check if a
SERC Illegal Access was caught and print the SERC register and panic()
if that is the case.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: add platform-specific abort handler

Platforms may have specific code to handle an abort when fault type
is FAULT_TYPE_IGNORE. Add plat_abort_handler() that can be overridden
at platform level

core: add platform-specific abort handler

Platforms may have specific code to handle an abort when fault type
is FAULT_TYPE_IGNORE. Add plat_abort_handler() that can be overridden
at platform level.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm: boot: mask native interrupts for virtualization

Native interrupts are prior to this patch unmasked while processing
initcalls. This is only permitted if the temporary stack isn't used.
Th

core: arm: boot: mask native interrupts for virtualization

Native interrupts are prior to this patch unmasked while processing
initcalls. This is only permitted if the temporary stack isn't used.
That's not true when CFG_NS_VIRTUALIZATION=y so fix this by only
unmasking when NS-virtualization isn't enabled.

Fixes: 259c34df294f ("core: arm: boot: enable native interrupts before initcalls")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm32: initialize secure monitor late

Initialize the secure monitor as late as possible before exiting to the
normal world. This is needed in later patches where the stacks aren't
statically a

core: arm32: initialize secure monitor late

Initialize the secure monitor as late as possible before exiting to the
normal world. This is needed in later patches where the stacks aren't
statically allocated.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm: refactor boot

Introduce CFG_BOOT_INIT_THREAD_CORE_LOCAL0 to indicate that
thread_core_local[0] is initialized before the boot_init_* functions are
called.

thread_init_core_local_stacks()

core: arm: refactor boot

Introduce CFG_BOOT_INIT_THREAD_CORE_LOCAL0 to indicate that
thread_core_local[0] is initialized before the boot_init_* functions are
called.

thread_init_core_local_stacks() and thread_init_thread_core_local() are
replaced by a new version of thread_init_thread_core_local() for
CFG_BOOT_INIT_THREAD_CORE_LOCAL0=y.

Move initialization of thread_core_local[] from very early to
boot_init_primary_late() where various DTBs containing run-time
configuration are available. This will be needed in later patches when
the number of configured cores can be read from DT or some other
run-time configuration.

Move the "OP-TEE version" print and following code from
boot_init_primary_late() to boot_init_primary_final()

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm: entry_a32.S: use ldr over adr

Load address of reset_vect_table using ldr r0, =reset_vect_table,
instead of adr r0 reset_vect_table to allow longer addressing range.

Signed-off-by: Jens W

core: arm: entry_a32.S: use ldr over adr

Load address of reset_vect_table using ldr r0, =reset_vect_table,
instead of adr r0 reset_vect_table to allow longer addressing range.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: mmu: Add dynamic VA regions' mapping to page table

When optee boots, the initial mapping for MEM_AREA_RES_VASPACE and
MEM_AREA_SHM_VASPACE should be added into page tables and replicated to
al

core: mmu: Add dynamic VA regions' mapping to page table

When optee boots, the initial mapping for MEM_AREA_RES_VASPACE and
MEM_AREA_SHM_VASPACE should be added into page tables and replicated to
all CPU cores too. This fixes an issue when the VA of
MEM_AREA_RES_VASPACE or MEM_AREA_SHM_VASPACE is not in a same 1GB region
with other memory regions.

Link: https://github.com/OP-TEE/optee_os/issues/7275
Signed-off-by: Mark Zhang <markz@nvidia.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-versal2: disable ARM CE v8.2

Disable the ARM CE v8.2 configuration since it is not available on the SoC.
Allow the ARM CE configuration to be overridden at build time while keeping
the default

plat-versal2: disable ARM CE v8.2

Disable the ARM CE v8.2 configuration since it is not available on the SoC.
Allow the ARM CE configuration to be overridden at build time while keeping
the default value enabled.

Signed-off-by: Amey Avinash Raghatate <AmeyAvinash.Raghatate@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: firewall: stm32_etzpc: remove header file

Remove stm32_etzpc.h header file that is not required since the
declared and defined resources are used internally in stm32_etzpc.c

By the way, al

drivers: firewall: stm32_etzpc: remove header file

Remove stm32_etzpc.h header file that is not required since the
declared and defined resources are used internally in stm32_etzpc.c

By the way, also remove inclusion of stm32mp15-etzpc.h DT bindings
header file from stm32_rng.c where it is not needed.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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core: arm: virt-aware FF-A thread_foreign_intr_exit()

thread_foreign_intr_exit() is called after the thread state has been
saved and the thread is suspended. With virtualization enabled
(CFG_NS_VIRT

core: arm: virt-aware FF-A thread_foreign_intr_exit()

thread_foreign_intr_exit() is called after the thread state has been
saved and the thread is suspended. With virtualization enabled
(CFG_NS_VIRTUALIZATION=y) the virt_unset_guest() is also called. After
this, the guests thread contexts aren't available any longer. For FF-A
thread_foreign_intr_exit() needs a few fields from the suspend threads
context so extract those before suspending the thread and pass them as
parameters for thread_foreign_intr_exit().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: ffa: __nex-annotate nexus rxtx buffer

Add __nex_bss and __nex_data annotations for the rxtx buffers used in a
configuration with SPMC at S-EL2 or EL3.

Signed-off-by: Jens Wiklander <jens.wikl

core: ffa: __nex-annotate nexus rxtx buffer

Add __nex_bss and __nex_data annotations for the rxtx buffers used in a
configuration with SPMC at S-EL2 or EL3.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: ffa: virt-aware spmc_init() for SPMC at S-EL2/EL3

Call virt_add_guest_spec_data() for the struct notif_vm_bitmap to make
it accessible from notif_send_async().

Signed-off-by: Jens Wiklander <

core: ffa: virt-aware spmc_init() for SPMC at S-EL2/EL3

Call virt_add_guest_spec_data() for the struct notif_vm_bitmap to make
it accessible from notif_send_async().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm: boot: enable native interrupts before initcalls

Enable native interrupts on Arm architectures when executing
initcalls (early,service,driver,final). This change allows drivers
to leverage

core: arm: boot: enable native interrupts before initcalls

Enable native interrupts on Arm architectures when executing
initcalls (early,service,driver,final). This change allows drivers
to leverage interrupts during OP-TEE core initialization, as for example
detecting a firewall access violation when it occurs. Before this change,
OP-TEE needed to complete its initialization and return the secure
monitor for secure interrupts to be handled.

Note that when CFG_NS_VIRTUALIZATION is enabled, initcalls called from
virt_on_stdcall() is not changed here since they are executing from a
standard call entry hence with native and foreign interrupts already
default unmasked.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-k3: Add initial support for AM62Lx SoC

AM62Lx newest among on the K3 class of SoCs designed to be low footprint
system where DDR can be as small as 128M. Hence, move the DDR location
to the beg

plat-k3: Add initial support for AM62Lx SoC

AM62Lx newest among on the K3 class of SoCs designed to be low footprint
system where DDR can be as small as 128M. Hence, move the DDR location
to the beginning of DDR right after TF-A.

Disable TI SCI, secure boot info and HW unique ID support for now, they
will be incrementally at later point in time as the underlying
communication layer is different than AM62x.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Dhruva Gole <d-gole@ti.com>

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dts: stm32: add RISAL configuration on the stm32mp257f-ev1 board

Configure the RISALs on the stm32mp257f-ev1 board so that the LPSRAM1/2/3
are accessible by both the ARM Cortex A-35 and ARM Cortex M

dts: stm32: add RISAL configuration on the stm32mp257f-ev1 board

Configure the RISALs on the stm32mp257f-ev1 board so that the LPSRAM1/2/3
are accessible by both the ARM Cortex A-35 and ARM Cortex M0+.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: declare RISAF instances as access controllers

Declare RISAFs as access controllers so that it's possible to check
firewall access rights on address ranges, and reconfigure dynamically
RI

dts: stm32: declare RISAF instances as access controllers

Declare RISAFs as access controllers so that it's possible to check
firewall access rights on address ranges, and reconfigure dynamically
RISAF regions.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: add SAES dependency on RNG firewall configuration for stm32mp13

SAES is connected to RNG by an internal RNG bus to be DPA resistant.
We must ensure that RNG is allocated to the secure wo

dts: stm32: add SAES dependency on RNG firewall configuration for stm32mp13

SAES is connected to RNG by an internal RNG bus to be DPA resistant.
We must ensure that RNG is allocated to the secure world to prevent
the non secure to shut down the RNG peripheral.
Therefore add RNG to the access-controllers of SAES node in stm32mp13
SoC DTSI files.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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dts: stm32: enable PKA on stm32mp135f-dk

Sets PKA peripheral status to okay.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com

dts: stm32: enable PKA on stm32mp135f-dk

Sets PKA peripheral status to okay.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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