drivers: csu: allow setting CSU_CSL0

The sentinel detection in the initialization loop for the CSU_CSL<n>
registers is wrong in that is doesn't allow to set the first register,
CSU_CSL0 (when csu_in

drivers: csu: allow setting CSU_CSL0

The sentinel detection in the initialization loop for the CSU_CSL<n>
registers is wrong in that is doesn't allow to set the first register,
CSU_CSL0 (when csu_index == 0). Fix the conditional so that it stops
on the sentinel value (-1) but still allows 0 as a valid index.
CSU_CSL0 is used for the PWM peripherals on i.MX6 platforms.

Reported-by: Robert Delien <r.delien@payter.nl>
Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Acked-by : Clement Faure <clement.faure@nxp.com>

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core: ls: add CAAM support for LS platforms

Add CAAM support for the following LS platforms:
- ls1012afrwy
- ls1012ardb
- ls1021atwr
- ls1021aqds
- ls1043ardb
- ls1046ardb

Signed-off-by: Clem

core: ls: add CAAM support for LS platforms

Add CAAM support for the following LS platforms:
- ls1012afrwy
- ls1012ardb
- ls1021atwr
- ls1021aqds
- ls1043ardb
- ls1046ardb

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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core: ls: add CAAM_BASE for all LS platforms

Add CAAM_BASE for the following LS platforms:
- ls1021aqds/atwr
- ls1088ardb
- ls2088ardb
- ls1028ardb
- lx2160aqds

Signed-off-by: Clement Faure <c

core: ls: add CAAM_BASE for all LS platforms

Add CAAM_BASE for the following LS platforms:
- ls1021aqds/atwr
- ls1088ardb
- ls2088ardb
- ls1028ardb
- lx2160aqds

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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core: ls: Enable CAAM MAC algorithms

Enable CAAM MAC algorithms:
- HMAC
- CMAC

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

core: pager: initialize vabase in core pager tables

Initialize the vabase in each struct pgt used to page OP-TEE core.

Fixes: 5ca851ec83ba ("core: pager: add struct tblidx")
Acked-by: Jerome Foriss

core: pager: initialize vabase in core pager tables

Initialize the vabase in each struct pgt used to page OP-TEE core.

Fixes: 5ca851ec83ba ("core: pager: add struct tblidx")
Acked-by: Jerome Forissier <jerome@forissier.org>
Tested-by: Jerome Forissier <jerome@forissier.org> (HiKey960)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pager: add struct tblidx

Adds struct tblidx when referring to entries associated with an area
(struct tee_pager_area). This should make a few table indexes a bit less
ambiguous.

Reviewed-by:

core: pager: add struct tblidx

Adds struct tblidx when referring to entries associated with an area
(struct tee_pager_area). This should make a few table indexes a bit less
ambiguous.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: ls: set SGT properties for LS platforms

Set the following SGT properties for LS platforms:
* CFG_CAAM_SGT_ALIGN
* CFG_NXP_CAAM_SGT_V1/V2

Signed-off-by: Clement Faure <clement.faure@nxp.co

core: ls: set SGT properties for LS platforms

Set the following SGT properties for LS platforms:
* CFG_CAAM_SGT_ALIGN
* CFG_NXP_CAAM_SGT_V1/V2

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Sahil Malhotra <sahil.malhotra@nxp.com>

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core: imx: set SGT properties for imx platforms

Set the following SGT properties for imx platforms:
* CFG_CAAM_SGT_ALIGN
* CFG_NXP_CAAM_SGT_V1

Signed-off-by: Clement Faure <clement.faure@nxp.com>

core: imx: set SGT properties for imx platforms

Set the following SGT properties for imx platforms:
* CFG_CAAM_SGT_ALIGN
* CFG_NXP_CAAM_SGT_V1

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: caam: implement CAAM DMA Object

Implementation of a CAAM DMA object to:
- create a DMA object (SGT/buffer) based on input/output buffers
- reallocate a new buffer accessible from the CA

drivers: caam: implement CAAM DMA Object

Implementation of a CAAM DMA object to:
- create a DMA object (SGT/buffer) based on input/output buffers
- reallocate a new buffer accessible from the CAAM address space
- ensure buffer is cache aligned (for the output)

Implementation of CAAM DMA object functions to:
- cache maintenance
- free CAAM DMA object

Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: mm: update description of vm.h exported functions

Update vm_va2pa() and vm_va2pa() inline description comments to
state these are not deprecated and add some details. These 2
functions are nee

core: mm: update description of vm.h exported functions

Update vm_va2pa() and vm_va2pa() inline description comments to
state these are not deprecated and add some details. These 2
functions are needed in debug mode to assert that va/pa conversion
is consistent with core implementation.

Move information about user mapping and ASID from core/mm/vm.h to
arm specific core_mmu.h since ASID is specific to Arm architectures.

Update style for vm_info_init() and vm_info_final() inline description
for consistency in the header file.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: mobj: some mobjs may have no physical address

Change mobj_with_fobj_get_pa() to return TEE_ERROR_NOT_SUPPORTED
when a virtual memory address has no assigned physical address.
This can occ

core: arm: mobj: some mobjs may have no physical address

Change mobj_with_fobj_get_pa() to return TEE_ERROR_NOT_SUPPORTED
when a virtual memory address has no assigned physical address.
This can occur when the related memory is pageable and pager is enabled.
This is the only memory object for which the object physical address
range is volatile because under pager control.

With this change, mobj_get_pa() now can return TEE_ERROR_NOT_SUPPORTED
for mapped addresses. Only check_pa_matches_va() must be updated, all
other calls to mobj_get_pa() already handle the return code values
they need to.

Update check_pa_matches_va() to not panic when vm_va2pa() returns this
code because it can't convert the virtual address because the effective
physical address of the memory cell is volatile as when target memory
is paged and pager is enabled.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: mm: change vm_pa2va() to return a virtual address

Change vm_pa2va() to return target virtual address or NULL if the
physical address cannot be resolved which can happen when pager is
enabled a

core: mm: change vm_pa2va() to return a virtual address

Change vm_pa2va() to return target virtual address or NULL if the
physical address cannot be resolved which can happen when pager is
enabled and the target physical page belongs to the pager page pool.
This change makes vm_pa2va() helper function simpler and its only caller
doesn't differentiate error return codes.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: mm: initialize local variables

Add missing default initializer for local variables of the functions
related to memory address conversion in core_mmu.c.

Signed-off-by: Etienne Carriere <e

core: arm: mm: initialize local variables

Add missing default initializer for local variables of the functions
related to memory address conversion in core_mmu.c.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: introduce CFG_CORE_PAGE_TAG_AND_IV

Introduces CFG_CORE_PAGE_TAG_AND_IV which defaults to enabled if TA
paging is enabled. Can be used to disable tag and IV paging for paged
read-write pages.

core: introduce CFG_CORE_PAGE_TAG_AND_IV

Introduces CFG_CORE_PAGE_TAG_AND_IV which defaults to enabled if TA
paging is enabled. Can be used to disable tag and IV paging for paged
read-write pages.

Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pager: support paging of tag and IV

Adds support for paging of the tag and IV protecting some read-write
fobjs. The tag and IV needed to decrypt/encrypt a page are accessed by
the pager. Since

core: pager: support paging of tag and IV

Adds support for paging of the tag and IV protecting some read-write
fobjs. The tag and IV needed to decrypt/encrypt a page are accessed by
the pager. Since the pager can't handle page fault caused by itself
special measures are taken to make sure that the needed tag and IV are
accessible when needed.

tee_pager_get_page() and tee_pager_load_page() are replaced by
pager_get_page() which does what the previous functions used plus the
additional logic to handle paging of tag and IV.

A new function tee_pager_init_iv_area() is added. It enables
registration of a read/write paged fobj spanning the area used for
storing all tags and IVs. This fobj must store its tags and IVs in
unpaged memory, for instance the heap.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pager: small simplifications

Adds pmem_clear() and make_dirty_page() as small helper functions to avoid
some duplication of code.

Changes tee_pager_unhide_page() to take the virtual address o

core: pager: small simplifications

Adds pmem_clear() and make_dirty_page() as small helper functions to avoid
some duplication of code.

Changes tee_pager_unhide_page() to take the virtual address of the page
to unhide instead of an index into the translation table.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add abort_is_write_fault()

Adds abort_is_write_fault() which returns true if the exception is a
data abort caused by an instruction trying to write at an address.

Acked-by: Etienne Carriere <

core: add abort_is_write_fault()

Adds abort_is_write_fault() which returns true if the exception is a
data abort caused by an instruction trying to write at an address.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm32: increase abort stack without crypto accelerations

In case CFG_CRYPTO_WITH_CE=n choose a larger abort stack since the C
implementation of AES-GCM uses a bit more stack than the one using

core: arm32: increase abort stack without crypto accelerations

In case CFG_CRYPTO_WITH_CE=n choose a larger abort stack since the C
implementation of AES-GCM uses a bit more stack than the one using the
crypto extensions.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-mediatek: add support for MT8175 SoC

Add OP-TEE support for MT8175 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

drivers: scmi-msg: rename agent_id to channel_id

Rename agent_id reference to channel_id to avoid confusion with the
agent identifiers used in SCMI protocol to identify agent, whereas
the drivers on

drivers: scmi-msg: rename agent_id to channel_id

Rename agent_id reference to channel_id to avoid confusion with the
agent identifiers used in SCMI protocol to identify agent, whereas
the drivers only reference an SCMI channel, whatever the agent ID
associated with the channel and knowing that an SCMI agent can have
several channels to communicate with the SCMI platform/server.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>

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core: arm: enforce LTC multi-threading protection

Remove CFG_LTC_OPTEE_THREAD switch and enable or disable
_CFG_CORE_LTC_OPTEE_THREAD based on multi-thread support
since multi-threading mandates thr

core: arm: enforce LTC multi-threading protection

Remove CFG_LTC_OPTEE_THREAD switch and enable or disable
_CFG_CORE_LTC_OPTEE_THREAD based on multi-thread support
since multi-threading mandates thread protection means.

Suggested-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: simplify device memory mapping

Register device memory by cluster range rather than by device interface
as the later is likely to grow as new devices are added whereas the
overall stat

plat-stm32mp1: simplify device memory mapping

Register device memory by cluster range rather than by device interface
as the later is likely to grow as new devices are added whereas the
overall static mapped may not change.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>

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plat-stm32mp1: update from deprecated register_dynamic_shm()

Use macro register_ddr() rather than register_dynamic_shm() that is
deprecated.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro

plat-stm32mp1: update from deprecated register_dynamic_shm()

Use macro register_ddr() rather than register_dynamic_shm() that is
deprecated.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>

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drivers: imx_rngb: random number generator

Add support for the RNG(B) as described in the i.MX 6ULL Applications
Processor Reference Manual, Rev 1, 11/2017.

Tested on an imx6ull based board.

Signe

drivers: imx_rngb: random number generator

Add support for the RNG(B) as described in the i.MX 6ULL Applications
Processor Reference Manual, Rev 1, 11/2017.

Tested on an imx6ull based board.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: mm: move core_memprot.h to core/include/mm

This commit moves core_memprot.h to core/include/mm since it is
architecture-independent.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.co

core: mm: move core_memprot.h to core/include/mm

This commit moves core_memprot.h to core/include/mm since it is
architecture-independent.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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