1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2017-2018, STMicroelectronics 4 * Copyright (c) 2016-2018, Linaro Limited 5 */ 6 7 #include <boot_api.h> 8 #include <config.h> 9 #include <console.h> 10 #include <drivers/gic.h> 11 #include <drivers/stm32_etzpc.h> 12 #include <drivers/stm32mp1_etzpc.h> 13 #include <drivers/stm32_uart.h> 14 #include <dt-bindings/clock/stm32mp1-clks.h> 15 #include <kernel/boot.h> 16 #include <kernel/dt.h> 17 #include <kernel/interrupt.h> 18 #include <kernel/misc.h> 19 #include <kernel/panic.h> 20 #include <kernel/spinlock.h> 21 #include <mm/core_memprot.h> 22 #include <platform_config.h> 23 #include <sm/psci.h> 24 #include <stm32_util.h> 25 #include <trace.h> 26 27 #ifdef CFG_WITH_NSEC_GPIOS 28 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, GPIOS_NSEC_BASE, GPIOS_NSEC_SIZE); 29 #endif 30 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, I2C4_BASE, SMALL_PAGE_SIZE); 31 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, I2C6_BASE, SMALL_PAGE_SIZE); 32 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, RNG1_BASE, SMALL_PAGE_SIZE); 33 #ifdef CFG_WITH_NSEC_UARTS 34 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART1_BASE, SMALL_PAGE_SIZE); 35 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART2_BASE, SMALL_PAGE_SIZE); 36 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART3_BASE, SMALL_PAGE_SIZE); 37 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART4_BASE, SMALL_PAGE_SIZE); 38 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART5_BASE, SMALL_PAGE_SIZE); 39 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART6_BASE, SMALL_PAGE_SIZE); 40 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART7_BASE, SMALL_PAGE_SIZE); 41 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART8_BASE, SMALL_PAGE_SIZE); 42 #endif 43 44 register_phys_mem_pgdir(MEM_AREA_IO_SEC, BSEC_BASE, SMALL_PAGE_SIZE); 45 register_phys_mem_pgdir(MEM_AREA_IO_SEC, ETZPC_BASE, SMALL_PAGE_SIZE); 46 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, GIC_SIZE); 47 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GPIOZ_BASE, SMALL_PAGE_SIZE); 48 register_phys_mem_pgdir(MEM_AREA_IO_SEC, I2C4_BASE, SMALL_PAGE_SIZE); 49 register_phys_mem_pgdir(MEM_AREA_IO_SEC, I2C6_BASE, SMALL_PAGE_SIZE); 50 register_phys_mem_pgdir(MEM_AREA_IO_SEC, PWR_BASE, SMALL_PAGE_SIZE); 51 register_phys_mem_pgdir(MEM_AREA_IO_SEC, RCC_BASE, SMALL_PAGE_SIZE); 52 register_phys_mem_pgdir(MEM_AREA_IO_SEC, RNG1_BASE, SMALL_PAGE_SIZE); 53 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SYSCFG_BASE, SMALL_PAGE_SIZE); 54 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TAMP_BASE, SMALL_PAGE_SIZE); 55 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TZC_BASE, SMALL_PAGE_SIZE); 56 register_phys_mem_pgdir(MEM_AREA_IO_SEC, USART1_BASE, SMALL_PAGE_SIZE); 57 58 register_ddr(DDR_BASE, CFG_DRAM_SIZE); 59 60 #define _ID2STR(id) (#id) 61 #define ID2STR(id) _ID2STR(id) 62 63 static TEE_Result platform_banner(void) 64 { 65 #ifdef CFG_EMBED_DTB 66 IMSG("Platform stm32mp1: flavor %s - DT %s", 67 ID2STR(PLATFORM_FLAVOR), 68 ID2STR(CFG_EMBED_DTB_SOURCE_FILE)); 69 #else 70 IMSG("Platform stm32mp1: flavor %s - no device tree", 71 ID2STR(PLATFORM_FLAVOR)); 72 #endif 73 74 return TEE_SUCCESS; 75 } 76 service_init(platform_banner); 77 78 /* 79 * Console 80 * 81 * CFG_STM32_EARLY_CONSOLE_UART specifies the ID of the UART used for 82 * trace console. Value 0 disables the early console. 83 * 84 * We cannot use the generic serial_console support since probing 85 * the console requires the platform clock driver to be already 86 * up and ready which is done only once service_init are completed. 87 */ 88 static struct stm32_uart_pdata console_data; 89 90 void console_init(void) 91 { 92 /* Early console initialization before MMU setup */ 93 struct uart { 94 paddr_t pa; 95 bool secure; 96 } uarts[] = { 97 [0] = { .pa = 0 }, 98 [1] = { .pa = USART1_BASE, .secure = true, }, 99 [2] = { .pa = USART2_BASE, .secure = false, }, 100 [3] = { .pa = USART3_BASE, .secure = false, }, 101 [4] = { .pa = UART4_BASE, .secure = false, }, 102 [5] = { .pa = UART5_BASE, .secure = false, }, 103 [6] = { .pa = USART6_BASE, .secure = false, }, 104 [7] = { .pa = UART7_BASE, .secure = false, }, 105 [8] = { .pa = UART8_BASE, .secure = false, }, 106 }; 107 108 COMPILE_TIME_ASSERT(ARRAY_SIZE(uarts) > CFG_STM32_EARLY_CONSOLE_UART); 109 110 if (!uarts[CFG_STM32_EARLY_CONSOLE_UART].pa) 111 return; 112 113 /* No clock yet bound to the UART console */ 114 console_data.clock = DT_INFO_INVALID_CLOCK; 115 116 console_data.secure = uarts[CFG_STM32_EARLY_CONSOLE_UART].secure; 117 stm32_uart_init(&console_data, uarts[CFG_STM32_EARLY_CONSOLE_UART].pa); 118 119 register_serial_console(&console_data.chip); 120 121 IMSG("Early console on UART#%u", CFG_STM32_EARLY_CONSOLE_UART); 122 } 123 124 #ifdef CFG_DT 125 static TEE_Result init_console_from_dt(void) 126 { 127 struct stm32_uart_pdata *pd = NULL; 128 void *fdt = NULL; 129 int node = 0; 130 TEE_Result res = TEE_ERROR_GENERIC; 131 132 fdt = get_embedded_dt(); 133 res = get_console_node_from_dt(fdt, &node, NULL, NULL); 134 if (res == TEE_ERROR_ITEM_NOT_FOUND) { 135 fdt = get_external_dt(); 136 res = get_console_node_from_dt(fdt, &node, NULL, NULL); 137 if (res == TEE_ERROR_ITEM_NOT_FOUND) 138 return TEE_SUCCESS; 139 if (res != TEE_SUCCESS) 140 return res; 141 } 142 143 pd = stm32_uart_init_from_dt_node(fdt, node); 144 if (!pd) { 145 IMSG("DTB disables console"); 146 register_serial_console(NULL); 147 return TEE_SUCCESS; 148 } 149 150 /* Replace early console with the new one */ 151 console_flush(); 152 console_data = *pd; 153 free(pd); 154 register_serial_console(&console_data.chip); 155 IMSG("DTB enables console (%ssecure)", pd->secure ? "" : "non-"); 156 157 return TEE_SUCCESS; 158 } 159 160 /* Probe console from DT once clock inits (service init level) are completed */ 161 service_init_late(init_console_from_dt); 162 #endif 163 164 /* 165 * GIC init, used also for primary/secondary boot core wake completion 166 */ 167 static struct gic_data gic_data; 168 169 void itr_core_handler(void) 170 { 171 gic_it_handle(&gic_data); 172 } 173 174 void main_init_gic(void) 175 { 176 assert(cpu_mmu_enabled()); 177 178 gic_init(&gic_data, get_gicc_base(), get_gicd_base()); 179 itr_init(&gic_data.chip); 180 181 stm32mp_register_online_cpu(); 182 } 183 184 void main_secondary_init_gic(void) 185 { 186 gic_cpu_init(&gic_data); 187 188 stm32mp_register_online_cpu(); 189 } 190 191 static TEE_Result init_stm32mp1_drivers(void) 192 { 193 /* Without secure DTB support, some drivers must be inited */ 194 if (!IS_ENABLED(CFG_EMBED_DTB)) 195 stm32_etzpc_init(ETZPC_BASE); 196 197 /* Secure internal memories for the platform, once ETZPC is ready */ 198 etzpc_configure_tzma(0, ETZPC_TZMA_ALL_SECURE); 199 etzpc_lock_tzma(0); 200 201 COMPILE_TIME_ASSERT(((SYSRAM_BASE + SYSRAM_SIZE) <= CFG_TZSRAM_START) || 202 ((SYSRAM_BASE <= CFG_TZSRAM_START) && 203 (SYSRAM_SEC_SIZE >= CFG_TZSRAM_SIZE))); 204 205 etzpc_configure_tzma(1, SYSRAM_SEC_SIZE >> SMALL_PAGE_SHIFT); 206 etzpc_lock_tzma(1); 207 208 return TEE_SUCCESS; 209 } 210 service_init_late(init_stm32mp1_drivers); 211 212 vaddr_t get_gicc_base(void) 213 { 214 struct io_pa_va base = { .pa = GIC_BASE + GICC_OFFSET }; 215 216 return io_pa_or_va_secure(&base); 217 } 218 219 vaddr_t get_gicd_base(void) 220 { 221 struct io_pa_va base = { .pa = GIC_BASE + GICD_OFFSET }; 222 223 return io_pa_or_va_secure(&base); 224 } 225 226 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg) 227 { 228 cfg->base = BSEC_BASE; 229 cfg->upper_start = STM32MP1_UPPER_OTP_START; 230 cfg->max_id = STM32MP1_OTP_MAX_ID; 231 } 232 233 bool stm32mp_is_closed_device(void) 234 { 235 uint32_t otp = 0; 236 TEE_Result result = TEE_ERROR_GENERIC; 237 238 /* Non closed_device platform expects fuse well programmed to 0 */ 239 result = stm32_bsec_shadow_read_otp(&otp, DATA0_OTP); 240 if (!result && !(otp & BIT(DATA0_OTP_SECURED_POS))) 241 return false; 242 243 return true; 244 } 245 246 bool __weak stm32mp_with_pmic(void) 247 { 248 return false; 249 } 250 251 uint32_t may_spin_lock(unsigned int *lock) 252 { 253 if (!lock || !cpu_mmu_enabled()) 254 return 0; 255 256 return cpu_spin_lock_xsave(lock); 257 } 258 259 void may_spin_unlock(unsigned int *lock, uint32_t exceptions) 260 { 261 if (!lock || !cpu_mmu_enabled()) 262 return; 263 264 cpu_spin_unlock_xrestore(lock, exceptions); 265 } 266 267 static vaddr_t stm32_tamp_base(void) 268 { 269 static struct io_pa_va base = { .pa = TAMP_BASE }; 270 271 return io_pa_or_va_secure(&base); 272 } 273 274 static vaddr_t bkpreg_base(void) 275 { 276 return stm32_tamp_base() + TAMP_BKP_REGISTER_OFF; 277 } 278 279 vaddr_t stm32mp_bkpreg(unsigned int idx) 280 { 281 return bkpreg_base() + (idx * sizeof(uint32_t)); 282 } 283 284 vaddr_t stm32_get_gpio_bank_base(unsigned int bank) 285 { 286 static struct io_pa_va gpios_nsec_base = { .pa = GPIOS_NSEC_BASE }; 287 static struct io_pa_va gpioz_base = { .pa = GPIOZ_BASE }; 288 289 /* Get secure mapping address for GPIOZ */ 290 if (bank == GPIO_BANK_Z) 291 return io_pa_or_va_secure(&gpioz_base); 292 293 COMPILE_TIME_ASSERT(GPIO_BANK_A == 0); 294 assert(bank <= GPIO_BANK_K); 295 296 return io_pa_or_va_nsec(&gpios_nsec_base) + (bank * GPIO_BANK_OFFSET); 297 } 298 299 unsigned int stm32_get_gpio_bank_offset(unsigned int bank) 300 { 301 if (bank == GPIO_BANK_Z) 302 return 0; 303 304 assert(bank <= GPIO_BANK_K); 305 return bank * GPIO_BANK_OFFSET; 306 } 307 308 unsigned int stm32_get_gpio_bank_clock(unsigned int bank) 309 { 310 if (bank == GPIO_BANK_Z) 311 return GPIOZ; 312 313 assert(bank <= GPIO_BANK_K); 314 return GPIOA + bank; 315 } 316