core: pager: don't call free_region() from paged function

Call free_region() directly from tee_pager_rem_um_region() instead
of the unpaged helper function rem_region(). This reduces the unpaged
par

core: pager: don't call free_region() from paged function

Call free_region() directly from tee_pager_rem_um_region() instead
of the unpaged helper function rem_region(). This reduces the unpaged
part with a few bytes.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: imx_i2c: add support for MX8MQ

Add support for iMX8MQ.

Signed-off-by: David Griego <david.griego@foundries.io>
Reviewed-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jens Wiklande

drivers: imx_i2c: add support for MX8MQ

Add support for iMX8MQ.

Signed-off-by: David Griego <david.griego@foundries.io>
Reviewed-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat: rcar: fix second DDR bank address for m3_2x4g flavor

Due to mistake, NSEC_DDR_1_BASE was set to incorrect value. In fact, second
DDR bank begins at 0x480000000.

Signed-off-by: Volodymyr Babch

plat: rcar: fix second DDR bank address for m3_2x4g flavor

Due to mistake, NSEC_DDR_1_BASE was set to incorrect value. In fact, second
DDR bank begins at 0x480000000.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pager: fix split_region() to maintain order

Fixes split_region() to maintain the order of paged regions when a
region is split into two.

Fixes: 4a3f6ad054d4 ("core: pager: let struct tee_page

core: pager: fix split_region() to maintain order

Fixes split_region() to maintain the order of paged regions when a
region is split into two.

Fixes: 4a3f6ad054d4 ("core: pager: let struct tee_pager_area span multiple translation tables")
Tested-by: Jerome Forissier <jerome@forissier.org> (HiKey)
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (stm32mp1 w/ gp, stmm)
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pager fix alloc_merged_pgt_array()

Fix the logic for how a shared pgt is detected in
alloc_merged_pgt_array(). Without this there's a buffer overrun in the
pgt_array plus of course not quite

core: pager fix alloc_merged_pgt_array()

Fix the logic for how a shared pgt is detected in
alloc_merged_pgt_array(). Without this there's a buffer overrun in the
pgt_array plus of course not quite right pgt pointers in that array.

Fixes: 4a3f6ad054d4 ("core: pager: let struct tee_pager_area span multiple translation tables")
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pager: fix split_region() pgt assignment

Fixes an error in how pgt_array is copied from the original paged region
into the new split off region.

Fixes: 4a3f6ad054d4 ("core: pager: let struct

core: pager: fix split_region() pgt assignment

Fixes an error in how pgt_array is copied from the original paged region
into the new split off region.

Fixes: 4a3f6ad054d4 ("core: pager: let struct tee_pager_area span multiple translation tables")
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pager: fix increment calculation in tee_pager_set_um_region_attr()

With the introduction of the commit referred below may a paged region
span multiple translation tables, but tee_pager_set_um_

core: pager: fix increment calculation in tee_pager_set_um_region_attr()

With the introduction of the commit referred below may a paged region
span multiple translation tables, but tee_pager_set_um_region_attr()
wasn't updated to handle this. So fix this by accurately calculate
the increment in the main loop of that function.

Fixes: 4a3f6ad054d4 ("core: pager: let struct tee_pager_area span multiple translation tables")
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jerome Forissier <jerome@forissier.org> (HiKey)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-zynq7k: fix wrong argument ordering in NS world unlocking

A defect was introduced in 3.5.0 where the register value and address
in io_write32 are displaced, which eventually led to failure swit

plat-zynq7k: fix wrong argument ordering in NS world unlocking

A defect was introduced in 3.5.0 where the register value and address
in io_write32 are displaced, which eventually led to failure switching
to NS world.

Fixes: af4c7f4b3ad2 ("zynq7k: upgrade from write32() to io_write32() and friends")
Signed-off-by: Yan Yan <yan.yan@windriver.com>
Tested-by: Yan Yan <yan.yan@windriver.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-imx: add compulab iot-gate-imx8 board support

Support for Compulab IoT Gateway (imx8mm) platform.
(PLATFORM=imx-mx8mm_cl_iot_gate)

Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
A

plat-imx: add compulab iot-gate-imx8 board support

Support for Compulab IoT Gateway (imx8mm) platform.
(PLATFORM=imx-mx8mm_cl_iot_gate)

Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Acked-by: Jerome Forissier <jerome@forissier.org>

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core_mmu: fix implicit behavior of core_mmu_add_mapping()

In core_mmu_add_mapping() requested physical address
rounded up/down to granule size (0x100000), which leads
to establishing of virtual mapp

core_mmu: fix implicit behavior of core_mmu_add_mapping()

In core_mmu_add_mapping() requested physical address
rounded up/down to granule size (0x100000), which leads
to establishing of virtual mappings with overlapped
physical counterparts. If two virtual mappings overlaps
due to such roundings, then following phys_to_virt() can
implicitly return result of virtual address from
unexpected mapping. This patch fix such behavior by
returning virtual address of newly established mapping.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Anton Rybakov <a.rybakov@omp.ru>

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core: arm32: update thread_smc() for SMCCC v1.2

SMC Calling Convention v1.2 allows returning result in r4-r7 in addition
to the already used r0-r3. In thread_smc() we're not using r4-r7 to
return a

core: arm32: update thread_smc() for SMCCC v1.2

SMC Calling Convention v1.2 allows returning result in r4-r7 in addition
to the already used r0-r3. In thread_smc() we're not using r4-r7 to
return a result, but the normal function calling convention requires
r4-r7 to be preserved so save and restore them.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: FF-A: add missing break statements to spmc_sp_msg_handler()

Some break statements are missing in spmc_sp_msg_handler(). Add them.

Signed-off-by: Jelle Sels <jelle.sels@arm.com>
Acked-by: Jero

core: FF-A: add missing break statements to spmc_sp_msg_handler()

Some break statements are missing in spmc_sp_msg_handler(). Add them.

Signed-off-by: Jelle Sels <jelle.sels@arm.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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plat: rcar: enable hardware RNG pseudo TA

Enable access of hardware entropy through HWRNG PTA.

Signed-off-by: Sergiy Kibrik <Sergiy_Kibrik@epam.com>
Reviewed-by: Jerome Forissier <jerome@forissier.

plat: rcar: enable hardware RNG pseudo TA

Enable access of hardware entropy through HWRNG PTA.

Signed-off-by: Sergiy Kibrik <Sergiy_Kibrik@epam.com>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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synquacer: rng-pta: move rng_pta_client.h to common path

Header is platform independent and can be used by generic RNG PTA.

Signed-off-by: Sergiy Kibrik <Sergiy_Kibrik@epam.com>
Reviewed-by: Jerome

synquacer: rng-pta: move rng_pta_client.h to common path

Header is platform independent and can be used by generic RNG PTA.

Signed-off-by: Sergiy Kibrik <Sergiy_Kibrik@epam.com>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: dt: don't add optee node for FF-A systems

Systems with FF-A enabled doesn't need an OP-TEE node since the driver
is initialized via the FF-A framework instead.

Acked-by: Jerome Forissier <jer

core: dt: don't add optee node for FF-A systems

Systems with FF-A enabled doesn't need an OP-TEE node since the driver
is initialized via the FF-A framework instead.

Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: ffa: FF-A specific boot arguments

Updates OP-TEE accept FF-A specific boot arguments. This is only used
when OP-TEE is a SPMC at S-EL1 and is loaded with TF-A. So no change
for ARMv7-A platfor

core: ffa: FF-A specific boot arguments

Updates OP-TEE accept FF-A specific boot arguments. This is only used
when OP-TEE is a SPMC at S-EL1 and is loaded with TF-A. So no change
for ARMv7-A platforms.

Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat: rcar: enable ASLR

On RCAR hw_get_random_byte() can be called very early, as it have no
dependencies. So we can use it to provide ASLR seed value.

Also, the previous fix to SCIF drivers preven

plat: rcar: enable ASLR

On RCAR hw_get_random_byte() can be called very early, as it have no
dependencies. So we can use it to provide ASLR seed value.

Also, the previous fix to SCIF drivers prevents crashes with ASLR enabled.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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plat: rcar: implement hw_get_random_byte() function

As we now can call ROM API to access hardware random generator, it is
possible to implement generic interface to it, using hw_get_random_byte()
fu

plat: rcar: implement hw_get_random_byte() function

As we now can call ROM API to access hardware random generator, it is
possible to implement generic interface to it, using hw_get_random_byte()
function.

ROM API provides 32 bytes of random data at a time. To optimally use it, we
need to cache received random vector and provide random number bytes from
it one by one.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Reviewed-by: Jerome Forissier <jerome@forissier.org>

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plat: rcar: add support for ROM API calls including HW RNG

RCAR Gen3 SoCs have public ROM API functions that provide access to various
security-related features, including access to hardware random

plat: rcar: add support for ROM API calls including HW RNG

RCAR Gen3 SoCs have public ROM API functions that provide access to various
security-related features, including access to hardware random number
generator.

This patch adds both generic ROM API interface and wrapper function for
ROM_GetRndVector() call.

As ROM API code is written with identity mapping in mind, we can't call
those function with MMU enabled. So we need a special trampoline function
that would disable MMU, save state and jump to ROM API code.

Beginning with the latest revisions (H3 ES3.0, M3 ES1.1, etc) of Renesas
SoCs, ROM API addresses are fixed, but prior to that each family had own
address, so we need to maintain table of all possible addressed and select
correct one in runtime.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat: rcar: store PRR value in global variable

Product Register will be needed not only by get_core_pos_mpidr
function but by other platform code as well. So move its cached
value into variable in m

plat: rcar: store PRR value in global variable

Product Register will be needed not only by get_core_pos_mpidr
function but by other platform code as well. So move its cached
value into variable in main.c

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>

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plat: rcar: disable aarch32 support for OP-TEE core

While it is theoretically possible to boot RCar Gen3 SoC in aarch32
mode, it isn't supported by Renesas BSP. ARM TF provided by Renesas
boots only

plat: rcar: disable aarch32 support for OP-TEE core

While it is theoretically possible to boot RCar Gen3 SoC in aarch32
mode, it isn't supported by Renesas BSP. ARM TF provided by Renesas
boots only in aarch64 mode. Also it lacks aarch32 assembler code, so
it is not possible to built it for aarch32 at all.

Therefore, there is a little sense in supporting aarch32 in
OP-TEE (for plat-rcar, of course) - user just can't boot it. On other
hand it requires additional efforts to maintain aarch32 assembly code
that newer will be used.

This patch enforces CFG_ARM64_core build option and removes all
aarch32 related parts.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>

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boot: introduce plat_get_aslr_seed()

Platforms may provide own ways to get ASLR seed, so this commit
adds weak function plat_get_aslr_seed(), which is called when we
can't obtain seed from FDT.

Sig

boot: introduce plat_get_aslr_seed()

Platforms may provide own ways to get ASLR seed, so this commit
adds weak function plat_get_aslr_seed(), which is called when we
can't obtain seed from FDT.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome@forissier.org>

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plat-vexpress: FF-A: update secondary core init

Currently when using FF-A on FVP platform, the secondary core entrypoint
registration is done with PSCI calls. However, this relies on a forked
TF-A v

plat-vexpress: FF-A: update secondary core init

Currently when using FF-A on FVP platform, the secondary core entrypoint
registration is done with PSCI calls. However, this relies on a forked
TF-A version, as normally PSCI calls aren't accepted from SWd. Replace
this mechanism with FFA_SECONDARY_EP_REGISTER, which is an FF-A v1.1
ALP0 ABI and it's supported by upstream TF-A v2.5.

Note that the Function ID expected by TF-A differs from the one in the
spec, this will be fixed when the spec is finalized, but the overall
mechanism should stay the same.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>

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core: a32: fix parameter passing for __thread_std_smc_entry()

With the commit referred below is __thread_std_smc_entry() changed to
take 6 arguments instead of 4. This means with the arm32 calling
c

core: a32: fix parameter passing for __thread_std_smc_entry()

With the commit referred below is __thread_std_smc_entry() changed to
take 6 arguments instead of 4. This means with the arm32 calling
convention [1] that the last two parameters are passed on the stack.
This is handled automatically by the C compiler, but has to be done by
hand when calling from assembly. __thread_std_smc_entry() is called from
assembly so fix the two places where the function is called.

Link [1]: https://developer.arm.com/documentation/ihi0042/latest/

Fixes: 4107d2f93e3e ("core: add a4 and a5 to thread_alloc_and_run()")
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: fix thread_alloc_and_run() argument passing

Fix thread_alloc_and_run() to pass all its arguments to
__thread_alloc_and_run(). This is needed with FF-A since the offset of
the struct optee_msg_

core: fix thread_alloc_and_run() argument passing

Fix thread_alloc_and_run() to pass all its arguments to
__thread_alloc_and_run(). This is needed with FF-A since the offset of
the struct optee_msg_arg is passed in w6 from normal world. The Linux
kernel driver currently passes offset=0 so it's not seen while testing,
but that may change with future optimizations in the kernel driver.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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