core: Add support for DEVICE_nGnRnE

Currently OP-TEE only allows non-cached memory to be mapped as
ATTR_DEVICE_nGnRE/Device. This patch adds support for
ATTR_DEVICE_nGnRnE/Strongly-ordered.

Signed-

core: Add support for DEVICE_nGnRnE

Currently OP-TEE only allows non-cached memory to be mapped as
ATTR_DEVICE_nGnRE/Device. This patch adds support for
ATTR_DEVICE_nGnRnE/Strongly-ordered.

Signed-off-by: Jelle Sels <jelle.sels@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: Add mattr_is_cached()

mattr_is_cached() can be used to determine if the mattr is cached or
not.

Signed-off-by: Jelle Sels <jelle.sels@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@lina

core: Add mattr_is_cached()

mattr_is_cached() can be used to determine if the mattr is cached or
not.

Signed-off-by: Jelle Sels <jelle.sels@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: change TEE_MATTR_CACHE_ to TEE_MATTR_MEM_TYPE_

Some extra memory types will be added. This patch renames all
TEE_MATTR_CACHE_ defines to TEE_MATTR_MEM_TYPE_. This will make the next
patches ea

core: change TEE_MATTR_CACHE_ to TEE_MATTR_MEM_TYPE_

Some extra memory types will be added. This patch renames all
TEE_MATTR_CACHE_ defines to TEE_MATTR_MEM_TYPE_. This will make the next
patches easier to understand.

Signed-off-by: Jelle Sels <jelle.sels@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-sam: enable RTC support

Enable RTC API, RTC PTA and Atmel RTC driver for sama5d2.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

plat-sam: enable RTC support

Enable RTC API, RTC PTA and Atmel RTC driver for sama5d2.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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dts: sama5d2: set RTC as secure

The RTC on sama5d2 is actually securing both RSTC, WDT and RTC register
access. Enable secure mode for the RTC to ensure the WDT register
accesses are secured.

Acked

dts: sama5d2: set RTC as secure

The RTC on sama5d2 is actually securing both RSTC, WDT and RTC register
access. Enable secure mode for the RTC to ensure the WDT register
accesses are secured.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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drivers: rstctrl: remove stm32_rstctrl legacy API functions

Removes stm32mp1 reset controllers legacy platform API functions and
moves declaration of stm32mp_rcc_reset_id_to_rstctrl() next to the
de

drivers: rstctrl: remove stm32_rstctrl legacy API functions

Removes stm32mp1 reset controllers legacy platform API functions and
moves declaration of stm32mp_rcc_reset_id_to_rstctrl() next to the
declaration of the remaining platform helper function related to reset
controllers: stm32mp_nsec_can_access_reset().

Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-stm32mp1: scmi_server: use rstctrl resources

Change stm32mp1 SCMI server implementation to use rstctrl framework
to handle reset controllers.

Acked-by: Jerome Forissier <jerome@forissier.org>

plat-stm32mp1: scmi_server: use rstctrl resources

Change stm32mp1 SCMI server implementation to use rstctrl framework
to handle reset controllers.

Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: stm32_rstctrl reset controller for stm32mp1 platforms

Implement stm32 platforms reset controller device, embedded upon
CFG_STM32_RSTCTRL=y.

The drivers exposes its reset controls to the dt

drivers: stm32_rstctrl reset controller for stm32mp1 platforms

Implement stm32 platforms reset controller device, embedded upon
CFG_STM32_RSTCTRL=y.

The drivers exposes its reset controls to the dt_driver provider and
with stm32mp1 platform legacy reset control API function:
stm32_reset_assert(), stm32_reset_deassert() and
stm32_reset_assert_deassert_mcu().

This change also removes source file stm32mp1_rcc.c that has moved
to drivers/rstctrl/stm32_rstctrl.c but stm32_rcc_base() definition
which is moved into to platform main.c.

Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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plar: rcar: add initial support for Gen4

RCar Gen4 is the next generation of Renesas automotive
chips. Currently only RCar S4 on board Spider is available. This
platform has 8 CortexA55 cores with G

plar: rcar: add initial support for Gen4

RCar Gen4 is the next generation of Renesas automotive
chips. Currently only RCar S4 on board Spider is available. This
platform has 8 CortexA55 cores with GICv3.

This is patch adds minimal support, so not all Gen4 features are
available. Namely, ROM API is not supported right now, so HW RNG and
ASLR are disabled. Also, ATF does not provide DTB, so non-secure DDR
ranges are hardcoded.

Apart from that, depending on external configuration, initial
bootloader can use two different UARTs as console: either SCIF3 or
HSCIF0. Thus, CFG_RCAR_UART is introduced.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat: rcar: enable GIC support

Enable GIC support in the same as it is done in other platforms.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Acked-by: Jens Wiklander <jens.wiklande

plat: rcar: enable GIC support

Enable GIC support in the same as it is done in other platforms.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-imx: Add SA settings for i.MX7DS

The Secure Access register configures the access mode for
non-TrustZone aware DMA masters. To ensure that no DMA master can read
the secure memory for OP-TEE, w

plat-imx: Add SA settings for i.MX7DS

The Secure Access register configures the access mode for
non-TrustZone aware DMA masters. To ensure that no DMA master can read
the secure memory for OP-TEE, we set access for all masters except the
ARM CP15 register to non-secure only and lock the settings afterwards.

Acked-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>

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plat: arm: refactor GIC initialization

All platforms (except STM32MP1) follow the same pattern during GIC
initialization: get virtual addresses for distributor (and optionally,
for CPU interface), c

plat: arm: refactor GIC initialization

All platforms (except STM32MP1) follow the same pattern during GIC
initialization: get virtual addresses for distributor (and optionally,
for CPU interface), check that they are not NULL, call either
gic_init() or gic_init_base_addr().

We can move most of this logic into gic_init_base_addr(), while
platform-specific code will supply only base physical addresses for
distributor and CPU interface. This will simplify and align platform
code.

ST32MP1 had more complex logic, as it used io_pa_or_va_secure() to get
MMIO range addresses. However, as main_init_gic() called
assert(cpu_mmu_enabled()), there is no sense in using
io_pa_or_va_secure(), because we already ensured that VA will be
always used. Thus assert() call was moved to gic_init_base_addr(), and
STM32MP1 were aligned with other platforms.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: ls: fix GIC offset for ls1043a rev1 and rev1.1

GIC offsets are different on ls1043a depending of the SoC revision
1 or 1.1

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Signed-off-by

core: ls: fix GIC offset for ls1043a rev1 and rev1.1

GIC offsets are different on ls1043a depending of the SoC revision
1 or 1.1

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: ls: remove CAAM endianness definitions from conf.mk

Remove CAAM endianness definition (CFG_CAAM_LITTLE_ENDIAN and
CFG_CAAM_BIG_ENDIAN) from conf.mk as it is already defined in
crypto_conf.mk

core: ls: remove CAAM endianness definitions from conf.mk

Remove CAAM endianness definition (CFG_CAAM_LITTLE_ENDIAN and
CFG_CAAM_BIG_ENDIAN) from conf.mk as it is already defined in
crypto_conf.mk

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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crypto/aspeed: ast2600: Add HACE HW hash support

Aspeed AST2600 Hash and Crypto Engine (HACE) is designated to
accelerate the throughput of hash and symmetric encryption/decryption.

This patch adds

crypto/aspeed: ast2600: Add HACE HW hash support

Aspeed AST2600 Hash and Crypto Engine (HACE) is designated to
accelerate the throughput of hash and symmetric encryption/decryption.

This patch adds the driver support for AST2600 HACE to provide
HW-assisted hash for the SHA family. The initial driver structure
for Aspeed crypto engines is also constructed.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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core: change return type for tee_entry_std() TEE_Result

Changes the return type for the function tee_entry_std() to TEE_Result
in order to make it independent of optee_smc.h. tee_entry_std() is also

core: change return type for tee_entry_std() TEE_Result

Changes the return type for the function tee_entry_std() to TEE_Result
in order to make it independent of optee_smc.h. tee_entry_std() is also
called from yielding_call_with_arg() and it doesn't make sense for that
function to return values based on the SMC ABI.

With this we're doing an ABI change for FF-A, but that should not make a
difference for the driver since that only test for 0 or !0. In addition
if !0 is returned the communication has broken down completely so there
not much left to recover from. Note that this patch does not require
changes in the Linux kernel driver.

Acked-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: move NOTIF_VALUE_DO_BOTTOM_HALF assert to thread_optee_smc.c

Moves the compile assertion that NOTIF_VALUE_DO_BOTTOM_HALF matches
OPTEE_SMC_ASYNC_NOTIF_VALUE_DO_BOTTOM_HALF in core/kernel/notif

core: move NOTIF_VALUE_DO_BOTTOM_HALF assert to thread_optee_smc.c

Moves the compile assertion that NOTIF_VALUE_DO_BOTTOM_HALF matches
OPTEE_SMC_ASYNC_NOTIF_VALUE_DO_BOTTOM_HALF in core/kernel/notif.c to
core/arch/arm/kernel/thread_optee_smc.c to keep dependencies to
optee_smc.h in architecture specific code.

Acked-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: mm: move tee_mm.c to core/mm

Move tee_mm.c from core/arch/arm/mm to core/mm to reuse it with new
architectures.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Etien

core: mm: move tee_mm.c to core/mm

Move tee_mm.c from core/arch/arm/mm to core/mm to reuse it with new
architectures.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: kernel: move boot.h to core/include/kernel

Move boot.h from core/arch/arm/include/kernel/ to core/include/kernel to
avoid duplicating it in arch folder if we build for a new architecture.

Sig

core: kernel: move boot.h to core/include/kernel

Move boot.h from core/arch/arm/include/kernel/ to core/include/kernel to
avoid duplicating it in arch folder if we build for a new architecture.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: split core/arch/arm/mm/core_mmu.c

Splits core/arch/arm/mm/core_mmu.c into one generic and one architecture
specific file.

Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Marouene

core: split core/arch/arm/mm/core_mmu.c

Splits core/arch/arm/mm/core_mmu.c into one generic and one architecture
specific file.

Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add core_mmu_table_write_barrier()

Adds the special barrier core_mmu_table_write_barrier() which is
supposed to be used to make sure that writes to translation tables has
become visible.

Revi

core: add core_mmu_table_write_barrier()

Adds the special barrier core_mmu_table_write_barrier() which is
supposed to be used to make sure that writes to translation tables has
become visible.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: introduce TRUSTED_{S,D}RAM_*

Introduces TRUSTED_{S,D}RAM_* intended to replace TZ{S,D}RAM_* on the
longer term. In this patch we're cleaning up core_mmu.c to make it
less architecture dependen

core: introduce TRUSTED_{S,D}RAM_*

Introduces TRUSTED_{S,D}RAM_* intended to replace TZ{S,D}RAM_* on the
longer term. In this patch we're cleaning up core_mmu.c to make it
less architecture dependent.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: split core_mmu_private.h

Splits core_mmu_private.h into <mm/core_mmu_arch.h> and <mm/core_mmu.h>

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Marouene Boubakri <marouene.bou

core: split core_mmu_private.h

Splits core_mmu_private.h into <mm/core_mmu_arch.h> and <mm/core_mmu.h>

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: split core/arch/arm/include/mm/core_mmu.h

Splits core/arch/arm/include/mm/core_mmu.h into one generic and one
architecture specific file.

Reviewed-by: Jerome Forissier <jerome@forissier.org>

core: split core/arch/arm/include/mm/core_mmu.h

Splits core/arch/arm/include/mm/core_mmu.h into one generic and one
architecture specific file.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm{32,64}.h: add "memory" constraint

Adds the missing memory constraint to the inline assembly instructions
isb, dsb, dmb, sev, wfe and wfi.

Reviewed-by: Jerome Forissier <jerome@forissier.o

core: arm{32,64}.h: add "memory" constraint

Adds the missing memory constraint to the inline assembly instructions
isb, dsb, dmb, sev, wfe and wfi.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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