xref: /optee_os/core/arch/arm/plat-imx/conf.mk (revision 57432984b1327b45fe613bede99d844dd9baf96e) 
1PLATFORM_FLAVOR ?= mx6ulevk
2
3# Get SoC associated with the PLATFORM_FLAVOR
4mx6ul-flavorlist = \
5	mx6ulevk \
6	mx6ul9x9evk \
7	mx6ulccimx6ulsbcpro \
8	mx6ulccbv2 \
9
10mx6ull-flavorlist = \
11	mx6ullevk \
12	mx6ulzevk \
13
14mx6q-flavorlist = \
15	mx6qsabrelite \
16	mx6qsabreauto \
17	mx6qsabresd \
18	mx6qhmbedge \
19	mx6qapalis \
20
21mx6qp-flavorlist = \
22	mx6qpsabreauto \
23	mx6qpsabresd \
24
25mx6sl-flavorlist = \
26	mx6slevk
27
28mx6sll-flavorlist = \
29	mx6sllevk
30
31mx6sx-flavorlist = \
32	mx6sxsabreauto \
33	mx6sxsabresd \
34	mx6sxudooneofull \
35
36mx6d-flavorlist = \
37	mx6dhmbedge \
38	mx6dapalis \
39
40mx6dl-flavorlist = \
41	mx6dlsabreauto \
42	mx6dlsabresd \
43	mx6dlhmbedge \
44
45mx6s-flavorlist = \
46	mx6shmbedge \
47	mx6solosabresd \
48	mx6solosabreauto \
49
50mx7d-flavorlist = \
51	mx7dsabresd \
52	mx7dpico_mbl \
53	mx7dclsom \
54
55mx7s-flavorlist = \
56	mx7swarp7 \
57	mx7swarp7_mbl \
58
59mx7ulp-flavorlist = \
60	mx7ulpevk
61
62mx8mq-flavorlist = \
63	mx8mqevk
64
65mx8mm-flavorlist = \
66	mx8mmevk \
67	mx8mm_cl_iot_gate \
68	mx8mm_phyboard_polis \
69	mx8mm_phygate_tauri_l
70
71mx8mn-flavorlist = \
72	mx8mnevk
73
74mx8mp-flavorlist = \
75	mx8mpevk \
76	mx8mp_rsb3720_6g \
77	mx8mp_phyboard_pollux \
78	mx8mp_libra_fpsc
79
80mx8qm-flavorlist = \
81	mx8qmmek \
82
83mx8qx-flavorlist = \
84	mx8qxpmek \
85	mx8dxmek \
86
87mx8dxl-flavorlist = \
88	mx8dxlevk \
89
90mx8ulp-flavorlist = \
91	mx8ulpevk \
92
93mx93-flavorlist = \
94	mx93evk \
95
96mx95-flavorlist = \
97	mx95evk \
98
99mx91-flavorlist = \
100	mx91evk \
101
102mx943-flavorlist = \
103	mx943evk \
104
105ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6ul-flavorlist)))
106$(call force,CFG_MX6,y)
107$(call force,CFG_MX6UL,y)
108$(call force,CFG_TEE_CORE_NB_CORE,1)
109$(call force,CFG_TZC380,y)
110include core/arch/arm/cpu/cortex-a7.mk
111else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6ull-flavorlist)))
112$(call force,CFG_MX6,y)
113$(call force,CFG_MX6ULL,y)
114$(call force,CFG_TEE_CORE_NB_CORE,1)
115$(call force,CFG_TZC380,y)
116$(call force,CFG_IMX_CAAM,n)
117$(call force,CFG_NXP_CAAM,n)
118$(call force,CFG_IMX_DCP,y)
119include core/arch/arm/cpu/cortex-a7.mk
120else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6q-flavorlist)))
121$(call force,CFG_MX6,y)
122$(call force,CFG_MX6Q,y)
123$(call force,CFG_TEE_CORE_NB_CORE,4)
124$(call force,CFG_TZC380,y)
125else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6qp-flavorlist)))
126$(call force,CFG_MX6,y)
127$(call force,CFG_MX6QP,y)
128$(call force,CFG_TEE_CORE_NB_CORE,4)
129else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6d-flavorlist)))
130$(call force,CFG_MX6,y)
131$(call force,CFG_MX6D,y)
132$(call force,CFG_TEE_CORE_NB_CORE,2)
133$(call force,CFG_TZC380,y)
134else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6dl-flavorlist)))
135$(call force,CFG_MX6,y)
136$(call force,CFG_MX6DL,y)
137$(call force,CFG_TEE_CORE_NB_CORE,2)
138$(call force,CFG_TZC380,y)
139else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6s-flavorlist)))
140$(call force,CFG_MX6,y)
141$(call force,CFG_MX6S,y)
142$(call force,CFG_TEE_CORE_NB_CORE,1)
143else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sl-flavorlist)))
144$(call force,CFG_MX6,y)
145$(call force,CFG_MX6SL,y)
146$(call force,CFG_TEE_CORE_NB_CORE,1)
147$(call force,CFG_IMX_CAAM,n)
148$(call force,CFG_NXP_CAAM,n)
149$(call force,CFG_IMX_DCP,y)
150else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sll-flavorlist)))
151$(call force,CFG_MX6,y)
152$(call force,CFG_MX6SLL,y)
153$(call force,CFG_TEE_CORE_NB_CORE,1)
154$(call force,CFG_IMX_CAAM,n)
155$(call force,CFG_NXP_CAAM,n)
156$(call force,CFG_IMX_DCP,y)
157$(call force,CFG_NO_SMP,y)
158else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sx-flavorlist)))
159$(call force,CFG_MX6,y)
160$(call force,CFG_MX6SX,y)
161$(call force,CFG_TEE_CORE_NB_CORE,1)
162else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7s-flavorlist)))
163$(call force,CFG_MX7,y)
164$(call force,CFG_TEE_CORE_NB_CORE,1)
165include core/arch/arm/cpu/cortex-a7.mk
166else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7d-flavorlist)))
167$(call force,CFG_MX7,y)
168$(call force,CFG_TEE_CORE_NB_CORE,2)
169include core/arch/arm/cpu/cortex-a7.mk
170else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7ulp-flavorlist)))
171$(call force,CFG_MX7ULP,y)
172$(call force,CFG_TEE_CORE_NB_CORE,1)
173$(call force,CFG_TZC380,n)
174$(call force,CFG_IMX_CSU,n)
175include core/arch/arm/cpu/cortex-a7.mk
176else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mq-flavorlist)))
177$(call force,CFG_MX8MQ,y)
178$(call force,CFG_MX8M,y)
179$(call force,CFG_ARM64_core,y)
180$(call force,CFG_TZC380,y)
181CFG_DRAM_BASE ?= 0x40000000
182CFG_TEE_CORE_NB_CORE ?= 4
183else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mm-flavorlist)))
184$(call force,CFG_MX8MM,y)
185$(call force,CFG_MX8M,y)
186$(call force,CFG_ARM64_core,y)
187$(call force,CFG_TZC380,y)
188CFG_DRAM_BASE ?= 0x40000000
189CFG_TEE_CORE_NB_CORE ?= 4
190else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mn-flavorlist)))
191$(call force,CFG_MX8MN,y)
192$(call force,CFG_MX8M,y)
193$(call force,CFG_ARM64_core,y)
194$(call force,CFG_TZC380,y)
195CFG_DRAM_BASE ?= 0x40000000
196CFG_TEE_CORE_NB_CORE ?= 4
197else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mp-flavorlist)))
198$(call force,CFG_MX8MP,y)
199$(call force,CFG_MX8M,y)
200$(call force,CFG_ARM64_core,y)
201$(call force,CFG_TZC380,y)
202CFG_DRAM_BASE ?= 0x40000000
203CFG_TEE_CORE_NB_CORE ?= 4
204else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8qm-flavorlist)))
205$(call force,CFG_MX8QM,y)
206$(call force,CFG_ARM64_core,y)
207$(call force,CFG_IMX_SNVS,n)
208CFG_IMX_LPUART ?= y
209CFG_DRAM_BASE ?= 0x80000000
210CFG_TEE_CORE_NB_CORE ?= 6
211$(call force,CFG_IMX_OCOTP,n)
212else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8qx-flavorlist)))
213$(call force,CFG_MX8QX,y)
214$(call force,CFG_ARM64_core,y)
215$(call force,CFG_IMX_SNVS,n)
216CFG_IMX_LPUART ?= y
217CFG_DRAM_BASE ?= 0x80000000
218CFG_TEE_CORE_NB_CORE ?= 4
219$(call force,CFG_IMX_OCOTP,n)
220else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8dxl-flavorlist)))
221$(call force,CFG_MX8DXL,y)
222$(call force,CFG_ARM64_core,y)
223$(call force,CFG_IMX_SNVS,n)
224CFG_IMX_LPUART ?= y
225CFG_DRAM_BASE ?= 0x80000000
226$(call force,CFG_TEE_CORE_NB_CORE,2)
227$(call force,CFG_IMX_OCOTP,n)
228else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8ulp-flavorlist)))
229$(call force,CFG_MX8ULP,y)
230$(call force,CFG_ARM64_core,y)
231CFG_IMX_LPUART ?= y
232CFG_DRAM_BASE ?= 0x80000000
233CFG_TEE_CORE_NB_CORE ?= 2
234$(call force,CFG_NXP_SNVS,n)
235$(call force,CFG_IMX_OCOTP,n)
236CFG_IMX_MU ?= y
237CFG_IMX_ELE ?= n
238else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx93-flavorlist)))
239$(call force,CFG_MX93,y)
240$(call force,CFG_ARM64_core,y)
241CFG_IMX_LPUART ?= y
242CFG_DRAM_BASE ?= 0x80000000
243CFG_TEE_CORE_NB_CORE ?= 2
244$(call force,CFG_NXP_SNVS,n)
245$(call force,CFG_IMX_OCOTP,n)
246$(call force,CFG_TZC380,n)
247$(call force,CFG_CRYPTO_DRIVER,n)
248$(call force,CFG_NXP_CAAM,n)
249CFG_IMX_MU ?= y
250CFG_IMX_ELE ?= y
251else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx95-flavorlist)))
252$(call force,CFG_MX95,y)
253$(call force,CFG_ARM64_core,y)
254CFG_IMX_LPUART ?= y
255CFG_DRAM_BASE ?= 0x80000000
256CFG_TEE_CORE_NB_CORE ?= 6
257$(call force,CFG_NXP_SNVS,n)
258$(call force,CFG_IMX_OCOTP,n)
259$(call force,CFG_TZC380,n)
260$(call force,CFG_NXP_CAAM,n)
261CFG_IMX_MU ?= y
262CFG_IMX_ELE ?= y
263else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx91-flavorlist)))
264$(call force,CFG_MX91,y)
265$(call force,CFG_ARM64_core,y)
266CFG_IMX_LPUART ?= y
267CFG_DRAM_BASE ?= 0x80000000
268CFG_TEE_CORE_NB_CORE ?= 1
269$(call force,CFG_NXP_SNVS,n)
270$(call force,CFG_IMX_OCOTP,n)
271$(call force,CFG_TZC380,n)
272$(call force,CFG_NXP_CAAM,n)
273CFG_IMX_MU ?= y
274CFG_IMX_ELE ?= y
275else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx943-flavorlist)))
276$(call force,CFG_MX943,y)
277$(call force,CFG_ARM64_core,y)
278CFG_IMX_LPUART ?= y
279CFG_DRAM_BASE ?= 0x80000000
280CFG_TEE_CORE_NB_CORE ?= 4
281$(call force,CFG_NXP_SNVS,n)
282$(call force,CFG_IMX_OCOTP,n)
283$(call force,CFG_TZC380,n)
284$(call force,CFG_NXP_CAAM,n)
285CFG_IMX_MU ?= y
286CFG_IMX_ELE ?= y
287else
288$(error Unsupported PLATFORM_FLAVOR "$(PLATFORM_FLAVOR)")
289endif
290
291ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dsabresd))
292CFG_DDR_SIZE ?= 0x40000000
293CFG_NS_ENTRY_ADDR ?= 0x80800000
294CFG_IMX_WDOG_EXT_RESET ?= y
295endif
296
297ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dclsom))
298CFG_DDR_SIZE ?= 0x40000000
299CFG_UART_BASE ?= UART1_BASE
300CFG_IMX_WDOG_EXT_RESET ?= y
301endif
302
303ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dpico_mbl))
304CFG_DDR_SIZE ?= 0x20000000
305CFG_NS_ENTRY_ADDR ?= 0x87800000
306CFG_DT_ADDR ?= 0x83100000
307CFG_UART_BASE ?= UART5_BASE
308CFG_BOOT_SECONDARY_REQUEST ?= n
309CFG_EXTERNAL_DTB_OVERLAY ?= y
310CFG_IMX_WDOG_EXT_RESET ?= y
311endif
312
313ifneq (,$(filter $(PLATFORM_FLAVOR),mx7swarp7))
314CFG_DDR_SIZE ?= 0x20000000
315CFG_NS_ENTRY_ADDR ?= 0x80800000
316CFG_BOOT_SECONDARY_REQUEST ?= n
317endif
318
319ifneq (,$(filter $(PLATFORM_FLAVOR),mx7swarp7_mbl))
320CFG_DDR_SIZE ?= 0x20000000
321CFG_NS_ENTRY_ADDR ?= 0x87800000
322CFG_DT_ADDR ?= 0x83100000
323CFG_BOOT_SECONDARY_REQUEST ?= n
324CFG_EXTERNAL_DTB_OVERLAY = y
325CFG_IMX_WDOG_EXT_RESET = y
326endif
327
328ifneq (,$(filter $(PLATFORM_FLAVOR),mx7ulpevk))
329CFG_DDR_SIZE ?= 0x40000000
330CFG_NS_ENTRY_ADDR ?= 0x60800000
331CFG_UART_BASE ?= UART4_BASE
332endif
333
334ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qpsabresd mx6qsabresd mx6dlsabresd \
335	mx6dlsabrelite mx6dhmbedge mx6dlhmbedge mx6solosabresd \
336	mx6dapalis mx6qapalis))
337CFG_DDR_SIZE ?= 0x40000000
338CFG_NS_ENTRY_ADDR ?= 0x12000000
339endif
340
341ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qpsabreauto mx6qsabreauto \
342	mx6dlsabreauto mx6solosabreauto))
343CFG_DDR_SIZE ?= 0x80000000
344CFG_NS_ENTRY_ADDR ?= 0x12000000
345CFG_UART_BASE ?= UART4_BASE
346endif
347
348ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qhmbedge))
349CFG_DDR_SIZE ?= 0x80000000
350CFG_UART_BASE ?= UART1_BASE
351endif
352
353ifneq (,$(filter $(PLATFORM_FLAVOR),mx6shmbedge))
354CFG_DDR_SIZE ?= 0x40000000
355CFG_NS_ENTRY_ADDR ?= 0x12000000
356endif
357
358ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qsabrelite mx6dlsabrelite))
359CFG_DDR_SIZE ?= 0x40000000
360CFG_NS_ENTRY_ADDR ?= 0x12000000
361CFG_UART_BASE ?= UART2_BASE
362endif
363
364ifneq (,$(filter $(PLATFORM_FLAVOR),mx6slevk))
365CFG_NS_ENTRY_ADDR ?= 0x80800000
366CFG_DDR_SIZE ?= 0x40000000
367endif
368
369ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sllevk))
370CFG_NS_ENTRY_ADDR ?= 0x80800000
371CFG_DDR_SIZE ?= 0x80000000
372endif
373
374ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sxsabreauto))
375CFG_DDR_SIZE ?= 0x80000000
376CFG_NS_ENTRY_ADDR ?= 0x80800000
377endif
378
379ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sxsabresd))
380CFG_DDR_SIZE ?= 0x40000000
381CFG_NS_ENTRY_ADDR ?= 0x80800000
382endif
383
384ifeq ($(PLATFORM_FLAVOR), mx6sxudooneofull)
385CFG_DDR_SIZE ?= 0x40000000
386CFG_UART_BASE ?= UART1_BASE
387endif
388
389ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulevk mx6ullevk mx6ulzevk))
390CFG_DDR_SIZE ?= 0x20000000
391CFG_NS_ENTRY_ADDR ?= 0x80800000
392endif
393
394ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulccimx6ulsbcpro))
395CFG_DDR_SIZE ?= 0x10000000
396CFG_NS_ENTRY_ADDR ?= 0x80800000
397CFG_UART_BASE ?= UART5_BASE
398endif
399
400ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ul9x9evk))
401CFG_DDR_SIZE ?= 0x10000000
402CFG_NS_ENTRY_ADDR ?= 0x80800000
403endif
404
405ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulccbv2))
406CFG_DDR_SIZE ?= 0x10000000
407CFG_UART_BASE ?= UART7_BASE
408endif
409
410ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mqevk))
411CFG_DDR_SIZE ?= 0xc0000000
412CFG_UART_BASE ?= UART1_BASE
413endif
414
415ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mmevk))
416CFG_DDR_SIZE ?= 0x80000000
417CFG_UART_BASE ?= UART2_BASE
418endif
419
420ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mm_cl_iot_gate))
421CFG_DDR_SIZE ?= 0x40000000
422CFG_UART_BASE ?= UART3_BASE
423CFG_NSEC_DDR_1_BASE ?= 0x80000000UL
424CFG_NSEC_DDR_1_SIZE ?= 0x40000000UL
425endif
426
427ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mm_phyboard_polis))
428CFG_DDR_SIZE ?= 0x40000000
429CFG_UART_BASE ?= UART3_BASE
430$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
431$(call force,CFG_CORE_ARM64_PA_BITS,36)
432endif
433
434ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mm_phygate_tauri_l))
435CFG_DDR_SIZE ?= 0x80000000
436CFG_UART_BASE ?= UART3_BASE
437$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
438$(call force,CFG_CORE_ARM64_PA_BITS,36)
439endif
440
441ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mnevk))
442CFG_DDR_SIZE ?= 0x80000000
443CFG_UART_BASE ?= UART2_BASE
444endif
445
446ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mpevk))
447CFG_DDR_SIZE ?= UL(0x180000000)
448CFG_UART_BASE ?= UART2_BASE
449$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
450$(call force,CFG_CORE_ARM64_PA_BITS,36)
451endif
452
453ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mp_libra_fpsc))
454CFG_DDR_SIZE ?= 0x40000000
455CFG_UART_BASE ?= UART4_BASE
456$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
457$(call force,CFG_CORE_ARM64_PA_BITS,36)
458endif
459
460ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mp_phyboard_pollux))
461CFG_DDR_SIZE ?= 0x40000000
462CFG_UART_BASE ?= UART1_BASE
463$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
464$(call force,CFG_CORE_ARM64_PA_BITS,36)
465endif
466
467ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mp_rsb3720_6g))
468CFG_DDR_SIZE ?= UL(0x180000000)
469CFG_UART_BASE ?= UART3_BASE
470CFG_TZDRAM_START ?= 0x56000000
471$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
472$(call force,CFG_CORE_ARM64_PA_BITS,36)
473endif
474
475ifneq (,$(filter $(PLATFORM_FLAVOR),mx8qxpmek mx8qmmek))
476CFG_DDR_SIZE ?= 0x80000000
477CFG_UART_BASE ?= UART0_BASE
478CFG_NSEC_DDR_1_BASE ?= 0x880000000UL
479CFG_NSEC_DDR_1_SIZE  ?= 0x380000000UL
480CFG_CORE_ARM64_PA_BITS ?= 40
481endif
482
483ifneq (,$(filter $(PLATFORM_FLAVOR),mx8dxmek))
484CFG_DDR_SIZE ?= 0x40000000
485CFG_UART_BASE ?= UART0_BASE
486$(call force,CFG_MX8DX,y)
487endif
488
489ifneq (,$(filter $(PLATFORM_FLAVOR),mx8dxlevk))
490CFG_DDR_SIZE ?= 0x40000000
491CFG_UART_BASE ?= UART0_BASE
492CFG_NSEC_DDR_1_BASE ?= 0x800000000UL
493CFG_NSEC_DDR_1_SIZE ?= 0x400000000UL
494CFG_CORE_ARM64_PA_BITS ?= 40
495endif
496
497ifneq (,$(filter $(PLATFORM_FLAVOR),mx8ulpevk))
498CFG_DDR_SIZE ?= 0x80000000
499CFG_UART_BASE ?= UART5_BASE
500endif
501
502ifneq (,$(filter $(PLATFORM_FLAVOR),mx93evk mx91evk))
503CFG_DDR_SIZE ?= 0x80000000
504CFG_UART_BASE ?= UART1_BASE
505endif
506
507ifneq (,$(filter $(PLATFORM_FLAVOR),mx95evk mx943evk))
508CFG_DDR_SIZE ?= 0x80000000
509CFG_UART_BASE ?= UART1_BASE
510CFG_NSEC_DDR_1_BASE ?= 0x100000000UL
511CFG_NSEC_DDR_1_SIZE ?= 0x380000000UL
512CFG_CORE_ARM64_PA_BITS ?= 40
513endif
514
515# i.MX6 Solo/SL/SoloX/DualLite/Dual/Quad specific config
516ifeq ($(filter y, $(CFG_MX6QP) $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S) \
517	$(CFG_MX6SL) $(CFG_MX6SLL) $(CFG_MX6SX)), y)
518include core/arch/arm/cpu/cortex-a9.mk
519
520$(call force,CFG_PL310,y)
521
522CFG_PL310_LOCKED ?= y
523CFG_ENABLE_SCTLR_RR ?= y
524CFG_IMX_SCU ?= y
525endif
526
527ifeq ($(filter y, $(CFG_MX6QP) $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S)), y)
528CFG_DRAM_BASE ?= 0x10000000
529endif
530
531ifneq (,$(filter y, $(CFG_MX6UL) $(CFG_MX6ULL) $(CFG_MX6SL) $(CFG_MX6SLL) \
532	$(CFG_MX6SX)))
533CFG_DRAM_BASE ?= 0x80000000
534endif
535
536ifeq ($(filter y, $(CFG_MX7)), y)
537CFG_INIT_CNTVOFF ?= y
538CFG_DRAM_BASE ?= 0x80000000
539endif
540
541ifeq ($(filter y, $(CFG_MX7ULP)), y)
542CFG_INIT_CNTVOFF ?= y
543CFG_DRAM_BASE ?= UL(0x60000000)
544$(call force,CFG_IMX_LPUART,y)
545$(call force,CFG_BOOT_SECONDARY_REQUEST,n)
546endif
547
548ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX7ULP)))
549$(call force,CFG_GIC,y)
550
551CFG_BOOT_SECONDARY_REQUEST ?= y
552CFG_DT ?= y
553CFG_DTB_MAX_SIZE ?= 0x20000
554CFG_PAGEABLE_ADDR ?= 0
555CFG_PSCI_ARM32 ?= y
556CFG_SECURE_TIME_SOURCE_REE ?= y
557CFG_UART_BASE ?= UART1_BASE
558endif
559
560ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX8M)))
561$(call force,CFG_IMX_UART,y)
562CFG_IMX_SNVS ?= y
563endif
564
565ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7)))
566CFG_IMX_CSU ?= y
567endif
568
569ifeq ($(filter y, $(CFG_PSCI_ARM32)), y)
570CFG_HWSUPP_MEM_PERM_WXN = n
571CFG_IMX_WDOG ?= y
572endif
573
574ifeq ($(CFG_ARM64_core),y)
575# arm-v8 platforms
576include core/arch/arm/cpu/cortex-armv8-0.mk
577$(call force,CFG_ARM_GICV3,y)
578$(call force,CFG_GIC,y)
579$(call force,CFG_WITH_ARM_TRUSTED_FW,y)
580$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
581
582CFG_CRYPTO_WITH_CE ?= y
583
584supported-ta-targets = ta_arm64
585endif
586
587CFG_TZDRAM_SIZE ?= 0x01e00000
588CFG_SHMEM_SIZE ?= 0x00200000
589CFG_TZDRAM_START ?= ($(CFG_DRAM_BASE) - $(CFG_TZDRAM_SIZE) - $(CFG_SHMEM_SIZE) + $(CFG_DDR_SIZE))
590CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE))
591
592# Enable embedded tests by default
593CFG_ENABLE_EMBEDDED_TESTS ?= y
594CFG_ATTESTATION_PTA ?= y
595
596# Set default heap size for imx platforms to 128k
597CFG_CORE_HEAP_SIZE ?= 131072
598
599CFG_CRYPTO_SIZE_OPTIMIZATION ?= n
600CFG_MMAP_REGIONS ?= 24
601
602# SE05X and OCOTP both implement tee_otp_get_die_id()
603ifeq ($(CFG_NXP_SE05X),y)
604$(call force,CFG_IMX_OCOTP,n)
605$(call force,CFG_CORE_HUK_SUBKEY_COMPAT_USE_OTP_DIE_ID,n)
606endif
607CFG_IMX_OCOTP ?= y
608CFG_IMX_DIGPROG ?= y
609CFG_PKCS11_TA ?= y
610CFG_CORE_HUK_SUBKEY_COMPAT_USE_OTP_DIE_ID ?= y
611
612# Almost all platforms include CAAM HW Modules, except the
613# ones forced to be disabled
614CFG_NXP_CAAM ?= n
615
616ifeq ($(CFG_NXP_CAAM),y)
617ifeq ($(filter y, $(CFG_MX8QM) $(CFG_MX8QX) $(CFG_MX8DXL)), y)
618CFG_IMX_SC ?= y
619CFG_IMX_MU ?= y
620endif
621
622else
623
624ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX7ULP)))
625CFG_IMX_CAAM ?= y
626endif
627
628endif
629