xref: /utopia/UTPA2-700.0.x/projects/tools/lint/mips-linux-gnu_include/fpu_control.h (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)
1*53ee8cc1Swenshuai.xi /* FPU control word bits.  Mips version.
2*53ee8cc1Swenshuai.xi    Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
3*53ee8cc1Swenshuai.xi    This file is part of the GNU C Library.
4*53ee8cc1Swenshuai.xi    Contributed by Olaf Flebbe and Ralf Baechle.
5*53ee8cc1Swenshuai.xi 
6*53ee8cc1Swenshuai.xi    The GNU C Library is free software; you can redistribute it and/or
7*53ee8cc1Swenshuai.xi    modify it under the terms of the GNU Lesser General Public
8*53ee8cc1Swenshuai.xi    License as published by the Free Software Foundation; either
9*53ee8cc1Swenshuai.xi    version 2.1 of the License, or (at your option) any later version.
10*53ee8cc1Swenshuai.xi 
11*53ee8cc1Swenshuai.xi    The GNU C Library is distributed in the hope that it will be useful,
12*53ee8cc1Swenshuai.xi    but WITHOUT ANY WARRANTY; without even the implied warranty of
13*53ee8cc1Swenshuai.xi    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14*53ee8cc1Swenshuai.xi    Lesser General Public License for more details.
15*53ee8cc1Swenshuai.xi 
16*53ee8cc1Swenshuai.xi    You should have received a copy of the GNU Lesser General Public
17*53ee8cc1Swenshuai.xi    License along with the GNU C Library; if not, write to the Free
18*53ee8cc1Swenshuai.xi    Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
19*53ee8cc1Swenshuai.xi    02111-1307 USA.  */
20*53ee8cc1Swenshuai.xi 
21*53ee8cc1Swenshuai.xi #ifndef _FPU_CONTROL_H
22*53ee8cc1Swenshuai.xi #define _FPU_CONTROL_H
23*53ee8cc1Swenshuai.xi 
24*53ee8cc1Swenshuai.xi /* MIPS FPU floating point control register bits.
25*53ee8cc1Swenshuai.xi  *
26*53ee8cc1Swenshuai.xi  * 31-25  -> floating point conditions code bits 7-1.  These bits are only
27*53ee8cc1Swenshuai.xi  *           available in MIPS IV.
28*53ee8cc1Swenshuai.xi  * 24     -> flush denormalized results to zero instead of
29*53ee8cc1Swenshuai.xi  *           causing unimplemented operation exception.  This bit is only
30*53ee8cc1Swenshuai.xi  *           available for MIPS III and newer.
31*53ee8cc1Swenshuai.xi  * 23     -> Condition bit
32*53ee8cc1Swenshuai.xi  * 22-18  -> reserved (read as 0, write with 0)
33*53ee8cc1Swenshuai.xi  * 17     -> cause bit for unimplemented operation
34*53ee8cc1Swenshuai.xi  * 16     -> cause bit for invalid exception
35*53ee8cc1Swenshuai.xi  * 15     -> cause bit for division by zero exception
36*53ee8cc1Swenshuai.xi  * 14     -> cause bit for overflow exception
37*53ee8cc1Swenshuai.xi  * 13     -> cause bit for underflow exception
38*53ee8cc1Swenshuai.xi  * 12     -> cause bit for inexact exception
39*53ee8cc1Swenshuai.xi  * 11     -> enable exception for invalid exception
40*53ee8cc1Swenshuai.xi  * 10     -> enable exception for division by zero exception
41*53ee8cc1Swenshuai.xi  *  9     -> enable exception for overflow exception
42*53ee8cc1Swenshuai.xi  *  8     -> enable exception for underflow exception
43*53ee8cc1Swenshuai.xi  *  7     -> enable exception for inexact exception
44*53ee8cc1Swenshuai.xi  *  6     -> flag invalid exception
45*53ee8cc1Swenshuai.xi  *  5     -> flag division by zero exception
46*53ee8cc1Swenshuai.xi  *  4     -> flag overflow exception
47*53ee8cc1Swenshuai.xi  *  3     -> flag underflow exception
48*53ee8cc1Swenshuai.xi  *  2     -> flag inexact exception
49*53ee8cc1Swenshuai.xi  *  1-0   -> rounding control
50*53ee8cc1Swenshuai.xi  *
51*53ee8cc1Swenshuai.xi  *
52*53ee8cc1Swenshuai.xi  * Rounding Control:
53*53ee8cc1Swenshuai.xi  * 00 - rounding to nearest (RN)
54*53ee8cc1Swenshuai.xi  * 01 - rounding toward zero (RZ)
55*53ee8cc1Swenshuai.xi  * 10 - rounding (up) toward plus infinity (RP)
56*53ee8cc1Swenshuai.xi  * 11 - rounding (down)toward minus infinity (RM)
57*53ee8cc1Swenshuai.xi  */
58*53ee8cc1Swenshuai.xi 
59*53ee8cc1Swenshuai.xi #include <features.h>
60*53ee8cc1Swenshuai.xi 
61*53ee8cc1Swenshuai.xi #ifdef __mips_soft_float
62*53ee8cc1Swenshuai.xi 
63*53ee8cc1Swenshuai.xi #define _FPU_RESERVED 0xffffffff
64*53ee8cc1Swenshuai.xi #define _FPU_DEFAULT  0x00000000
65*53ee8cc1Swenshuai.xi typedef unsigned int fpu_control_t;
66*53ee8cc1Swenshuai.xi #define _FPU_GETCW(cw) 0
67*53ee8cc1Swenshuai.xi #define _FPU_SETCW(cw) do { } while (0)
68*53ee8cc1Swenshuai.xi extern fpu_control_t __fpu_control;
69*53ee8cc1Swenshuai.xi 
70*53ee8cc1Swenshuai.xi #else /* __mips_soft_float */
71*53ee8cc1Swenshuai.xi 
72*53ee8cc1Swenshuai.xi /* masking of interrupts */
73*53ee8cc1Swenshuai.xi #define _FPU_MASK_V     0x0800  /* Invalid operation */
74*53ee8cc1Swenshuai.xi #define _FPU_MASK_Z     0x0400  /* Division by zero  */
75*53ee8cc1Swenshuai.xi #define _FPU_MASK_O     0x0200  /* Overflow          */
76*53ee8cc1Swenshuai.xi #define _FPU_MASK_U     0x0100  /* Underflow         */
77*53ee8cc1Swenshuai.xi #define _FPU_MASK_I     0x0080  /* Inexact operation */
78*53ee8cc1Swenshuai.xi 
79*53ee8cc1Swenshuai.xi /* flush denormalized numbers to zero */
80*53ee8cc1Swenshuai.xi #define _FPU_FLUSH_TZ   0x1000000
81*53ee8cc1Swenshuai.xi 
82*53ee8cc1Swenshuai.xi /* rounding control */
83*53ee8cc1Swenshuai.xi #define _FPU_RC_NEAREST 0x0     /* RECOMMENDED */
84*53ee8cc1Swenshuai.xi #define _FPU_RC_ZERO    0x1
85*53ee8cc1Swenshuai.xi #define _FPU_RC_UP      0x2
86*53ee8cc1Swenshuai.xi #define _FPU_RC_DOWN    0x3
87*53ee8cc1Swenshuai.xi 
88*53ee8cc1Swenshuai.xi #define _FPU_RESERVED 0xfe3c0000  /* Reserved bits in cw */
89*53ee8cc1Swenshuai.xi 
90*53ee8cc1Swenshuai.xi 
91*53ee8cc1Swenshuai.xi /* The fdlibm code requires strict IEEE double precision arithmetic,
92*53ee8cc1Swenshuai.xi    and no interrupts for exceptions, rounding to nearest.  */
93*53ee8cc1Swenshuai.xi 
94*53ee8cc1Swenshuai.xi #define _FPU_DEFAULT  0x00000000
95*53ee8cc1Swenshuai.xi 
96*53ee8cc1Swenshuai.xi /* IEEE:  same as above, but exceptions */
97*53ee8cc1Swenshuai.xi #define _FPU_IEEE     0x00000F80
98*53ee8cc1Swenshuai.xi 
99*53ee8cc1Swenshuai.xi /* Type of the control word.  */
100*53ee8cc1Swenshuai.xi typedef unsigned int fpu_control_t __attribute__ ((__mode__ (__SI__)));
101*53ee8cc1Swenshuai.xi 
102*53ee8cc1Swenshuai.xi /* Macros for accessing the hardware control word.  */
103*53ee8cc1Swenshuai.xi #define _FPU_GETCW(cw) __asm__ volatile ("cfc1 %0,$31" : "=r" (cw))
104*53ee8cc1Swenshuai.xi #define _FPU_SETCW(cw) __asm__ volatile ("ctc1 %0,$31" : : "r" (cw))
105*53ee8cc1Swenshuai.xi 
106*53ee8cc1Swenshuai.xi /* Default control word set at startup.  */
107*53ee8cc1Swenshuai.xi extern fpu_control_t __fpu_control;
108*53ee8cc1Swenshuai.xi 
109*53ee8cc1Swenshuai.xi #endif /* __mips_soft_float */
110*53ee8cc1Swenshuai.xi 
111*53ee8cc1Swenshuai.xi #endif	/* fpu_control.h */
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