1 /* FPU control word bits. Mips version. 2 Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. 3 This file is part of the GNU C Library. 4 Contributed by Olaf Flebbe and Ralf Baechle. 5 6 The GNU C Library is free software; you can redistribute it and/or 7 modify it under the terms of the GNU Lesser General Public 8 License as published by the Free Software Foundation; either 9 version 2.1 of the License, or (at your option) any later version. 10 11 The GNU C Library is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 Lesser General Public License for more details. 15 16 You should have received a copy of the GNU Lesser General Public 17 License along with the GNU C Library; if not, write to the Free 18 Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 19 02111-1307 USA. */ 20 21 #ifndef _FPU_CONTROL_H 22 #define _FPU_CONTROL_H 23 24 /* MIPS FPU floating point control register bits. 25 * 26 * 31-25 -> floating point conditions code bits 7-1. These bits are only 27 * available in MIPS IV. 28 * 24 -> flush denormalized results to zero instead of 29 * causing unimplemented operation exception. This bit is only 30 * available for MIPS III and newer. 31 * 23 -> Condition bit 32 * 22-18 -> reserved (read as 0, write with 0) 33 * 17 -> cause bit for unimplemented operation 34 * 16 -> cause bit for invalid exception 35 * 15 -> cause bit for division by zero exception 36 * 14 -> cause bit for overflow exception 37 * 13 -> cause bit for underflow exception 38 * 12 -> cause bit for inexact exception 39 * 11 -> enable exception for invalid exception 40 * 10 -> enable exception for division by zero exception 41 * 9 -> enable exception for overflow exception 42 * 8 -> enable exception for underflow exception 43 * 7 -> enable exception for inexact exception 44 * 6 -> flag invalid exception 45 * 5 -> flag division by zero exception 46 * 4 -> flag overflow exception 47 * 3 -> flag underflow exception 48 * 2 -> flag inexact exception 49 * 1-0 -> rounding control 50 * 51 * 52 * Rounding Control: 53 * 00 - rounding to nearest (RN) 54 * 01 - rounding toward zero (RZ) 55 * 10 - rounding (up) toward plus infinity (RP) 56 * 11 - rounding (down)toward minus infinity (RM) 57 */ 58 59 #include <features.h> 60 61 #ifdef __mips_soft_float 62 63 #define _FPU_RESERVED 0xffffffff 64 #define _FPU_DEFAULT 0x00000000 65 typedef unsigned int fpu_control_t; 66 #define _FPU_GETCW(cw) 0 67 #define _FPU_SETCW(cw) do { } while (0) 68 extern fpu_control_t __fpu_control; 69 70 #else /* __mips_soft_float */ 71 72 /* masking of interrupts */ 73 #define _FPU_MASK_V 0x0800 /* Invalid operation */ 74 #define _FPU_MASK_Z 0x0400 /* Division by zero */ 75 #define _FPU_MASK_O 0x0200 /* Overflow */ 76 #define _FPU_MASK_U 0x0100 /* Underflow */ 77 #define _FPU_MASK_I 0x0080 /* Inexact operation */ 78 79 /* flush denormalized numbers to zero */ 80 #define _FPU_FLUSH_TZ 0x1000000 81 82 /* rounding control */ 83 #define _FPU_RC_NEAREST 0x0 /* RECOMMENDED */ 84 #define _FPU_RC_ZERO 0x1 85 #define _FPU_RC_UP 0x2 86 #define _FPU_RC_DOWN 0x3 87 88 #define _FPU_RESERVED 0xfe3c0000 /* Reserved bits in cw */ 89 90 91 /* The fdlibm code requires strict IEEE double precision arithmetic, 92 and no interrupts for exceptions, rounding to nearest. */ 93 94 #define _FPU_DEFAULT 0x00000000 95 96 /* IEEE: same as above, but exceptions */ 97 #define _FPU_IEEE 0x00000F80 98 99 /* Type of the control word. */ 100 typedef unsigned int fpu_control_t __attribute__ ((__mode__ (__SI__))); 101 102 /* Macros for accessing the hardware control word. */ 103 #define _FPU_GETCW(cw) __asm__ volatile ("cfc1 %0,$31" : "=r" (cw)) 104 #define _FPU_SETCW(cw) __asm__ volatile ("ctc1 %0,$31" : : "r" (cw)) 105 106 /* Default control word set at startup. */ 107 extern fpu_control_t __fpu_control; 108 109 #endif /* __mips_soft_float */ 110 111 #endif /* fpu_control.h */ 112