xref: /utopia/UTPA2-700.0.x/projects/tools/gr/mdrv_system_io.h (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)
1*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
2*53ee8cc1Swenshuai.xi //
3*53ee8cc1Swenshuai.xi // Copyright (c) 2006-2007 MStar Semiconductor, Inc.
4*53ee8cc1Swenshuai.xi // All rights reserved.
5*53ee8cc1Swenshuai.xi //
6*53ee8cc1Swenshuai.xi // Unless otherwise stipulated in writing, any and all information contained
7*53ee8cc1Swenshuai.xi // herein regardless in any format shall remain the sole proprietary of
8*53ee8cc1Swenshuai.xi // MStar Semiconductor Inc. and be kept in strict confidence
9*53ee8cc1Swenshuai.xi // (��MStar Confidential Information��) by the recipient.
10*53ee8cc1Swenshuai.xi // Any unauthorized act including without limitation unauthorized disclosure,
11*53ee8cc1Swenshuai.xi // copying, use, reproduction, sale, distribution, modification, disassembling,
12*53ee8cc1Swenshuai.xi // reverse engineering and compiling of the contents of MStar Confidential
13*53ee8cc1Swenshuai.xi // Information is unlawful and strictly prohibited. MStar hereby reserves the
14*53ee8cc1Swenshuai.xi // rights to any and all damages, losses, costs and expenses resulting therefrom.
15*53ee8cc1Swenshuai.xi //
16*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
17*53ee8cc1Swenshuai.xi 
18*53ee8cc1Swenshuai.xi #ifndef __DRV_SYSTEM_IO_H__
19*53ee8cc1Swenshuai.xi #define __DRV_SYSTEM_IO_H__
20*53ee8cc1Swenshuai.xi 
21*53ee8cc1Swenshuai.xi #define IO_SYS_GET_RAW_UART	// not used for LGE (dreamer@lge.com)
22*53ee8cc1Swenshuai.xi //#define IO_SYS_REG_OP      	// not used for LGE (dreamer@lge.com)
23*53ee8cc1Swenshuai.xi 
24*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
25*53ee8cc1Swenshuai.xi //  ioctl method
26*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
27*53ee8cc1Swenshuai.xi 
28*53ee8cc1Swenshuai.xi // Use 'S' as magic number
29*53ee8cc1Swenshuai.xi #define SYS_IOCTL_MAGIC             'S'
30*53ee8cc1Swenshuai.xi 
31*53ee8cc1Swenshuai.xi #define IOCTL_SYS_INIT                 _IOWR(SYS_IOCTL_MAGIC, 0x00, int)
32*53ee8cc1Swenshuai.xi #define IOCTL_SYS_SET_PANEL_INFO       _IOW (SYS_IOCTL_MAGIC, 0x01, int)
33*53ee8cc1Swenshuai.xi #define IOCTL_SYS_SET_BOARD_INFO       _IOW (SYS_IOCTL_MAGIC, 0x02, int)
34*53ee8cc1Swenshuai.xi #define IOCTL_SYS_GET_PANEL_RES        _IOR (SYS_IOCTL_MAGIC, 0x03, int)
35*53ee8cc1Swenshuai.xi #define IOCTL_SYS_READ_GEN_REGISTER    _IOR (SYS_IOCTL_MAGIC, 0x04, int)
36*53ee8cc1Swenshuai.xi #define IOCTL_SYS_WRITE_GEN_REGISTER   _IOWR(SYS_IOCTL_MAGIC, 0x05, int)
37*53ee8cc1Swenshuai.xi #define IOCTL_SYS_LOAD_AEON            _IOWR(SYS_IOCTL_MAGIC, 0x06, int)
38*53ee8cc1Swenshuai.xi #define IOCTL_SYS_RESET_AEON           _IOWR(SYS_IOCTL_MAGIC, 0x07, int)
39*53ee8cc1Swenshuai.xi #define IOCTL_SYS_ENABLE_AEON          _IO(SYS_IOCTL_MAGIC, 0x08)
40*53ee8cc1Swenshuai.xi #define IOCTL_SYS_DISABLE_AEON         _IO(SYS_IOCTL_MAGIC, 0x09)
41*53ee8cc1Swenshuai.xi #define IOCTL_SYS_SWITCH_UART          _IOR (SYS_IOCTL_MAGIC, 0x0A, int)
42*53ee8cc1Swenshuai.xi #define IOCTL_SYS_DUMP_AEON_MSG        _IOR (SYS_IOCTL_MAGIC, 0x0B, int)
43*53ee8cc1Swenshuai.xi #define IOCTL_SYS_IS_AEON_ENABLE	   _IOR (SYS_IOCTL_MAGIC, 0x0C, int)
44*53ee8cc1Swenshuai.xi #define IOCTL_SYS_CHANGE_UART          _IOWR(SYS_IOCTL_MAGIC, 0x0D, int)
45*53ee8cc1Swenshuai.xi 
46*53ee8cc1Swenshuai.xi #define IOCTL_SYS_FLUSH_MEMORY         _IO(SYS_IOCTL_MAGIC, 0x50)
47*53ee8cc1Swenshuai.xi #define IOCTL_SYS_READ_MEMORY          _IO(SYS_IOCTL_MAGIC, 0x51)
48*53ee8cc1Swenshuai.xi 
49*53ee8cc1Swenshuai.xi #ifdef IO_SYS_REG_OP
50*53ee8cc1Swenshuai.xi #   define IOCTL_SYS_REG_OP            _IOWR(SYS_IOCTL_MAGIC, 0x54, int)
51*53ee8cc1Swenshuai.xi #endif
52*53ee8cc1Swenshuai.xi 
53*53ee8cc1Swenshuai.xi #ifdef IO_SYS_GET_RAW_UART
54*53ee8cc1Swenshuai.xi #define IOCTL_SYS_GET_RAW_UART         _IOWR(SYS_IOCTL_MAGIC, 0x55, int) //terry, change ID 56 -> 55
55*53ee8cc1Swenshuai.xi #define IOCTL_SYS_SEND_RAW_UART        _IOWR(SYS_IOCTL_MAGIC, 0x56, int)
56*53ee8cc1Swenshuai.xi #endif
57*53ee8cc1Swenshuai.xi 
58*53ee8cc1Swenshuai.xi #define IOCTL_SYS_TIMER                _IOWR(SYS_IOCTL_MAGIC, 0x57, int)
59*53ee8cc1Swenshuai.xi #define IOCTL_SYS_RELOAD_AEON          _IOWR(SYS_IOCTL_MAGIC, 0x58, int)
60*53ee8cc1Swenshuai.xi 
61*53ee8cc1Swenshuai.xi #if 0
62*53ee8cc1Swenshuai.xi //#define IOCTL_SYS_SWITCH_PAD        _IOWR(SYS_IOCTL_MAGIC, 0x01, DevSys_Switch_Pad)
63*53ee8cc1Swenshuai.xi #define IOCTL_SYS_WDT_ENABLE        _IOW (SYS_IOCTL_MAGIC, 0x02, MS_U32)
64*53ee8cc1Swenshuai.xi #define IOCTL_SYS_WDT_CLEAR         _IO  (SYS_IOCTL_MAGIC, 0x03)
65*53ee8cc1Swenshuai.xi #define IOCTL_SYS_WDT_LASTSTATUS    _IOWR(SYS_IOCTL_MAGIC, 0x04, MS_U32)
66*53ee8cc1Swenshuai.xi #define IOCTL_SYS_WDT_SETTIME       _IOW (SYS_IOCTL_MAGIC, 0x05, MS_U32)
67*53ee8cc1Swenshuai.xi #define IOCTL_SYS_RESET_CHIP        _IO  (SYS_IOCTL_MAGIC, 0x06)
68*53ee8cc1Swenshuai.xi #define IOCTL_SYS_RESET_CPU         _IO  (SYS_IOCTL_MAGIC, 0x07)
69*53ee8cc1Swenshuai.xi #endif
70*53ee8cc1Swenshuai.xi 
71*53ee8cc1Swenshuai.xi #define IOCTL_SYS_HOTEL_MODE           _IOWR(SYS_IOCTL_MAGIC, 0x59, int)
72*53ee8cc1Swenshuai.xi #define IOCTL_SYS_HOTEL_MODE_PRINTF    _IOWR(SYS_IOCTL_MAGIC, 0x5A, int)
73*53ee8cc1Swenshuai.xi 
74*53ee8cc1Swenshuai.xi #define IOCTL_SYS_SETSEQFILE           _IOW (SYS_IOCTL_MAGIC, 0x60, int)
75*53ee8cc1Swenshuai.xi 
76*53ee8cc1Swenshuai.xi // Samuel, bad HDD timeout, 090115
77*53ee8cc1Swenshuai.xi #define IOCTL_SYS_SETVBUS              _IOW (SYS_IOCTL_MAGIC, 0x61, int)
78*53ee8cc1Swenshuai.xi 
79*53ee8cc1Swenshuai.xi //20090724 Terry, URSA ISP Load Code
80*53ee8cc1Swenshuai.xi #define IOCTL_SYS_GETSPI               _IOWR (SYS_IOCTL_MAGIC, 0x62, int)
81*53ee8cc1Swenshuai.xi 
82*53ee8cc1Swenshuai.xi #define IOCTL_SYS_GETREV               _IOR (SYS_IOCTL_MAGIC, 0x63, int)
83*53ee8cc1Swenshuai.xi 
84*53ee8cc1Swenshuai.xi //20091028, Terry, MIU protect
85*53ee8cc1Swenshuai.xi #define IOCTL_SYS_MIU_PROTECT          _IOWR (SYS_IOCTL_MAGIC, 0x64, int)
86*53ee8cc1Swenshuai.xi 
87*53ee8cc1Swenshuai.xi #define IOCTL_SYS_SETUART_MODE         _IOWR (SYS_IOCTL_MAGIC, 0x65, int)
88*53ee8cc1Swenshuai.xi 
89*53ee8cc1Swenshuai.xi #define IOCTL_SYS_SPI_LOAD             _IOWR (SYS_IOCTL_MAGIC, 0x66, int)
90*53ee8cc1Swenshuai.xi 
91*53ee8cc1Swenshuai.xi #define IOCTL_SYS_MAXNR    0xFF
92*53ee8cc1Swenshuai.xi 
93*53ee8cc1Swenshuai.xi #endif // __DRV_SYSTEM_IO_H__
94*53ee8cc1Swenshuai.xi 
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