1 //////////////////////////////////////////////////////////////////////////////// 2 // 3 // Copyright (c) 2006-2007 MStar Semiconductor, Inc. 4 // All rights reserved. 5 // 6 // Unless otherwise stipulated in writing, any and all information contained 7 // herein regardless in any format shall remain the sole proprietary of 8 // MStar Semiconductor Inc. and be kept in strict confidence 9 // (��MStar Confidential Information��) by the recipient. 10 // Any unauthorized act including without limitation unauthorized disclosure, 11 // copying, use, reproduction, sale, distribution, modification, disassembling, 12 // reverse engineering and compiling of the contents of MStar Confidential 13 // Information is unlawful and strictly prohibited. MStar hereby reserves the 14 // rights to any and all damages, losses, costs and expenses resulting therefrom. 15 // 16 //////////////////////////////////////////////////////////////////////////////// 17 18 #ifndef __DRV_SYSTEM_IO_H__ 19 #define __DRV_SYSTEM_IO_H__ 20 21 #define IO_SYS_GET_RAW_UART // not used for LGE (dreamer@lge.com) 22 //#define IO_SYS_REG_OP // not used for LGE (dreamer@lge.com) 23 24 //------------------------------------------------------------------------------------------------- 25 // ioctl method 26 //------------------------------------------------------------------------------------------------- 27 28 // Use 'S' as magic number 29 #define SYS_IOCTL_MAGIC 'S' 30 31 #define IOCTL_SYS_INIT _IOWR(SYS_IOCTL_MAGIC, 0x00, int) 32 #define IOCTL_SYS_SET_PANEL_INFO _IOW (SYS_IOCTL_MAGIC, 0x01, int) 33 #define IOCTL_SYS_SET_BOARD_INFO _IOW (SYS_IOCTL_MAGIC, 0x02, int) 34 #define IOCTL_SYS_GET_PANEL_RES _IOR (SYS_IOCTL_MAGIC, 0x03, int) 35 #define IOCTL_SYS_READ_GEN_REGISTER _IOR (SYS_IOCTL_MAGIC, 0x04, int) 36 #define IOCTL_SYS_WRITE_GEN_REGISTER _IOWR(SYS_IOCTL_MAGIC, 0x05, int) 37 #define IOCTL_SYS_LOAD_AEON _IOWR(SYS_IOCTL_MAGIC, 0x06, int) 38 #define IOCTL_SYS_RESET_AEON _IOWR(SYS_IOCTL_MAGIC, 0x07, int) 39 #define IOCTL_SYS_ENABLE_AEON _IO(SYS_IOCTL_MAGIC, 0x08) 40 #define IOCTL_SYS_DISABLE_AEON _IO(SYS_IOCTL_MAGIC, 0x09) 41 #define IOCTL_SYS_SWITCH_UART _IOR (SYS_IOCTL_MAGIC, 0x0A, int) 42 #define IOCTL_SYS_DUMP_AEON_MSG _IOR (SYS_IOCTL_MAGIC, 0x0B, int) 43 #define IOCTL_SYS_IS_AEON_ENABLE _IOR (SYS_IOCTL_MAGIC, 0x0C, int) 44 #define IOCTL_SYS_CHANGE_UART _IOWR(SYS_IOCTL_MAGIC, 0x0D, int) 45 46 #define IOCTL_SYS_FLUSH_MEMORY _IO(SYS_IOCTL_MAGIC, 0x50) 47 #define IOCTL_SYS_READ_MEMORY _IO(SYS_IOCTL_MAGIC, 0x51) 48 49 #ifdef IO_SYS_REG_OP 50 # define IOCTL_SYS_REG_OP _IOWR(SYS_IOCTL_MAGIC, 0x54, int) 51 #endif 52 53 #ifdef IO_SYS_GET_RAW_UART 54 #define IOCTL_SYS_GET_RAW_UART _IOWR(SYS_IOCTL_MAGIC, 0x55, int) //terry, change ID 56 -> 55 55 #define IOCTL_SYS_SEND_RAW_UART _IOWR(SYS_IOCTL_MAGIC, 0x56, int) 56 #endif 57 58 #define IOCTL_SYS_TIMER _IOWR(SYS_IOCTL_MAGIC, 0x57, int) 59 #define IOCTL_SYS_RELOAD_AEON _IOWR(SYS_IOCTL_MAGIC, 0x58, int) 60 61 #if 0 62 //#define IOCTL_SYS_SWITCH_PAD _IOWR(SYS_IOCTL_MAGIC, 0x01, DevSys_Switch_Pad) 63 #define IOCTL_SYS_WDT_ENABLE _IOW (SYS_IOCTL_MAGIC, 0x02, MS_U32) 64 #define IOCTL_SYS_WDT_CLEAR _IO (SYS_IOCTL_MAGIC, 0x03) 65 #define IOCTL_SYS_WDT_LASTSTATUS _IOWR(SYS_IOCTL_MAGIC, 0x04, MS_U32) 66 #define IOCTL_SYS_WDT_SETTIME _IOW (SYS_IOCTL_MAGIC, 0x05, MS_U32) 67 #define IOCTL_SYS_RESET_CHIP _IO (SYS_IOCTL_MAGIC, 0x06) 68 #define IOCTL_SYS_RESET_CPU _IO (SYS_IOCTL_MAGIC, 0x07) 69 #endif 70 71 #define IOCTL_SYS_HOTEL_MODE _IOWR(SYS_IOCTL_MAGIC, 0x59, int) 72 #define IOCTL_SYS_HOTEL_MODE_PRINTF _IOWR(SYS_IOCTL_MAGIC, 0x5A, int) 73 74 #define IOCTL_SYS_SETSEQFILE _IOW (SYS_IOCTL_MAGIC, 0x60, int) 75 76 // Samuel, bad HDD timeout, 090115 77 #define IOCTL_SYS_SETVBUS _IOW (SYS_IOCTL_MAGIC, 0x61, int) 78 79 //20090724 Terry, URSA ISP Load Code 80 #define IOCTL_SYS_GETSPI _IOWR (SYS_IOCTL_MAGIC, 0x62, int) 81 82 #define IOCTL_SYS_GETREV _IOR (SYS_IOCTL_MAGIC, 0x63, int) 83 84 //20091028, Terry, MIU protect 85 #define IOCTL_SYS_MIU_PROTECT _IOWR (SYS_IOCTL_MAGIC, 0x64, int) 86 87 #define IOCTL_SYS_SETUART_MODE _IOWR (SYS_IOCTL_MAGIC, 0x65, int) 88 89 #define IOCTL_SYS_SPI_LOAD _IOWR (SYS_IOCTL_MAGIC, 0x66, int) 90 91 #define IOCTL_SYS_MAXNR 0xFF 92 93 #endif // __DRV_SYSTEM_IO_H__ 94 95