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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// @file drvMFC.h 98 /// @brief 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _DRV_MFC_H_ 103 #define _DRV_MFC_H_ 104 105 106 //////////////////////////////////////////////////////////////////////////////// 107 // Include List 108 //////////////////////////////////////////////////////////////////////////////// 109 110 #ifdef __cplusplus 111 extern "C" 112 { 113 #endif 114 115 #include "MsTypes.h" 116 117 //////////////////////////////////////////////////////////////////////////////// 118 // Constant & Macro Definition 119 //////////////////////////////////////////////////////////////////////////////// 120 /// Version string. 121 #define MFC_DRV_VERSION /* Character String for DRV/API version */ \ 122 MSIF_TAG, /* 'MSIF' */ \ 123 MSIF_CLASS, /* '00' */ \ 124 MSIF_CUS, /* 0x0000 */ \ 125 MSIF_MOD, /* 0x0000 */ \ 126 MSIF_CHIP, \ 127 MSIF_CPU, \ 128 {'M','F','V','_'}, /* IP__ */ \ 129 {'0','1'}, /* 0.0 ~ Z.Z */ \ 130 {'0','1'}, /* 00 ~ 99 */ \ 131 {'0','0','1','4','0','9','4','2'}, /* CL# */ \ 132 MSIF_OS 133 134 //////////////////////////////////////////////////////////////////////////////// 135 // Type & Structure Declaration 136 //////////////////////////////////////////////////////////////////////////////// 137 /// MFC's capability 138 139 #define U8 MS_U8 140 #define U16 MS_U16 141 #define U32 MS_U32 142 #define S8 MS_S8 143 #define S16 MS_S16 144 #define S32 MS_S32 145 146 typedef struct MST_MFC_DRV_SYS_INFO_s 147 { 148 //titania to URSA 149 U8 u8LVDSChannel; //Single, Dual 150 U8 u8LVDSBitNum; //8bits, 10 bits 151 U8 u8LVDSTiMode; //Thin/Ti mode scaler 40-bit2 152 U8 u8LVDSSwapMsbLsb; //ursa scaler 153 U8 u8LVDSSwap_P_N; //ursa scaler 154 U8 u8LVDSSwapOddEven; //ursa scaler 155 156 //URSA to Panel info 157 U8 u8PanelType; //TTL, Mini_LVDS, LVDS 158 U8 u8PanelBitNum; //Panel bit number 159 U8 u8PanelChannel; //Single, Dual, Quad, Quad_LR 160 U8 u8PanelDither; 161 U8 u8PanelLVDSTiMode; //Panel TI/Thin mode 162 U8 u8PanelLVDSSwapPol; //Panel LVDS polarity swap 163 U8 u8PanelLVDSSwapCH; //LVDS chenel swap ABCD 164 U8 u8PanelLVDSSwapPair; //Panel LVDS pair swap 165 U8 u8PanelLVDSShiftPair; 166 U8 u8PanelBlankCPVC; //Panel Mini LVDS use 167 U8 u8PanelBlankOEC; //Panel Mini LVDS use 168 U8 u8PanelBlankTPC; //Panel Mini LVDS use 169 U8 u8PanelBlankSTHC; //Panel Mini LVDS use 170 171 U16 u16HStart; //ursa scaler 172 U16 u16VStart; //ursa scaler 173 U16 u16Width; //ursa scaler 174 U16 u16Height; //ursa scaler 175 U16 u16HTotal; //ursa scaler 176 U16 u16VTotal; //ursa scaler 177 U8 u8PanelVfreq; //Panel frame rate 60Hz, 120Hz, 240Hz 178 U8 u8PanelIncVtotalFor50Hz; //Change Vtotal for DCLK 179 U8 u8PanelCSC; //LVDS CSC enable/disable 180 U16 u16MFCMemoryClk; //MFC memory clock MHz 181 U16 u16MFCMemoryType; //MFC memory type 182 U8 u8PanelGAMMA; 183 U8 u8ODMode; 184 U8 u8IPMode; 185 U8 u8Preset; 186 U8 u8MirrorMode; 187 U8 u8UseMPIF; 188 } MST_MFC_DRV_SYS_INFO_t, *PMST_MFC_DRV_SYS_INFO_t; 189 190 void MDrv_URSA_Init(PMST_MFC_DRV_SYS_INFO_t mfcSysInfo, MS_U8 u8IsS7M); 191 void MDrv_URSA_ControlFrameLockMode(MS_U8 u8type); 192 void MDrv_URSA_SetSpreadSpectrum(MS_U16 u16KHz, MS_U16 u16Percent, MS_BOOL bEnable, MS_BOOL bMiuLVDS); 193 void MDrv_URSA_SetVFreq(MS_U16 u16Inputfreq, MS_BOOL bEnableFPLL); 194 195 #ifdef __cplusplus 196 } 197 #endif 198 199 #endif 200