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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// @file drvHDMITx.h 98 /// @author MStar Semiconductor Inc. 99 /// @brief HDMI Tx Driver Interface 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _DRV_HDMITX_H_ 103 #define _DRV_HDMITX_H_ 104 105 106 #ifdef __cplusplus 107 extern "C" 108 { 109 #endif 110 111 #include "halHDMITx.h" 112 #ifdef CUSTOMER_NDS 113 #include "apiHDMITx_NDS.h" 114 #endif // CUSTOMER_NDS 115 116 //------------------------------------------------------------------------------------------------- 117 // Driver Capability 118 //------------------------------------------------------------------------------------------------- 119 120 121 //------------------------------------------------------------------------------------------------- 122 // Macro and Define 123 //------------------------------------------------------------------------------------------------- 124 125 #ifdef MSOS_TYPE_LINUX_KERNEL 126 #define HDMITX_ISR_ENABLE 1 127 #else 128 #define HDMITX_ISR_ENABLE 1 129 #endif 130 131 //------------------------------------------------------------------------------------------------- 132 // Type and Structure 133 //------------------------------------------------------------------------------------------------- 134 135 //*********************// 136 // DVI / HDMI // 137 //*********************// 138 139 /* 140 Bit1: 141 - 0: DVI 142 - 1: HDMI 143 Bit0: 144 - 0: without HDCP 145 - 1: with HDCP 146 */ 147 typedef enum 148 { 149 E_HDMITX_DVI = 0, // DVI without HDCP 150 E_HDMITX_DVI_HDCP = 1, // DVI with HDCP 151 E_HDMITX_HDMI = 2, // HDMI without HDCP 152 E_HDMITX_HDMI_HDCP = 3, // HDMI with HDCP 153 } MsHDMITX_OUTPUT_MODE; 154 155 typedef enum 156 { 157 E_HDMITX_EVENT_RUN = 0x00000001, 158 E_HDMITX_EVENT_IRQ = 0x00000002, 159 E_HDMITX_EVENT_RITIMER = 0x00000004, 160 E_HDMITX_EVENT_RXTIMER = 0x00000008, 161 E_HDMITX_EVENT_CECRX = 0x00000010, 162 } MDrvHDMITXEvent; 163 164 165 typedef enum 166 { 167 E_HDMITX_FSM_PENDING = 0, 168 E_HDMITX_FSM_CHECK_HPD = 1, 169 E_HDMITX_FSM_VALIDATE_EDID = 2, 170 E_HDMITX_FSM_HDCP_AUTH_WAIT_RX = 3, 171 E_HDMITX_FSM_HDCP_AUTH_CHECK_R0 = 4, 172 E_HDMITX_FSM_HDCP_AUTH_CHECK_REPEATER = 5, 173 E_HDMITX_FSM_HDCP_AUTH_DONE = 6, 174 E_HDMITX_FSM_HDCP_AUTH_FAIL = 7, 175 } MDrvHDMITX_FSM_STATE; 176 177 typedef enum 178 { 179 E_NORMAL_OUTPUT = 0, // still display normally 180 E_HDCP_ENCRYPTION = 1, // HDCP encryption to show snow screen 181 E_BLUE_SCREEN = 2, // blue screen 182 } MDrvHDMITX_UNHDCPRX_CONTROL; 183 184 typedef enum 185 { 186 E_CHECK_NOT_READY = 0, 187 E_CHECK_REVOKED = 1, 188 E_CHECK_NOT_REVOKED = 2, 189 }MDrvHDMITX_REVOCATION_STATE; 190 191 typedef enum 192 { 193 E_RXFail_NORMAL_OUTPUT = 0, // still display normally 194 E_RXFail_HDCP_ENCRYPTION = 1, // HDCP encryption to show snow screen 195 E_RXFail_BLUE_SCREEN = 2, // blue screen 196 } MDrvHDMITX_HDCPRXFail_CONTROL; 197 198 typedef enum 199 { 200 E_HDMITX_HDCP_RESET = 0x01, 201 E_HDMITX_HDCP_WAITING_ACTIVE_RX = 0x02, 202 E_HDMITX_HDCP_CHECK_REPEATER_READY = 0x03, 203 E_HDMITX_HDCP_CHECK_R0 = 0x04, 204 E_HDMITX_HDCP_AUTH_DONE = 0x05, 205 E_HDMITX_HDCP_AUTH_FAIL = 0x06, 206 207 // bit[7:6]=00 for checking valid rx 208 E_HDMITX_HDCP_RX_IS_NOT_VALID = 0x00, // 00 00 209 E_HDMITX_HDCP_RX_IS_VALID = 0x10, // 00 01 210 E_HDMITX_HDCP_RX_KEY_FAIL = 0x20, // 00 10 211 E_HDMITX_HDCP_TX_KEY_FAIL = 0x30, // 00 11 212 E_HDMITX_HDCP_RX_KEY_REVOKED = 0x0F, // 00 00 11 11 213 214 // bit[7:6]=01 for repeater 215 E_HDMITX_HDCP_REPEATER_TIMEOUT = 0x40, // 01 00 216 E_HDMITX_HDCP_REPEATER_READY = 0x50, // 01 01 217 E_HDMITX_HDCP_REPEATER_NOT_READY = 0x60, // 01 10 218 E_HDMITX_HDCP_REPEATER_VALID = 0x70, // 01 11 219 220 // bit[7:6]=10 for SHA1 221 E_HDMITX_HDCP_REPEATER_SHA1_FAIL = 0x80, // 10 00 222 E_HDMITX_HDCP_REPEATER_SHA1_PASS = 0x90, // 10 01 223 224 // bit[7:6]=11 for Ri 225 E_HDMITX_HDCP_SYNC_RI_FAIL = 0xC0, // 11 00 226 E_HDMITX_HDCP_SYNC_RI_PASS = 0xD0 // 11 01 227 }MsHDMITX_HDCP_AUTH_STATUS; 228 229 typedef struct 230 { 231 MS_BOOL hdmitx_enable_flag; ///< hdmitx module actived 232 MS_BOOL hdmitx_tmds_flag; ///< hdmitx tmds on/off 233 MS_BOOL hdmitx_video_flag; ///< hdmitx video on/off 234 MS_BOOL hdmitx_audio_flag; ///< hdmitx audio on/off 235 MS_BOOL hdmitx_hdcp_flag; ///< hdmitx hdcp encryption on/off 236 MS_BOOL hdmitx_csc_flag; ///< hdmitx csc on/off 237 MS_BOOL hdmitx_audio_supportAI; ///< hdmitx audio support AI 238 MS_BOOL hdmitx_RB_swap_flag; ///< hdmitx R/B swap 239 MS_BOOL hdmitx_force_mode; ///< hdmitx output force mode: auto/force 240 MS_BOOL hdmitx_force_output_color; ///< hdmitx output force color format: auto/force 241 MS_BOOL hdmitx_AFD_override_mode; ///< hdmitx AFD override mode: auto/override 242 MS_BOOL hdmitx_edid_ready; ///< hdmitx get ready to Rx's EDID 243 MS_BOOL hdmitx_avmute_flag; ///< hdmitx AVMUTE status 244 245 // HDCP 246 MS_BOOL hdmitx_HdcpUseInternalKey_flag; ///< hdmitx HDCP key source 247 MS_BOOL hdmitx_HdcpStartAuth_flag; ///< hdmitx HDCP start authentication flag 248 MS_BOOL hdmitx_HdcpAuthDone_flag; ///< hdmitx HDCP authentication done flag 249 MS_BOOL hdmitx_HdcpCheckRepeater_flag; ///< hdmitx HDCP check repeater flag 250 251 // CEC 252 MS_BOOL hdmitx_CECEnable_flag; ///< hdmitx CEC enable flag 253 254 MDrvHDMITX_FSM_STATE hdmitx_fsm_state; ///< hdmitx fsm state 255 MDrvHDMITX_FSM_STATE hdmitx_fsm_prestate; ///< hdmitx fsm pre-state 256 MsHDMITX_RX_STATUS hdmitx_preRX_status; ///< hdmitx previous Rx status 257 MsHDMITX_HDCP_AUTH_STATUS hdmitx_HDCPAuth_Status; ///< hdmitx HDCP authentication status 258 MDrvHDMITX_UNHDCPRX_CONTROL hdmitx_unHDCPRx_Control; ///< hdmitx unHDCP Rx ouput way 259 MDrvHDMITX_HDCPRXFail_CONTROL hdmitx_HDCPRxFail_Control; ///< hdmitx HDCP Rx fail output way 260 261 MsHDMITX_OUTPUT_MODE output_mode; ///< output DVI / HDMI mode 262 MsHDMITX_OUTPUT_MODE force_output_mode; ///< output DVI / HDMI mode 263 MsHDMITX_VIDEO_COLORDEPTH_VAL output_colordepth_val; // output video color depth 264 MsHDMITX_VIDEO_COLORDEPTH_VAL edid_colordepth_val; // EDID video color depth 265 MsHDMITX_VIDEO_TIMING output_video_timing; ///< output video timing 266 MsHDMITX_VIDEO_TIMING output_video_prevtiming; ///< output video previous timing 267 MsHDMITX_VIDEO_COLOR_FORMAT input_color; ///< RGB444 / YUV444 268 MsHDMITX_VIDEO_COLOR_FORMAT output_color; ///< RGB444 / YUV444 269 MsHDMITX_VIDEO_COLOR_FORMAT force_output_color; ///< RGB444 / YUV444 270 MsHDMITX_VIDEO_ASPECT_RATIO output_aspect_ratio; // Aspect ratio 271 MsHDMITX_VIDEO_SCAN_INFO output_scan_info; // overscan / underscan 272 MsHDMITX_VIDEO_AFD_RATIO output_afd_ratio; // AFD 273 MS_U8 output_activeformat_present; // Active format information present 274 MsHDMITX_AUDIO_FREQUENCY output_audio_frequncy; ///< audio sampling frequency 275 MsHDMITX_AUDIO_CHANNEL_COUNT output_audio_channel; // audio channel count 276 MsHDMITX_AUDIO_CODING_TYPE output_audio_type; // audio coding type 277 MS_U8 edid_phyadr[2]; // EDID physical address 278 MS_U8 hdcp_srmlist[5116]; // maximum length of the 1st generation 279 MS_U8 hdcp_revocationlist[5068]; // 5x max number of device 280 MS_BOOL revocationlist_ready; // revocationlist update flag 281 MS_U8 revocation_size; 282 MDrvHDMITX_REVOCATION_STATE revocation_state; // revocation check state 283 MS_U8 short_video_descriptor[32]; // short video descriptor of EDID 284 MS_U8 short_audio_descriptor[32]; // short audio descriptor of EDID 285 MS_U8 data_block_length[8]; // data block length of each data block 286 MS_U8 id_manufacturer_name[3]; // ID Manufacturer Name 287 MS_U8 edid_block0[128]; //EDID's 1st 128 data 288 MS_U8 edid_block1[128]; //EDID's 2nd 128 data 289 #ifdef CUSTOMER_NDS 290 MS_U32 events; 291 MS_U32 hdcp_encryptionStartTime; 292 MS_BOOL hdcp_checkPjIntegrity; 293 #endif 294 MsHDMITX_ANALOG_TUNING analog_setting; // HDMI Tx Pre-emphasis and Double termination 295 MsHDMITX_VIDEO_VS_FORMAT vs_pkt_format; // VS packet video format 296 MsHDMITX_VIDEO_3D_STRUCTURE vs_pkt_3d; // VS packet 3d structur 297 MsHDMITX_VIDEO_4k2k_VIC vs_4k2k_vic; // VS packet 3d structur 298 MS_BOOL edid_2D_50hz_support; 299 MS_BOOL edid_2D_60hz_support; 300 MS_BOOL edid_3D_50hz_support; 301 MS_BOOL edid_3D_60hz_support; 302 MS_BOOL edid_3D_present; 303 MS_BOOL edid_HDMI_support; 304 MsHDMITX_EDID_3D_SUPPORT_TIMING edid_3D_support_timing[32]; 305 MS_U8 HDCP_AKSV[5]; 306 MS_U8 HDCP_BKSV[5]; 307 MS_BOOL HDCP_74_check; 308 } MDrvHDMITX_PARAMETER_LIST; 309 310 // debug mask definition 311 #define HDMITX_DBG 0x01///< Debug PQ Table 312 #define HDMITX_DBG_HDCP 0x02///< Debug S RULE 313 #define HDMITX_DBG_UTILTX 0x04///< Debug S RULE 314 315 //------------------------------------------------------------------------------------------------- 316 // Function Prototype 317 //------------------------------------------------------------------------------------------------- 318 #ifdef MDRV_HDMITX_C 319 #define INTERFACED 320 #else 321 #define INTERFACED extern 322 #endif 323 324 INTERFACED MS_BOOL MDrv_HDMITx_Init(void); 325 326 // HDMI Tx get HDCP key 327 INTERFACED void MDrv_HDMITx_GetHdcpKey(MS_BOOL useinternalkey, MS_U8 *data); 328 329 // HDMI Tx clock power On/Off 330 INTERFACED void MDrv_HDMITx_Power_OnOff(MS_BOOL bEnable); 331 332 // HDMI Tx module On/Off 333 INTERFACED void MDrv_HDMITx_TurnOnOff(void); 334 335 // HDMI Tx output is DVI / HDMI mode 336 INTERFACED void MDrv_HDMITx_SetHDMITxMode(void); 337 338 // HDMI Tx TMDS signal On/Off 339 INTERFACED void MDrv_HDMITx_SetTMDSOnOff(void); 340 341 // This routine set video output On/Off 342 INTERFACED void MDrv_HDMITx_SetVideoOnOff(void); 343 344 // This routine set video color format 345 INTERFACED void MDrv_HDMITx_SetColorFormat(void); 346 347 // This routine set VS infoframe content for 3D or 4k2k 348 INTERFACED void MDrv_HDMITx_Set_VS_InfoFrame(void); 349 350 // This routine set video output mode (color/repetition/regen) 351 INTERFACED void MDrv_HDMITx_SetVideoOutputMode(void); 352 353 // This routine set video aspect ratio 354 INTERFACED void MDrv_HDMITx_SetVideoOutputAsepctRatio(void); 355 356 // This routine set video scan info and AFD 357 INTERFACED void MDrv_HDMITx_SetVideoOutputOverscan_AFD(void); 358 359 // This routine turn On/off Audio module. 360 INTERFACED void MDrv_HDMITx_SetAudioOnOff(void); 361 362 // This routine set audio sampling freq. 363 INTERFACED void MDrv_HDMITx_SetAudioFrequency(void); 364 365 // This routine get audio CTS value. 366 INTERFACEE MS_U32 MDrv_HDMITx_GetAudioCTS(void); 367 368 // This routine mute audio FIFO. 369 INTERFACEE void MDrv_HDMITx_MuteAudioFIFO(MS_BOOL bflag); 370 371 // This routine set HDMI Tx HDCP encryption On/Off 372 INTERFACED void MDrv_HDMITx_SetHDCPOnOff(void); 373 374 // This routine set HDMI Tx audio sorce format 375 INTERFACED void MDrv_HDMITx_SetAudioSourceFormat(MsHDMITX_AUDIO_SOURCE_FORMAT fmt); 376 377 INTERFACED void MDrv_HDMITx_Exhibit(void); 378 379 // This routine control HDMI packet generation 380 INTERFACED void MDrv_HDMITx_EnablePacketGen(MS_BOOL bflag); 381 // This routine force HDMITx output mode 382 INTERFACED void MDrv_HDMITx_ForceHDMIOutputMode(MS_BOOL bflag, MsHDMITX_OUTPUT_MODE output_mode); 383 384 // This routine force HDMITx output color format 385 INTERFACED MS_BOOL MDrv_HDMITx_ForceHDMIOutputColorFormat(MS_BOOL bflag, MsHDMITX_VIDEO_COLOR_FORMAT output_color); 386 387 // This routine set HDMI Tx AVMUTE 388 INTERFACED void MDrv_HDMITx_SetAVMUTE(MS_BOOL bflag); 389 390 // This routine check and set the related format by EDID 391 INTERFACED MS_BOOL MDrv_HDMITx_EdidChecking(void); 392 393 // This routine gets Rx's supported 3D structures of specific timing from EDID 394 INTERFACED MS_BOOL MDrv_HDMITx_GetRx3DStructureFromEDID(MsHDMITX_VIDEO_TIMING timing, MsHDMITX_EDID_3D_STRUCTURE_ALL *p3DStructure); 395 396 // This function do the RxBypass mode related setting 397 INTERFACED MS_BOOL MDrv_HDMITx_RxBypass_Mode(MsHDMITX_INPUT_FREQ freq, MS_BOOL bflag); 398 399 // This function disable RxBypass mode 400 INTERFACED MS_BOOL MDrv_HDMITx_Disable_RxBypass(void); 401 402 // This function clear settings of user defined packet 403 INTERFACEE void MDrv_HDMITx_PKT_User_Define_Clear(void); 404 405 // This function set user defined hdmi packet 406 INTERFACEE void MDrv_HDMITx_PKT_User_Define(MsHDMITX_PACKET_TYPE packet_type, MS_BOOL def_flag, 407 MsHDMITX_PACKET_PROCESS def_process, MS_U8 def_fcnt); 408 409 // This function let user define hdmi packet content 410 INTERFACEE MS_BOOL MDrv_HDMITx_PKT_Content_Define(MsHDMITX_PACKET_TYPE packet_type, MS_U8* data, MS_U8 length); 411 412 // The function to set the time interval from sent aksv to R0. 413 INTERFACEE void MDrv_HDMITx_SetAksv2R0Interval(MS_U32 u32Interval); 414 415 // The function start/stop HDCP authentication 416 INTERFACEE void MDrv_HDMITx_HDCP_StartAuth(MS_BOOL bFlag); 417 418 // Debug 419 /** 420 * @brief HDMI Info 421 */ 422 typedef struct 423 { 424 MS_U8 Reserved; 425 }MS_HDMI_TX_INFO; 426 427 /** 428 * @brief HDMI Status 429 */ 430 typedef struct 431 { 432 MS_BOOL bIsInitialized; 433 MS_BOOL bIsRunning; 434 }MS_HDMI_TX_Status; 435 436 MS_BOOL MDrv_HDMITx_GetLibVer(const MSIF_Version **ppVersion); ///< Get version (without Mutex protect) 437 MS_BOOL MDrv_HDMITx_GetInfo(MS_HDMI_TX_INFO *pInfo); 438 MS_BOOL MDrv_HDMITx_GetStatus(MS_HDMI_TX_Status *pStatus); 439 440 /** 441 * @brief set debug mask 442 * @param[in] u16DbgSwitch DEBUG MASK, 443 * 0x01: Debug HDMITX, 444 * 0x02: Debug HDCP 445 */ 446 MS_BOOL MDrv_HDMITx_SetDbgLevel(MS_U16 u16DbgSwitch); 447 448 void MDrv_HDMITx_SetHPDGpioPin(MS_U8 u8pin); 449 MS_BOOL MDrv_HDMITx_IsHDCPRxValid(void); 450 MS_BOOL MDrv_HDMITx_IsSupportDVIMode(void); 451 void MDrv_HDMITx_HDCP_RevocationKey_List(MS_U8 *data, MS_U16 size); 452 MDrvHDMITX_REVOCATION_STATE MDrv_HDMITx_HDCP_RevocationKey_Check(void); 453 454 // ************* For customer NDS **************// 455 MS_BOOL MDrv_HDMITx_GetRxStatus(void); 456 MS_BOOL MDrv_HDMITx_HDCP_IsSRMSignatureValid(MS_U8 *data, MS_U32 size); 457 MS_BOOL MDrv_HDMITx_HDCP_CheckRevokedKey(void); 458 MS_U32 MDrv_HDMITx_SetPowerState(EN_POWER_MODE u16PowerState); 459 #ifdef CUSTOMER_NDS 460 void MDrv_HDMITx_EnableRxStatusChecking(MS_BOOL bflag); 461 MS_BOOL MDrv_HDMITx_EdidReadBlock(MS_U8 num, MS_U8 *data); 462 void MDrv_HDMITx_Set_AVI_InfoFrame(MsHDMITX_AVI_CONTENT_TYPE content_type, MS_U16 *data); 463 void MDrv_HDMITx_Set_AVMUTE(MS_BOOL bflag); 464 MS_BOOL MDrv_HDMITx_HDCP_Get_BCaps(MS_U8 *u8bcaps); 465 MS_BOOL MDrv_HDMITx_HDCP_Get_BStatus(MS_U16 *u16bstatus); 466 void MDrv_HDMITx_HDCP_Reset_SRM(void); 467 MS_BOOL MDrv_HDMITx_HDCP_Start_Authentication(void); 468 MS_BOOL MDrv_HDMITx_HDCP_Stop_Authentication(void); 469 void MDrv_HDMITx_HdcpSetEncrypt(MS_BOOL bflag); 470 void MDrv_HDMITx_HDCP_Get_HDCP_Status(MS_U8 *status); 471 void MDrv_HDMITx_HDCP_Configure(HDMIHDCPConfiguration *arg); 472 void MDrv_HDMITx_FSM_ChangeState(MDrvHDMITX_FSM_STATE state); 473 #endif 474 475 #ifdef __cplusplus 476 } 477 #endif 478 479 #endif // _DRV_HDMITX_H_ 480 481