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MStar hereby reserves the 91*53ee8cc1Swenshuai.xi // rights to any and all damages, losses, costs and expenses resulting therefrom. 92*53ee8cc1Swenshuai.xi // 93*53ee8cc1Swenshuai.xi //////////////////////////////////////////////////////////////////////////////// 94*53ee8cc1Swenshuai.xi 95*53ee8cc1Swenshuai.xi /////////////////////////////////////////////////////////////////////////////////////////////////// 96*53ee8cc1Swenshuai.xi /// 97*53ee8cc1Swenshuai.xi /// @file drvDMD_common.h 98*53ee8cc1Swenshuai.xi /// @brief DVBC Driver Interface 99*53ee8cc1Swenshuai.xi /// @author MStar Semiconductor Inc. 100*53ee8cc1Swenshuai.xi /////////////////////////////////////////////////////////////////////////////////////////////////// 101*53ee8cc1Swenshuai.xi 102*53ee8cc1Swenshuai.xi /*! \defgroup Demod Demod interface 103*53ee8cc1Swenshuai.xi 104*53ee8cc1Swenshuai.xi 105*53ee8cc1Swenshuai.xi Peripheral functions are controlled by each DEMOD standard 106*53ee8cc1Swenshuai.xi 107*53ee8cc1Swenshuai.xi <b>Features</b> 108*53ee8cc1Swenshuai.xi 109*53ee8cc1Swenshuai.xi - Registers read/write. 110*53ee8cc1Swenshuai.xi - I2C, RF/IF, TS and SSPI control. 111*53ee8cc1Swenshuai.xi 112*53ee8cc1Swenshuai.xi <b>ATSC Interface brief</b> 113*53ee8cc1Swenshuai.xi ATSC is the demodulator of supporting 8VSB and J83B standard. 114*53ee8cc1Swenshuai.xi Receive RF signal from Tuner and transmit demodulated data to TS module. 115*53ee8cc1Swenshuai.xi 116*53ee8cc1Swenshuai.xi <b>Features</b> 117*53ee8cc1Swenshuai.xi 118*53ee8cc1Swenshuai.xi - Support 8VSB and J83B standard. 119*53ee8cc1Swenshuai.xi - Pass A74 SPEC. 120*53ee8cc1Swenshuai.xi - Pass the field stream. 121*53ee8cc1Swenshuai.xi 122*53ee8cc1Swenshuai.xi <b> ATSC Block Diagram: </b> \n 123*53ee8cc1Swenshuai.xi \image html drvDMD_ATSC_pic01.png 124*53ee8cc1Swenshuai.xi 125*53ee8cc1Swenshuai.xi <b> Operation Code Flow: </b> \n 126*53ee8cc1Swenshuai.xi -# Initialize ATSC parameters and load DEMOD FW 127*53ee8cc1Swenshuai.xi -# Enable DEMOD state machine 128*53ee8cc1Swenshuai.xi -# Monitor lock status 129*53ee8cc1Swenshuai.xi 130*53ee8cc1Swenshuai.xi <b>DTMB interface brief</b> 131*53ee8cc1Swenshuai.xi DTMB is the demodulator of supporting DTMB(6/7/8/9M) standard. 132*53ee8cc1Swenshuai.xi Receive RF signal from Tuner and transmit demodulated data to TS module. 133*53ee8cc1Swenshuai.xi 134*53ee8cc1Swenshuai.xi <b>Features</b> 135*53ee8cc1Swenshuai.xi 136*53ee8cc1Swenshuai.xi - Support DTMB(6/7/8/9M) standard. 137*53ee8cc1Swenshuai.xi - Pass CHINA SPEC. 138*53ee8cc1Swenshuai.xi - Pass the field stream. 139*53ee8cc1Swenshuai.xi 140*53ee8cc1Swenshuai.xi <b> DTMB Block Diagram: </b> \n 141*53ee8cc1Swenshuai.xi \image html drvDMD_DTMB_pic01.png 142*53ee8cc1Swenshuai.xi 143*53ee8cc1Swenshuai.xi <b> Operation Code Flow: </b> \n 144*53ee8cc1Swenshuai.xi -# Initialize DTMB parameters and load DEMOD FW 145*53ee8cc1Swenshuai.xi -# Enable DEMOD state machine 146*53ee8cc1Swenshuai.xi -# Monitor lock status 147*53ee8cc1Swenshuai.xi 148*53ee8cc1Swenshuai.xi *! \defgroup COMMON COMMON interface (drvDMD_common.h) 149*53ee8cc1Swenshuai.xi * \ingroup Demod 150*53ee8cc1Swenshuai.xi 151*53ee8cc1Swenshuai.xi *! \defgroup COMMON_BASIC COMMON basic control 152*53ee8cc1Swenshuai.xi * \ingroup COMMON 153*53ee8cc1Swenshuai.xi */ 154*53ee8cc1Swenshuai.xi 155*53ee8cc1Swenshuai.xi #ifndef _DRV_DMD_COMMON_H_ 156*53ee8cc1Swenshuai.xi #define _DRV_DMD_COMMON_H_ 157*53ee8cc1Swenshuai.xi 158*53ee8cc1Swenshuai.xi #ifdef __cplusplus 159*53ee8cc1Swenshuai.xi extern "C" 160*53ee8cc1Swenshuai.xi { 161*53ee8cc1Swenshuai.xi #endif 162*53ee8cc1Swenshuai.xi 163*53ee8cc1Swenshuai.xi 164*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 165*53ee8cc1Swenshuai.xi // Driver Capability 166*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 167*53ee8cc1Swenshuai.xi 168*53ee8cc1Swenshuai.xi 169*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 170*53ee8cc1Swenshuai.xi // Macro and Define 171*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 172*53ee8cc1Swenshuai.xi #define USE_UTOPIA2P0 173*53ee8cc1Swenshuai.xi 174*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 175*53ee8cc1Swenshuai.xi // Type and Structure 176*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 177*53ee8cc1Swenshuai.xi typedef enum 178*53ee8cc1Swenshuai.xi { 179*53ee8cc1Swenshuai.xi _QPSK = 0x0, 180*53ee8cc1Swenshuai.xi _16QAM = 0x1, 181*53ee8cc1Swenshuai.xi _64QAM = 0x2, 182*53ee8cc1Swenshuai.xi _UNKNOW_QAM = 0xff, 183*53ee8cc1Swenshuai.xi }DMD_CONSTEL; 184*53ee8cc1Swenshuai.xi 185*53ee8cc1Swenshuai.xi typedef enum 186*53ee8cc1Swenshuai.xi { 187*53ee8cc1Swenshuai.xi _CR1Y2 = 0x0, 188*53ee8cc1Swenshuai.xi _CR2Y3 = 0x1, 189*53ee8cc1Swenshuai.xi _CR3Y4 = 0x2, 190*53ee8cc1Swenshuai.xi _CR5Y6 = 0x3, 191*53ee8cc1Swenshuai.xi _CR7Y8 = 0x4, 192*53ee8cc1Swenshuai.xi _UNKNOW_CR = 0xff, 193*53ee8cc1Swenshuai.xi }DMD_CODERATE; 194*53ee8cc1Swenshuai.xi 195*53ee8cc1Swenshuai.xi typedef struct 196*53ee8cc1Swenshuai.xi { 197*53ee8cc1Swenshuai.xi float power_db; 198*53ee8cc1Swenshuai.xi MS_U8 sar3_val; 199*53ee8cc1Swenshuai.xi }DMD_RFAGC_SSI; 200*53ee8cc1Swenshuai.xi 201*53ee8cc1Swenshuai.xi typedef struct 202*53ee8cc1Swenshuai.xi { 203*53ee8cc1Swenshuai.xi float power_db; 204*53ee8cc1Swenshuai.xi MS_U8 agc_val; 205*53ee8cc1Swenshuai.xi }DMD_IFAGC_SSI; 206*53ee8cc1Swenshuai.xi 207*53ee8cc1Swenshuai.xi typedef struct 208*53ee8cc1Swenshuai.xi { 209*53ee8cc1Swenshuai.xi float attn_db; 210*53ee8cc1Swenshuai.xi MS_U8 agc_err; 211*53ee8cc1Swenshuai.xi }DMD_IFAGC_ERR; 212*53ee8cc1Swenshuai.xi 213*53ee8cc1Swenshuai.xi typedef struct 214*53ee8cc1Swenshuai.xi { 215*53ee8cc1Swenshuai.xi DMD_CONSTEL constel; 216*53ee8cc1Swenshuai.xi DMD_CODERATE code_rate; 217*53ee8cc1Swenshuai.xi float p_ref; 218*53ee8cc1Swenshuai.xi }DMD_SSI_DBM_NORDIGP1; 219*53ee8cc1Swenshuai.xi 220*53ee8cc1Swenshuai.xi typedef struct 221*53ee8cc1Swenshuai.xi { 222*53ee8cc1Swenshuai.xi DMD_CONSTEL constel; 223*53ee8cc1Swenshuai.xi DMD_CODERATE code_rate; 224*53ee8cc1Swenshuai.xi float cn_ref; 225*53ee8cc1Swenshuai.xi }DMD_SQI_CN_NORDIGP1; 226*53ee8cc1Swenshuai.xi 227*53ee8cc1Swenshuai.xi typedef struct 228*53ee8cc1Swenshuai.xi { 229*53ee8cc1Swenshuai.xi DMD_RFAGC_SSI *pRfagcSsi; 230*53ee8cc1Swenshuai.xi MS_U16 u16RfagcSsi_Size; 231*53ee8cc1Swenshuai.xi DMD_IFAGC_SSI *pIfagcSsi_LoRef; 232*53ee8cc1Swenshuai.xi MS_U16 u16IfagcSsi_LoRef_Size; 233*53ee8cc1Swenshuai.xi DMD_IFAGC_SSI *pIfagcSsi_HiRef; 234*53ee8cc1Swenshuai.xi MS_U16 u16IfagcSsi_HiRef_Size; 235*53ee8cc1Swenshuai.xi DMD_IFAGC_ERR *pIfagcErr_LoRef; 236*53ee8cc1Swenshuai.xi MS_U16 u16IfagcErr_LoRef_Size; 237*53ee8cc1Swenshuai.xi DMD_IFAGC_ERR *pIfagcErr_HiRef; 238*53ee8cc1Swenshuai.xi MS_U16 u16IfagcErr_HiRef_Size; 239*53ee8cc1Swenshuai.xi }DMD_SSI_TABLE; 240*53ee8cc1Swenshuai.xi 241*53ee8cc1Swenshuai.xi typedef struct _s_I2C_Interface_func 242*53ee8cc1Swenshuai.xi { 243*53ee8cc1Swenshuai.xi MS_BOOL (*I2C_WriteBytes)(MS_U16 u16BusNumSlaveID, MS_U8 u8addrcount, MS_U8* pu8addr, MS_U16 u16size, MS_U8* pu8data); 244*53ee8cc1Swenshuai.xi MS_BOOL (*I2C_ReadBytes)(MS_U16 u16BusNumSlaveID, MS_U8 u8AddrNum, MS_U8* paddr, MS_U16 u16size, MS_U8* pu8data); 245*53ee8cc1Swenshuai.xi }s_I2C_Interface_func; 246*53ee8cc1Swenshuai.xi 247*53ee8cc1Swenshuai.xi 248*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 249*53ee8cc1Swenshuai.xi // Function and Variable 250*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 251*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 252*53ee8cc1Swenshuai.xi /// Register DEMOD bank address 253*53ee8cc1Swenshuai.xi /// @ingroup COMMON_BASIC 254*53ee8cc1Swenshuai.xi /// @return TRUE : succeed 255*53ee8cc1Swenshuai.xi /// @return FALSE : fail 256*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 257*53ee8cc1Swenshuai.xi DLL_PUBLIC MS_BOOL MDrv_DMD_PreInit(void); 258*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 259*53ee8cc1Swenshuai.xi /// Enable RF AGC Tristate 260*53ee8cc1Swenshuai.xi /// @ingroup COMMON_BASIC 261*53ee8cc1Swenshuai.xi /// @param bEnable \b IN: Enable as TRUE 262*53ee8cc1Swenshuai.xi /// @return : NULL 263*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 264*53ee8cc1Swenshuai.xi DLL_PUBLIC void MDrv_DMD_RFAGC_Tristate(MS_BOOL bEnable); 265*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 266*53ee8cc1Swenshuai.xi /// Enable IF AGC Tristate 267*53ee8cc1Swenshuai.xi /// @ingroup COMMON_BASIC 268*53ee8cc1Swenshuai.xi /// @param bEnable \b IN: Enable as TRUE 269*53ee8cc1Swenshuai.xi /// @return : NULL 270*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 271*53ee8cc1Swenshuai.xi DLL_PUBLIC void MDrv_DMD_IFAGC_Tristate(MS_BOOL bEnable); 272*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 273*53ee8cc1Swenshuai.xi /// Get TS clock rate 274*53ee8cc1Swenshuai.xi /// @ingroup COMMON_BASIC 275*53ee8cc1Swenshuai.xi /// @param fTS_CLK \b OUT: the pointer to TS clock rate 276*53ee8cc1Swenshuai.xi /// @return TRUE : succeed 277*53ee8cc1Swenshuai.xi /// @return FALSE : fail 278*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 279*53ee8cc1Swenshuai.xi // DLL_PUBLIC MS_BOOL MDrv_DMD_TS_GetClockRate(float *fTS_CLK); 280*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 281*53ee8cc1Swenshuai.xi /// ts output clock frequency and phase configure 282*53ee8cc1Swenshuai.xi /// @ingroup COMMON_BASIC 283*53ee8cc1Swenshuai.xi /// @param u8cmd_array \b IN: the pointer to TS clock configuration 284*53ee8cc1Swenshuai.xi /// @return TRUE : succeed 285*53ee8cc1Swenshuai.xi /// @return FALSE : fail 286*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 287*53ee8cc1Swenshuai.xi DLL_PUBLIC MS_BOOL MDrv_DMD_TSO_Clk_Control(MS_U8 *u8cmd_array); 288*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 289*53ee8cc1Swenshuai.xi /// read register data 290*53ee8cc1Swenshuai.xi /// @ingroup COMMON_BASIC 291*53ee8cc1Swenshuai.xi /// @param u32Reg \b IN: register address 292*53ee8cc1Swenshuai.xi /// @param u8Value \b OUT: the pointer to register data 293*53ee8cc1Swenshuai.xi /// @return TRUE : succeed 294*53ee8cc1Swenshuai.xi /// @return FALSE : fail 295*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 296*53ee8cc1Swenshuai.xi DLL_PUBLIC MS_BOOL MDrv_DMD_ReadReg(MS_U32 u32Reg, MS_U8 *u8Value); 297*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 298*53ee8cc1Swenshuai.xi /// write register data 299*53ee8cc1Swenshuai.xi /// @ingroup COMMON_BASIC 300*53ee8cc1Swenshuai.xi /// @param u32Reg \b IN: register address 301*53ee8cc1Swenshuai.xi /// @param u8Value \b IN: register data 302*53ee8cc1Swenshuai.xi /// @return TRUE : succeed 303*53ee8cc1Swenshuai.xi /// @return FALSE : fail 304*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 305*53ee8cc1Swenshuai.xi DLL_PUBLIC MS_BOOL MDrv_DMD_WriteReg(MS_U32 u32Reg, MS_U8 u8Value); 306*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 307*53ee8cc1Swenshuai.xi /// write register data for more than one byte 308*53ee8cc1Swenshuai.xi /// @ingroup COMMON_BASIC 309*53ee8cc1Swenshuai.xi /// @param u32Reg \b IN: register address 310*53ee8cc1Swenshuai.xi /// @param u8Value \b IN: the pointer to data 311*53ee8cc1Swenshuai.xi /// @param u8Length \b IN: length of data 312*53ee8cc1Swenshuai.xi /// @return TRUE : succeed 313*53ee8cc1Swenshuai.xi /// @return FALSE : fail 314*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 315*53ee8cc1Swenshuai.xi // DLL_PUBLIC MS_BOOL MDrv_DMD_WriteRegs(MS_U32 u32Reg, MS_U8 *u8Value, MS_U8 u8Length); 316*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 317*53ee8cc1Swenshuai.xi /// Change I2C channel 318*53ee8cc1Swenshuai.xi /// @ingroup COMMON_BASIC 319*53ee8cc1Swenshuai.xi /// @param ch_num \b IN: I2C channel number 320*53ee8cc1Swenshuai.xi /// @return TRUE : succeed 321*53ee8cc1Swenshuai.xi /// @return FALSE : fail 322*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 323*53ee8cc1Swenshuai.xi // DLL_PUBLIC MS_BOOL MDrv_DMD_I2C_Channel_Change(MS_U8 ch_num); 324*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 325*53ee8cc1Swenshuai.xi /// Set I2C channel 326*53ee8cc1Swenshuai.xi /// @ingroup COMMON_BASIC 327*53ee8cc1Swenshuai.xi /// @param ch_num \b IN: I2C channel number 328*53ee8cc1Swenshuai.xi /// @return TRUE : succeed 329*53ee8cc1Swenshuai.xi /// @return FALSE : fail 330*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 331*53ee8cc1Swenshuai.xi // DLL_PUBLIC MS_BOOL MDrv_DMD_I2C_Channel_Set(MS_U8 ch_num); 332*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 333*53ee8cc1Swenshuai.xi /// Initialize SSPI interface 334*53ee8cc1Swenshuai.xi /// @ingroup COMMON_BASIC 335*53ee8cc1Swenshuai.xi /// @param u8DeviceNum \b IN: SSPI device number 336*53ee8cc1Swenshuai.xi /// @return TRUE : succeed 337*53ee8cc1Swenshuai.xi /// @return FALSE : fail 338*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 339*53ee8cc1Swenshuai.xi // DLL_PUBLIC MS_BOOL MDrv_DMD_SSPI_Init(MS_U8 u8DeviceNum); 340*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 341*53ee8cc1Swenshuai.xi /// MIU write data more than one byte per SSPI interface 342*53ee8cc1Swenshuai.xi /// @ingroup COMMON_BASIC 343*53ee8cc1Swenshuai.xi /// @param u32Addr \b IN: register address 344*53ee8cc1Swenshuai.xi /// @param pdata \b IN: the pointer to data 345*53ee8cc1Swenshuai.xi /// @param u16Size \b IN: length of data 346*53ee8cc1Swenshuai.xi /// @return TRUE : succeed 347*53ee8cc1Swenshuai.xi /// @return FALSE : fail 348*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 349*53ee8cc1Swenshuai.xi // DLL_PUBLIC MS_BOOL MDrv_DMD_SSPI_MIU_Writes(MS_U32 u32Addr, MS_U8 *pdata, MS_U16 u16Size); 350*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 351*53ee8cc1Swenshuai.xi /// MIU read data more than one byte per SSPI interface 352*53ee8cc1Swenshuai.xi /// @ingroup COMMON_BASIC 353*53ee8cc1Swenshuai.xi /// @param u32Addr \b IN: register address 354*53ee8cc1Swenshuai.xi /// @param pdata \b IN: the pointer to data 355*53ee8cc1Swenshuai.xi /// @param u16Size \b IN: length of data 356*53ee8cc1Swenshuai.xi /// @return TRUE : succeed 357*53ee8cc1Swenshuai.xi /// @return FALSE : fail 358*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 359*53ee8cc1Swenshuai.xi // DLL_PUBLIC MS_BOOL MDrv_DMD_SSPI_MIU_Reads(MS_U32 u32Addr, MS_U8 *pdata, MS_U16 u16Size); 360*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 361*53ee8cc1Swenshuai.xi /// MIU write data per SSPI interface 362*53ee8cc1Swenshuai.xi /// @ingroup COMMON_BASIC 363*53ee8cc1Swenshuai.xi /// @param u16Addr \b IN: register address 364*53ee8cc1Swenshuai.xi /// @param data \b IN: register data 365*53ee8cc1Swenshuai.xi /// @return TRUE : succeed 366*53ee8cc1Swenshuai.xi /// @return FALSE : fail 367*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 368*53ee8cc1Swenshuai.xi // DLL_PUBLIC MS_BOOL MDrv_DMD_SSPI_RIU_Write8(MS_U16 u16Addr, MS_U8 data); 369*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 370*53ee8cc1Swenshuai.xi /// MIU read data per SSPI interface 371*53ee8cc1Swenshuai.xi /// @ingroup COMMON_BASIC 372*53ee8cc1Swenshuai.xi /// @param u16Addr \b IN: register address 373*53ee8cc1Swenshuai.xi /// @param pdata \b out: register data 374*53ee8cc1Swenshuai.xi /// @return TRUE : succeed 375*53ee8cc1Swenshuai.xi /// @return FALSE : fail 376*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 377*53ee8cc1Swenshuai.xi // DLL_PUBLIC MS_BOOL MDrv_DMD_SSPI_RIU_Read8(MS_U16 u16Addr, MS_U8 *pdata); 378*53ee8cc1Swenshuai.xi 379*53ee8cc1Swenshuai.xi #ifdef __cplusplus 380*53ee8cc1Swenshuai.xi } 381*53ee8cc1Swenshuai.xi #endif 382*53ee8cc1Swenshuai.xi 383*53ee8cc1Swenshuai.xi 384*53ee8cc1Swenshuai.xi #endif // _DRV_DVBC_H_ 385*53ee8cc1Swenshuai.xi 386