1*53ee8cc1Swenshuai.xi //<MStar Software> 2*53ee8cc1Swenshuai.xi //****************************************************************************** 3*53ee8cc1Swenshuai.xi // MStar Software 4*53ee8cc1Swenshuai.xi // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5*53ee8cc1Swenshuai.xi // All software, firmware and related documentation herein ("MStar Software") are 6*53ee8cc1Swenshuai.xi // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7*53ee8cc1Swenshuai.xi // law, including, but not limited to, copyright law and international treaties. 8*53ee8cc1Swenshuai.xi // Any use, modification, reproduction, retransmission, or republication of all 9*53ee8cc1Swenshuai.xi // or part of MStar Software is expressly prohibited, unless prior written 10*53ee8cc1Swenshuai.xi // permission has been granted by MStar. 11*53ee8cc1Swenshuai.xi // 12*53ee8cc1Swenshuai.xi // By accessing, browsing and/or using MStar Software, you acknowledge that you 13*53ee8cc1Swenshuai.xi // have read, understood, and agree, to be bound by below terms ("Terms") and to 14*53ee8cc1Swenshuai.xi // comply with all applicable laws and regulations 15*53ee8cc1Swenshuai.xi // 16*53ee8cc1Swenshuai.xi // 1. MStar shall retain any and all right, ownership and interest to MStar 17*53ee8cc1Swenshuai.xi // Software and any modification/derivatives thereof. 18*53ee8cc1Swenshuai.xi // No right, ownership, or interest to MStar Software and any 19*53ee8cc1Swenshuai.xi // modification/derivatives thereof is transferred to you under Terms. 20*53ee8cc1Swenshuai.xi // 21*53ee8cc1Swenshuai.xi // 2. You understand that MStar Software might include, incorporate or be 22*53ee8cc1Swenshuai.xi // supplied together with third party`s software and the use of MStar 23*53ee8cc1Swenshuai.xi // Software may require additional licenses from third parties. 24*53ee8cc1Swenshuai.xi // Therefore, you hereby agree it is your sole responsibility to separately 25*53ee8cc1Swenshuai.xi // obtain any and all third party right and license necessary for your use of 26*53ee8cc1Swenshuai.xi // such third party`s software. 27*53ee8cc1Swenshuai.xi // 28*53ee8cc1Swenshuai.xi // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29*53ee8cc1Swenshuai.xi // MStar`s confidential information and you agree to keep MStar`s 30*53ee8cc1Swenshuai.xi // confidential information in strictest confidence and not disclose to any 31*53ee8cc1Swenshuai.xi // third party. 32*53ee8cc1Swenshuai.xi // 33*53ee8cc1Swenshuai.xi // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34*53ee8cc1Swenshuai.xi // kind. Any warranties are hereby expressly disclaimed by MStar, including 35*53ee8cc1Swenshuai.xi // without limitation, any warranties of merchantability, non-infringement of 36*53ee8cc1Swenshuai.xi // intellectual property rights, fitness for a particular purpose, error free 37*53ee8cc1Swenshuai.xi // and in conformity with any international standard. You agree to waive any 38*53ee8cc1Swenshuai.xi // claim against MStar for any loss, damage, cost or expense that you may 39*53ee8cc1Swenshuai.xi // incur related to your use of MStar Software. 40*53ee8cc1Swenshuai.xi // In no event shall MStar be liable for any direct, indirect, incidental or 41*53ee8cc1Swenshuai.xi // consequential damages, including without limitation, lost of profit or 42*53ee8cc1Swenshuai.xi // revenues, lost or damage of data, and unauthorized system use. 43*53ee8cc1Swenshuai.xi // You agree that this Section 4 shall still apply without being affected 44*53ee8cc1Swenshuai.xi // even if MStar Software has been modified by MStar in accordance with your 45*53ee8cc1Swenshuai.xi // request or instruction for your use, except otherwise agreed by both 46*53ee8cc1Swenshuai.xi // parties in writing. 47*53ee8cc1Swenshuai.xi // 48*53ee8cc1Swenshuai.xi // 5. If requested, MStar may from time to time provide technical supports or 49*53ee8cc1Swenshuai.xi // services in relation with MStar Software to you for your use of 50*53ee8cc1Swenshuai.xi // MStar Software in conjunction with your or your customer`s product 51*53ee8cc1Swenshuai.xi // ("Services"). 52*53ee8cc1Swenshuai.xi // You understand and agree that, except otherwise agreed by both parties in 53*53ee8cc1Swenshuai.xi // writing, Services are provided on an "AS IS" basis and the warranty 54*53ee8cc1Swenshuai.xi // disclaimer set forth in Section 4 above shall apply. 55*53ee8cc1Swenshuai.xi // 56*53ee8cc1Swenshuai.xi // 6. Nothing contained herein shall be construed as by implication, estoppels 57*53ee8cc1Swenshuai.xi // or otherwise 58*53ee8cc1Swenshuai.xi // (a) conferring any license or right to use MStar name, trademark, service 59*53ee8cc1Swenshuai.xi // mark, symbol or any other identification; 60*53ee8cc1Swenshuai.xi // (b) obligating MStar or any of its affiliates to furnish any person, 61*53ee8cc1Swenshuai.xi // including without limitation, you and your customers, any assistance 62*53ee8cc1Swenshuai.xi // of any kind whatsoever, or any information; or 63*53ee8cc1Swenshuai.xi // (c) conferring any license or right under any intellectual property right. 64*53ee8cc1Swenshuai.xi // 65*53ee8cc1Swenshuai.xi // 7. These terms shall be governed by and construed in accordance with the laws 66*53ee8cc1Swenshuai.xi // of Taiwan, R.O.C., excluding its conflict of law rules. 67*53ee8cc1Swenshuai.xi // Any and all dispute arising out hereof or related hereto shall be finally 68*53ee8cc1Swenshuai.xi // settled by arbitration referred to the Chinese Arbitration Association, 69*53ee8cc1Swenshuai.xi // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70*53ee8cc1Swenshuai.xi // Rules of the Association by three (3) arbitrators appointed in accordance 71*53ee8cc1Swenshuai.xi // with the said Rules. 72*53ee8cc1Swenshuai.xi // The place of arbitration shall be in Taipei, Taiwan and the language shall 73*53ee8cc1Swenshuai.xi // be English. 74*53ee8cc1Swenshuai.xi // The arbitration award shall be final and binding to both parties. 75*53ee8cc1Swenshuai.xi // 76*53ee8cc1Swenshuai.xi //****************************************************************************** 77*53ee8cc1Swenshuai.xi 78*53ee8cc1Swenshuai.xi #ifndef _VDEC_EX_V2_H_ 79*53ee8cc1Swenshuai.xi #define _VDEC_EX_V2_H_ 80*53ee8cc1Swenshuai.xi 81*53ee8cc1Swenshuai.xi #if !defined(MSOS_TYPE_NUTTX) || defined(SUPPORT_X_MODEL_FEATURE) 82*53ee8cc1Swenshuai.xi #ifdef __cplusplus 83*53ee8cc1Swenshuai.xi extern "C" 84*53ee8cc1Swenshuai.xi { 85*53ee8cc1Swenshuai.xi #endif 86*53ee8cc1Swenshuai.xi 87*53ee8cc1Swenshuai.xi #include "MsTypes.h" 88*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 89*53ee8cc1Swenshuai.xi // Define for Upper layer 90*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 91*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 92*53ee8cc1Swenshuai.xi // Macro and Define 93*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 94*53ee8cc1Swenshuai.xi #define MSIF_VDEC_EX_V2_LIB_CODE {'V','E','X','2'} 95*53ee8cc1Swenshuai.xi #define MSIF_VDEC_EX_V2_LIBVER {'0','5'} 96*53ee8cc1Swenshuai.xi #define MSIF_VDEC_EX_V2_BUILDNUM {'0','3'} 97*53ee8cc1Swenshuai.xi #define MSIF_VDEC_EX_V2_CHANGELIST {'0','0','6','9','3','0','7','7'} 98*53ee8cc1Swenshuai.xi 99*53ee8cc1Swenshuai.xi /// Version string. 100*53ee8cc1Swenshuai.xi #define VDEC_EX_V2_API_VERSION /* Character String for DRV/API version */ \ 101*53ee8cc1Swenshuai.xi MSIF_TAG, /* 'MSIF' */ \ 102*53ee8cc1Swenshuai.xi MSIF_CLASS, /* '00' */ \ 103*53ee8cc1Swenshuai.xi MSIF_CUS, /* 0x0000 */ \ 104*53ee8cc1Swenshuai.xi MSIF_MOD, /* 0x0000 */ \ 105*53ee8cc1Swenshuai.xi MSIF_CHIP, \ 106*53ee8cc1Swenshuai.xi MSIF_CPU, \ 107*53ee8cc1Swenshuai.xi MSIF_VDEC_EX_V2_LIB_CODE, /* IP__ */ \ 108*53ee8cc1Swenshuai.xi MSIF_VDEC_EX_V2_LIBVER, /* 0.0 ~ Z.Z */ \ 109*53ee8cc1Swenshuai.xi MSIF_VDEC_EX_V2_BUILDNUM, /* 00 ~ 99 */ \ 110*53ee8cc1Swenshuai.xi MSIF_VDEC_EX_V2_CHANGELIST, /* CL# */ \ 111*53ee8cc1Swenshuai.xi MSIF_OS 112*53ee8cc1Swenshuai.xi 113*53ee8cc1Swenshuai.xi #define VDEC_EX_V2_DEFAULT_DBG_MSG_LEVEL E_VDEC_EX_DBG_LEVEL_DBG 114*53ee8cc1Swenshuai.xi #define VDEC_EX_V2_RVD_BROKEN_BY_US 0x80000000 115*53ee8cc1Swenshuai.xi #define VDEC_EX_V2_MVD_PIC_START_FLAG 0x40000000 116*53ee8cc1Swenshuai.xi 117*53ee8cc1Swenshuai.xi #define VDEC_EX_V2_BIT(_bit_) (1 << (_bit_)) 118*53ee8cc1Swenshuai.xi 119*53ee8cc1Swenshuai.xi #define VDEC_EX_V2_FPA_TYPE_CHECKERBOARD_INTERLEAVING 0 120*53ee8cc1Swenshuai.xi #define VDEC_EX_V2_FPA_TYPE_COLUMN_INTERLEAVEING 1 121*53ee8cc1Swenshuai.xi #define VDEC_EX_V2_FPA_TYPE_ROW_INTERLEAVEING 2 122*53ee8cc1Swenshuai.xi #define VDEC_EX_V2_FPA_TYPE_SIDE_BY_SIDE_PACKING 3 123*53ee8cc1Swenshuai.xi #define VDEC_EX_V2_FPA_TYPE_TOP_BOTTOM_PACKING 4 124*53ee8cc1Swenshuai.xi #define VDEC_EX_V2_FPA_TYPE_TEMPORAL_INTERLEAVING_FRM 5 125*53ee8cc1Swenshuai.xi #define VDEC_EX_V2_MAX_DEC_NUM 2 126*53ee8cc1Swenshuai.xi 127*53ee8cc1Swenshuai.xi #define VDEC_CAP_DYNAMIC_CMA 128*53ee8cc1Swenshuai.xi #define VDEC_CAP_DISABLE_HEVC_10BITS // MApi_VDEC_EX_PreSetControl((VDEC_StreamId *)pHandle, E_VDEC_EX_USER_CMD_VDEC_FEATURE, E_VDEC_EX_FEATURE_FORCE_MAIN_PROFILE); 129*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 130*53ee8cc1Swenshuai.xi // Type and Structure 131*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 132*53ee8cc1Swenshuai.xi 133*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 134*53ee8cc1Swenshuai.xi // Enum for Upper layer 135*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 136*53ee8cc1Swenshuai.xi typedef enum 137*53ee8cc1Swenshuai.xi { 138*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_MAIN_STREAM = 0, 139*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_SUB_STREAM, 140*53ee8cc1Swenshuai.xi } VDEC_EX_V2_Stream; 141*53ee8cc1Swenshuai.xi 142*53ee8cc1Swenshuai.xi /// decoder event enumerator. 143*53ee8cc1Swenshuai.xi typedef enum 144*53ee8cc1Swenshuai.xi { 145*53ee8cc1Swenshuai.xi /// turn off all event 146*53ee8cc1Swenshuai.xi E_VDEC_E_V2_EVENT_OFF = 0x00, 147*53ee8cc1Swenshuai.xi /// display one frame/field 148*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_EVENT_DISP_ONE = VDEC_EX_V2_BIT(0), 149*53ee8cc1Swenshuai.xi /// repeat one frame/field 150*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_EVENT_DISP_REPEAT = VDEC_EX_V2_BIT(1), 151*53ee8cc1Swenshuai.xi /// one CC data should be displayed 152*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_EVENT_DISP_WITH_CC = VDEC_EX_V2_BIT(2), 153*53ee8cc1Swenshuai.xi /// decode one frame 154*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_EVENT_DEC_ONE = VDEC_EX_V2_BIT(3), 155*53ee8cc1Swenshuai.xi /// decode one I frame 156*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_EVENT_DEC_I = VDEC_EX_V2_BIT(4), 157*53ee8cc1Swenshuai.xi /// decode error 158*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_EVENT_DEC_ERR = VDEC_EX_V2_BIT(5), 159*53ee8cc1Swenshuai.xi /// display information is changed 160*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_EVENT_DISP_INFO_CHG = VDEC_EX_V2_BIT(6), 161*53ee8cc1Swenshuai.xi /// find user data 162*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_EVENT_USER_DATA_FOUND = VDEC_EX_V2_BIT(7), 163*53ee8cc1Swenshuai.xi /// display information ready after be changed 164*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_EVENT_DISP_INFO_RDY = VDEC_EX_V2_BIT(8), 165*53ee8cc1Swenshuai.xi /// first frame decoded 166*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_EVENT_FIRST_FRAME = VDEC_EX_V2_BIT(9), 167*53ee8cc1Swenshuai.xi /// first picture found 168*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_EVENT_PIC_FOUND = VDEC_EX_V2_BIT(10), 169*53ee8cc1Swenshuai.xi /// video is ready to display (no garbage and avsync done) 170*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_EVENT_VIDEO_UNMUTE = VDEC_EX_V2_BIT(11), 171*53ee8cc1Swenshuai.xi /// new sequence header found 172*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_EVENT_SEQ_HDR_FOUND = VDEC_EX_V2_BIT(12), 173*53ee8cc1Swenshuai.xi /// active format description found 174*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_EVENT_AFD_FOUND = VDEC_EX_V2_BIT(13), 175*53ee8cc1Swenshuai.xi // ES data invalid 176*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_EVENT_ES_DATA_ERR = VDEC_EX_V2_BIT(14), 177*53ee8cc1Swenshuai.xi 178*53ee8cc1Swenshuai.xi } VDEC_EX_V2_EventFlag; 179*53ee8cc1Swenshuai.xi 180*53ee8cc1Swenshuai.xi //define VDEC CB type 181*53ee8cc1Swenshuai.xi typedef enum 182*53ee8cc1Swenshuai.xi { 183*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CB_MAIN = 0, 184*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CB_SUB, 185*53ee8cc1Swenshuai.xi } VDEC_EX_V2_CB_TYPE; 186*53ee8cc1Swenshuai.xi 187*53ee8cc1Swenshuai.xi /// codec type enumerator 188*53ee8cc1Swenshuai.xi typedef enum 189*53ee8cc1Swenshuai.xi { 190*53ee8cc1Swenshuai.xi ///unsupported codec type 191*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CODEC_TYPE_NONE = 0, 192*53ee8cc1Swenshuai.xi ///MPEG 1/2 193*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CODEC_TYPE_MPEG2, 194*53ee8cc1Swenshuai.xi ///H263 (short video header) 195*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CODEC_TYPE_H263, 196*53ee8cc1Swenshuai.xi ///MPEG4 (default) 197*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CODEC_TYPE_MPEG4, 198*53ee8cc1Swenshuai.xi ///MPEG4 (Divx311) 199*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CODEC_TYPE_DIVX311, 200*53ee8cc1Swenshuai.xi ///MPEG4 (Divx412) 201*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CODEC_TYPE_DIVX412, 202*53ee8cc1Swenshuai.xi ///FLV 203*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CODEC_TYPE_FLV, 204*53ee8cc1Swenshuai.xi ///VC1 advanced profile (VC1) 205*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CODEC_TYPE_VC1_ADV, 206*53ee8cc1Swenshuai.xi ///VC1 main profile (RCV) 207*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CODEC_TYPE_VC1_MAIN, 208*53ee8cc1Swenshuai.xi ///Real Video version 8 209*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CODEC_TYPE_RV8, 210*53ee8cc1Swenshuai.xi ///Real Video version 9 and 10 211*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CODEC_TYPE_RV9, 212*53ee8cc1Swenshuai.xi ///H264 213*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CODEC_TYPE_H264, 214*53ee8cc1Swenshuai.xi ///AVS 215*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CODEC_TYPE_AVS, 216*53ee8cc1Swenshuai.xi ///MJPEG 217*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CODEC_TYPE_MJPEG, 218*53ee8cc1Swenshuai.xi ///MVC 219*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CODEC_TYPE_MVC, 220*53ee8cc1Swenshuai.xi ///VP8 221*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CODEC_TYPE_VP8, 222*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CODEC_TYPE_NUM 223*53ee8cc1Swenshuai.xi } VDEC_EX_V2_CodecType; 224*53ee8cc1Swenshuai.xi 225*53ee8cc1Swenshuai.xi /// input source select enumerator 226*53ee8cc1Swenshuai.xi typedef enum 227*53ee8cc1Swenshuai.xi { 228*53ee8cc1Swenshuai.xi ///DTV mode 229*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_SRC_MODE_DTV = 0, 230*53ee8cc1Swenshuai.xi ///TS file mode 231*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_SRC_MODE_TS_FILE, 232*53ee8cc1Swenshuai.xi ///generic file mode 233*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_SRC_MODE_FILE, 234*53ee8cc1Swenshuai.xi /// TS file and dual ES buffer mode 235*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_SRC_MODE_TS_FILE_DUAL_ES, 236*53ee8cc1Swenshuai.xi ///generic file and dual ES buffer mode 237*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_SRC_MODE_FILE_DUAL_ES, 238*53ee8cc1Swenshuai.xi } VDEC_EX_V2_SrcMode; 239*53ee8cc1Swenshuai.xi 240*53ee8cc1Swenshuai.xi /// function return enumerator 241*53ee8cc1Swenshuai.xi typedef enum 242*53ee8cc1Swenshuai.xi { 243*53ee8cc1Swenshuai.xi ///failed 244*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_FAIL = 0, 245*53ee8cc1Swenshuai.xi ///success 246*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_OK, 247*53ee8cc1Swenshuai.xi ///invalid parameter 248*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_RET_INVALID_PARAM, 249*53ee8cc1Swenshuai.xi ///access not allow 250*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_RET_ILLEGAL_ACCESS, 251*53ee8cc1Swenshuai.xi ///hardware abnormal 252*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_RET_HARDWARE_BREAKDOWN, 253*53ee8cc1Swenshuai.xi ///unsupported 254*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_RET_UNSUPPORTED, 255*53ee8cc1Swenshuai.xi ///timeout 256*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_RET_TIMEOUT, 257*53ee8cc1Swenshuai.xi ///not ready 258*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_RET_NOT_READY, 259*53ee8cc1Swenshuai.xi ///not initial 260*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_RET_NOT_INIT, 261*53ee8cc1Swenshuai.xi ///not exit after last initialization 262*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_RET_NOT_EXIT, 263*53ee8cc1Swenshuai.xi ///not running, counter does not change 264*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_RET_NOT_RUNNING, 265*53ee8cc1Swenshuai.xi ///max value 266*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_RET_NUM, 267*53ee8cc1Swenshuai.xi } VDEC_EX_V2_Result; 268*53ee8cc1Swenshuai.xi 269*53ee8cc1Swenshuai.xi /// Action enumerator of display commands 270*53ee8cc1Swenshuai.xi typedef enum 271*53ee8cc1Swenshuai.xi { 272*53ee8cc1Swenshuai.xi /// Action- display frame 273*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_DISP_ACTION_DISPLAY = 1, 274*53ee8cc1Swenshuai.xi /// Action - release frame 275*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_DISP_ACTION_RELEASE, 276*53ee8cc1Swenshuai.xi } VDEC_EX_V2_DispCmdAction; 277*53ee8cc1Swenshuai.xi 278*53ee8cc1Swenshuai.xi /// Freeze picture select after flush decoder 279*53ee8cc1Swenshuai.xi typedef enum 280*53ee8cc1Swenshuai.xi { 281*53ee8cc1Swenshuai.xi /// Freeze at current display picture 282*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_FREEZE_AT_CUR_PIC = 1, 283*53ee8cc1Swenshuai.xi /// freeze at the latest decode picture 284*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_FREEZE_AT_LAST_PIC, 285*53ee8cc1Swenshuai.xi } VDEC_EX_V2_FreezePicSelect; 286*53ee8cc1Swenshuai.xi 287*53ee8cc1Swenshuai.xi /// error code enumerator 288*53ee8cc1Swenshuai.xi typedef enum 289*53ee8cc1Swenshuai.xi { 290*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_ERR_CODE_BASE = 0x01000000, 291*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_ERR_CODE_NOT_SUPPORT, 292*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_ERR_CODE_ILLEGAL_ACCESS, 293*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_ERR_CODE_FRMRATE_NOT_SUPPORT, 294*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_ERR_CODE_DIVX_PLUS_UNSUPPORTED, 295*53ee8cc1Swenshuai.xi 296*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_MVD_ERR_CODE_BASE = 0x02000000, 297*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_MVD_ERR_CODE_SHAPE, 298*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_MVD_ERR_CODE_USED_SPRITE, 299*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_MVD_ERR_CODE_NOT_8_BIT, //error_status : bits per pixel 300*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_MVD_ERR_CODE_NERPRED_ENABLE, 301*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_MVD_ERR_CODE_REDUCED_RES_ENABLE, 302*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_MVD_ERR_CODE_SCALABILITY, 303*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_MVD_ERR_CODE_OTHER, 304*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_MVD_ERR_CODE_H263_ERROR, 305*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_MVD_ERR_CODE_RES_NOT_SUPPORT, //error_status : none 306*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_MVD_ERR_CODE_MPEG4_NOT_SUPPORT, //error_status : none 307*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_MVD_ERR_CODE_VC1_NOT_SUPPORT, //error_status : none 308*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_MVD_ERR_CODE_RCV_ERROR_OCCUR, 309*53ee8cc1Swenshuai.xi 310*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_HVD_ERR_CODE_BASE = 0x03000000, 311*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_HVD_ERR_CODE_GENERAL_BASE = (0x0000|E_VDEC_EX_HVD_ERR_CODE_BASE), 312*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_HVD_ERR_CODE_OUT_OF_SPEC , 313*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_HVD_ERR_CODE_UNKNOW_ERR, 314*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_HVD_ERR_CODE_HW_BREAK_DOWN, 315*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_HVD_ERR_CODE_HW_DEC_TIMEOUT, 316*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_HVD_ERR_CODE_OUT_OF_MEMORY, 317*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_HVD_ERR_CODE_UNKNOWN_CODEC, 318*53ee8cc1Swenshuai.xi // AVC 319*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_HVD_ERR_CODE_AVC_BASE = (0x1000|E_VDEC_EX_HVD_ERR_CODE_BASE), 320*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_HVD_ERR_CODE_AVC_SPS_BROKEN, 321*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_HVD_ERR_CODE_AVC_SPS_NOT_IN_SPEC, 322*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_HVD_ERR_CODE_AVC_SPS_NOT_ENOUGH_FRM, // DPB size at specified level is smaller than the specified number of reference frames. This is not allowed 323*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_HVD_ERR_CODE_AVC_PPS_BROKEN, // PPS is not valid 324*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_HVD_ERR_CODE_AVC_REF_LIST, 325*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_HVD_ERR_CODE_AVC_NO_REF, 326*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_HVD_ERR_CODE_AVC_RES, // out of supported resolution 327*53ee8cc1Swenshuai.xi // AVS 328*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_HVD_ERR_CODE_AVS_BASE = (0x2000|E_VDEC_EX_HVD_ERR_CODE_BASE), 329*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_HVD_ERR_CODE_AVS_RES, // out of supported resolution 330*53ee8cc1Swenshuai.xi // RM 331*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_HVD_ERR_CODE_RM_BASE = (0x3000|E_VDEC_EX_HVD_ERR_CODE_BASE), 332*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_HVD_ERR_CODE_RM_PACKET_HEADER, 333*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_HVD_ERR_CODE_RM_FRAME_HEADER, 334*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_HVD_ERR_CODE_RM_SLICE_HEADER, 335*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_HVD_ERR_CODE_RM_BYTE_CNT, 336*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_HVD_ERR_CODE_RM_DISP_TIMEOUT, 337*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_HVD_ERR_CODE_RM_NO_REF, 338*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_HVD_ERR_CODE_RM_RES, // out of supported resolution 339*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_HVD_ERR_CODE_RM_VLC, 340*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_HVD_ERR_CODE_RM_SIZE_OUT_FB_LAYOUT, 341*53ee8cc1Swenshuai.xi 342*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_RVD_ERR_CODE_BASE = 0x04000000, 343*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_RVD_ERR_CODE_PACKET_HEADER, ///< packet header version error 344*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_RVD_ERR_CODE_FRAME_HEADER, ///< frame type error 345*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_RVD_ERR_CODE_SLICE_HEADER, ///<slice header error 346*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_RVD_ERR_CODE_DECODE_TIMEOUT,///< decode MB timeout 347*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_RVD_ERR_CODE_OUT_OF_MEMORY, ///< frame buffer is out of memory 348*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_RVD_ERR_CODE_BYTE_POS, ///< can not find in ID table 349*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_RVD_ERR_CODE_DISPLAY_TIMEOUT, 350*53ee8cc1Swenshuai.xi 351*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_MJPEG_ERR_CODE_BASE = 0x05000000, 352*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_HVD_ERR_CODE_MJPEG_RES, 353*53ee8cc1Swenshuai.xi } VDEC_EX_V2_ErrCode; 354*53ee8cc1Swenshuai.xi 355*53ee8cc1Swenshuai.xi /// frame rate conversion mode enumerator 356*53ee8cc1Swenshuai.xi typedef enum 357*53ee8cc1Swenshuai.xi { 358*53ee8cc1Swenshuai.xi /// disable FRC mode. 359*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_FRC_NORMAL = 0, 360*53ee8cc1Swenshuai.xi /// output rate is twice of input rate (ex. 30p to 60p) 361*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_FRC_DISP_TWICE, 362*53ee8cc1Swenshuai.xi /// 3:2 pulldown mode (ex. 24p to 60i or 60p) 363*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_FRC_3_2_PULLDOWN, 364*53ee8cc1Swenshuai.xi /// PAL to NTSC conversion (50i to 60i) 365*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_FRC_PAL_TO_NTSC, 366*53ee8cc1Swenshuai.xi /// NTSC to PAL conversion (60i to 50i) 367*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_FRC_NTSC_TO_PAL, 368*53ee8cc1Swenshuai.xi /// output rate 50P ->60P 369*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_FRC_MODE_50P_60P, 370*53ee8cc1Swenshuai.xi /// output rate 60P ->50P 371*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_FRC_MODE_60P_50P, 372*53ee8cc1Swenshuai.xi } VDEC_EX_V2_FrcMode; 373*53ee8cc1Swenshuai.xi 374*53ee8cc1Swenshuai.xi /// trick decode mode enumerator 375*53ee8cc1Swenshuai.xi typedef enum 376*53ee8cc1Swenshuai.xi { 377*53ee8cc1Swenshuai.xi /// decode all frame 378*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_TRICK_DEC_ALL = 0, 379*53ee8cc1Swenshuai.xi /// decode all except of non-reference frame 380*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_TRICK_DEC_IP, 381*53ee8cc1Swenshuai.xi /// only decode I frame 382*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_TRICK_DEC_I, 383*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_TRICK_DEC_NUM 384*53ee8cc1Swenshuai.xi } VDEC_EX_V2_TrickDec; 385*53ee8cc1Swenshuai.xi 386*53ee8cc1Swenshuai.xi /// display speed setting enumerator 387*53ee8cc1Swenshuai.xi typedef enum 388*53ee8cc1Swenshuai.xi { 389*53ee8cc1Swenshuai.xi /// default speed type 390*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_SPEED_DEFAULT = 0, 391*53ee8cc1Swenshuai.xi /// fast display 392*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_SPEED_FAST, 393*53ee8cc1Swenshuai.xi /// slow display 394*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_SPEED_SLOW, 395*53ee8cc1Swenshuai.xi } VDEC_EX_V2_SpeedType; 396*53ee8cc1Swenshuai.xi 397*53ee8cc1Swenshuai.xi /// The display speed enumerator 398*53ee8cc1Swenshuai.xi typedef enum 399*53ee8cc1Swenshuai.xi { 400*53ee8cc1Swenshuai.xi /// Normal display speed. 401*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_DISP_SPEED_1X = 1, 402*53ee8cc1Swenshuai.xi /// 2X 403*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_DISP_SPEED_2X = 2, 404*53ee8cc1Swenshuai.xi /// 4X 405*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_DISP_SPEED_4X = 4, 406*53ee8cc1Swenshuai.xi /// 8X 407*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_DISP_SPEED_8X = 8, 408*53ee8cc1Swenshuai.xi /// 16X 409*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_DISP_SPEED_16X = 16, 410*53ee8cc1Swenshuai.xi /// 32X 411*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_DISP_SPEED_32X = 32, 412*53ee8cc1Swenshuai.xi } VDEC_EX_V2_DispSpeed; 413*53ee8cc1Swenshuai.xi 414*53ee8cc1Swenshuai.xi /// motion JPEG down scale factor enumerator 415*53ee8cc1Swenshuai.xi typedef enum 416*53ee8cc1Swenshuai.xi { 417*53ee8cc1Swenshuai.xi ///original size 418*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_MJPEG_SCALE_1to1 = 0, 419*53ee8cc1Swenshuai.xi ///down scale to 1/2 420*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_MJPEG_SCALE_2to1, 421*53ee8cc1Swenshuai.xi ///down scale to 1/4 422*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_MJPEG_SCALE_4to1, 423*53ee8cc1Swenshuai.xi ///down scale to 1/8 424*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_MJPEG_SCALE_8to1, 425*53ee8cc1Swenshuai.xi } VDEC_EX_V2_MJpegScaleFactor; 426*53ee8cc1Swenshuai.xi 427*53ee8cc1Swenshuai.xi /// timestamp type of command queue 428*53ee8cc1Swenshuai.xi typedef enum 429*53ee8cc1Swenshuai.xi { 430*53ee8cc1Swenshuai.xi ///without timestamp information 431*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_TIME_STAMP_NONE = 0, 432*53ee8cc1Swenshuai.xi ///PTS (Presentation Time Stamp) 433*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_TIME_STAMP_PTS, 434*53ee8cc1Swenshuai.xi ///DTS (Decode Time Stamp) 435*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_TIME_STAMP_DTS, 436*53ee8cc1Swenshuai.xi ///STS (Sorted Time Stamp) 437*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_TIME_STAMP_STS, 438*53ee8cc1Swenshuai.xi } VDEC_EX_V2_TimeStampType; 439*53ee8cc1Swenshuai.xi 440*53ee8cc1Swenshuai.xi /// The debug level of VDEC 441*53ee8cc1Swenshuai.xi typedef enum 442*53ee8cc1Swenshuai.xi { 443*53ee8cc1Swenshuai.xi /// disable all uart message. 444*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_DBG_LEVEL_NONE = 0, 445*53ee8cc1Swenshuai.xi /// Only output error message 446*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_DBG_LEVEL_ERR, 447*53ee8cc1Swenshuai.xi /// output general message, and above. 448*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_DBG_LEVEL_INFO, 449*53ee8cc1Swenshuai.xi /// output debug message, and above. 450*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_DBG_LEVEL_DBG, 451*53ee8cc1Swenshuai.xi /// output function tracing message, and above. 452*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_DBG_LEVEL_TRACE, 453*53ee8cc1Swenshuai.xi /// output FW message. 454*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_DBG_LEVEL_FW, 455*53ee8cc1Swenshuai.xi } VDEC_EX_V2_DbgLevel; 456*53ee8cc1Swenshuai.xi 457*53ee8cc1Swenshuai.xi /// Type of FW source 458*53ee8cc1Swenshuai.xi typedef enum 459*53ee8cc1Swenshuai.xi { 460*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_FW_SOURCE_NONE, 461*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_FW_SOURCE_DRAM, 462*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_FW_SOURCE_FLASH, 463*53ee8cc1Swenshuai.xi }VDEC_EX_V2_FWSourceType; 464*53ee8cc1Swenshuai.xi 465*53ee8cc1Swenshuai.xi /// Format of CC (Closed Caption) 466*53ee8cc1Swenshuai.xi typedef enum 467*53ee8cc1Swenshuai.xi { 468*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CC_NONE = 0x00, 469*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CC_608 = 0x01, //For CC608 or 157 470*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CC_708 = 0x02, //For CC708 471*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CC_UNPACKED = 0x03, 472*53ee8cc1Swenshuai.xi } VDEC_EX_V2_CCFormat; 473*53ee8cc1Swenshuai.xi 474*53ee8cc1Swenshuai.xi /// Type of CC 475*53ee8cc1Swenshuai.xi typedef enum 476*53ee8cc1Swenshuai.xi { 477*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CC_TYPE_NONE = 0, 478*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CC_TYPE_NTSC_FIELD1 = 1, 479*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CC_TYPE_NTSC_FIELD2 = 2, 480*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CC_TYPE_DTVCC = 3, 481*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CC_TYPE_NTSC_TWOFIELD = 4, 482*53ee8cc1Swenshuai.xi } VDEC_EX_V2_CCType; 483*53ee8cc1Swenshuai.xi 484*53ee8cc1Swenshuai.xi typedef enum 485*53ee8cc1Swenshuai.xi { 486*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CC_GET_BUFF_START = 0x1, 487*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CC_GET_BUFF_SIZE, 488*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CC_GET_708_ENABLE 489*53ee8cc1Swenshuai.xi } VDEC_EX_V2_CCInfoCmd; 490*53ee8cc1Swenshuai.xi 491*53ee8cc1Swenshuai.xi typedef enum 492*53ee8cc1Swenshuai.xi { 493*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_STAGE_STOP = 0, 494*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_STAGE_INIT, 495*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_STAGE_PLAY, 496*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_STAGE_PAUSE, 497*53ee8cc1Swenshuai.xi } VDEC_EX_V2_Stage; 498*53ee8cc1Swenshuai.xi 499*53ee8cc1Swenshuai.xi typedef enum 500*53ee8cc1Swenshuai.xi { 501*53ee8cc1Swenshuai.xi /// Used before MApi_VDEC_EX_Flush(). 502*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_PATTERN_FLUSH = 0, 503*53ee8cc1Swenshuai.xi /// Used after MApi_VDEC_EX_EnableLastFrameShow(). 504*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_PATTERN_FILEEND, 505*53ee8cc1Swenshuai.xi }VDEC_EX_V2_PatternType; 506*53ee8cc1Swenshuai.xi 507*53ee8cc1Swenshuai.xi typedef struct 508*53ee8cc1Swenshuai.xi { 509*53ee8cc1Swenshuai.xi MS_BOOL bInit; 510*53ee8cc1Swenshuai.xi MS_BOOL bIdle; 511*53ee8cc1Swenshuai.xi VDEC_EX_V2_Stage eStage; 512*53ee8cc1Swenshuai.xi } VDEC_EX_V2_Status; 513*53ee8cc1Swenshuai.xi 514*53ee8cc1Swenshuai.xi typedef struct 515*53ee8cc1Swenshuai.xi { 516*53ee8cc1Swenshuai.xi MS_U32 u32Tmp; 517*53ee8cc1Swenshuai.xi } VDEC_EX_V2_Info; 518*53ee8cc1Swenshuai.xi 519*53ee8cc1Swenshuai.xi typedef enum 520*53ee8cc1Swenshuai.xi { 521*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_FRM_TYPE_I = 0, 522*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_FRM_TYPE_P, 523*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_FRM_TYPE_B, 524*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_FRM_TYPE_OTHER, 525*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_FRM_TYPE_NUM 526*53ee8cc1Swenshuai.xi } VDEC_EX_V2_FrameType; 527*53ee8cc1Swenshuai.xi 528*53ee8cc1Swenshuai.xi typedef enum 529*53ee8cc1Swenshuai.xi { 530*53ee8cc1Swenshuai.xi ///< no field. 531*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_FIELDTYPE_NONE, 532*53ee8cc1Swenshuai.xi ///< Top field only. 533*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_FIELDTYPE_TOP, 534*53ee8cc1Swenshuai.xi ///< Bottom field only. 535*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_FIELDTYPE_BOTTOM, 536*53ee8cc1Swenshuai.xi ///< Both fields. 537*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_FIELDTYPE_BOTH, 538*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_FIELDTYPE_NUM 539*53ee8cc1Swenshuai.xi } VDEC_EX_V2_FieldType; 540*53ee8cc1Swenshuai.xi 541*53ee8cc1Swenshuai.xi typedef enum 542*53ee8cc1Swenshuai.xi { 543*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_PATTERN_BEFORE_FRM = 0, 544*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_PATTERN_AFTER_FRM, 545*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_PATTERN_SKIP_DATA, 546*53ee8cc1Swenshuai.xi } VDEC_EX_V2_PatchPattern; 547*53ee8cc1Swenshuai.xi 548*53ee8cc1Swenshuai.xi typedef enum 549*53ee8cc1Swenshuai.xi { 550*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_PIC_STRUCTURE_RSV = 0, //reserved 551*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_PIC_STRUCTURE_TOP, 552*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_PIC_STRUCTURE_BOT, 553*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_PIC_STRCUTURE_FRM, 554*53ee8cc1Swenshuai.xi } VDEC_EX_V2_PicStructure; 555*53ee8cc1Swenshuai.xi 556*53ee8cc1Swenshuai.xi //VDEC FB reduction type 557*53ee8cc1Swenshuai.xi typedef enum 558*53ee8cc1Swenshuai.xi { 559*53ee8cc1Swenshuai.xi VDEC_EX_V2_FB_REDUCTION_NONE = 0, 560*53ee8cc1Swenshuai.xi VDEC_EX_V2_FB_REDUCTION_1_2, 561*53ee8cc1Swenshuai.xi VDEC_EX_V2_FB_REDUCTION_1_4 562*53ee8cc1Swenshuai.xi } VDEC_EX_V2_FBReductionType; 563*53ee8cc1Swenshuai.xi 564*53ee8cc1Swenshuai.xi //VDEC set debug mode 565*53ee8cc1Swenshuai.xi typedef enum 566*53ee8cc1Swenshuai.xi { 567*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_DBG_MODE_BYPASS_INSERT_START_CODE = 0, /// for UT 568*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_DBG_MODE_BYPASS_DIVX_MC_PATCH, /// for UT 569*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_DBG_MODE_NUM 570*53ee8cc1Swenshuai.xi } VDEC_EX_V2_DbgMode; 571*53ee8cc1Swenshuai.xi 572*53ee8cc1Swenshuai.xi //VDEC set clock speed 573*53ee8cc1Swenshuai.xi typedef enum 574*53ee8cc1Swenshuai.xi { 575*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CLOCK_SPEED_NONE = 0, 576*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CLOCK_SPEED_HIGHEST, 577*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CLOCK_SPEED_HIGH, 578*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CLOCK_SPEED_MEDIUM, 579*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CLOCK_SPEED_LOW, 580*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CLOCK_SPEED_LOWEST, 581*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CLOCK_SPEED_DEFAULT, 582*53ee8cc1Swenshuai.xi } VDEC_EX_V2_ClockSpeed; 583*53ee8cc1Swenshuai.xi 584*53ee8cc1Swenshuai.xi //VDEC FW TYPE 585*53ee8cc1Swenshuai.xi typedef enum 586*53ee8cc1Swenshuai.xi { 587*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_FW_TYPE_MVD = 0, 588*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_FW_TYPE_HVD, 589*53ee8cc1Swenshuai.xi } VDEC_EX_V2_FwType; 590*53ee8cc1Swenshuai.xi 591*53ee8cc1Swenshuai.xi /// DecodeMode for f/w tasks 592*53ee8cc1Swenshuai.xi typedef enum 593*53ee8cc1Swenshuai.xi { 594*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_DEC_MODE_DUAL_INDIE = 0, ///< Two independent tasks 595*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_DEC_MODE_DUAL_3D, ///< Two dependent tasks for 3D 596*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_DEC_MODE_SINGLE, ///< One task use the whole SRAM 597*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_DEC_MODE_MVC = E_VDEC_EX_DEC_MODE_SINGLE, 598*53ee8cc1Swenshuai.xi } VDEC_EX_V2_DEC_MODE; 599*53ee8cc1Swenshuai.xi 600*53ee8cc1Swenshuai.xi 601*53ee8cc1Swenshuai.xi /// argument of DecodeMode structure for f/w tasks 602*53ee8cc1Swenshuai.xi typedef enum 603*53ee8cc1Swenshuai.xi { 604*53ee8cc1Swenshuai.xi //Group1:Set Korea3DTV mode 605*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_DEC_KR3D_MODE_BASE = 0x0000, 606*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_DEC_KR3D_INTERLACE_MODE = E_VDEC_EX_DEC_KR3D_MODE_BASE, 607*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_DEC_KR3D_FORCE_P_MODE, 608*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_DEC_KR3D_INTERLACE_TWO_PITCH, 609*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_DEC_KR3D_FORCE_P_TWO_PITCH, 610*53ee8cc1Swenshuai.xi 611*53ee8cc1Swenshuai.xi //Group2:Set PIP mode 612*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_DEC_PIP_MODE_BASE = 0x1000, 613*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_DEC_PIP_SYNC_INDIE = E_VDEC_EX_DEC_PIP_MODE_BASE, 614*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_DEC_PIP_SYNC_MAIN_STC, 615*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_DEC_PIP_SYNC_SWITCH 616*53ee8cc1Swenshuai.xi } VDEC_EX_V2_DEC_MODE_ARG; 617*53ee8cc1Swenshuai.xi 618*53ee8cc1Swenshuai.xi typedef enum 619*53ee8cc1Swenshuai.xi { 620*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_DIU_DRAM = 0, //MCU mode 621*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_DIU_HVD = 1, 622*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_DIU_MVD = 2, 623*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_DIU_HVD_3DLR = 3, //MVC 624*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_DIU_MVD_3DLR = 4, //Korea3D, WMV3D 625*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_DIU_UNKNOWN = -1 626*53ee8cc1Swenshuai.xi } VDEC_EX_V2_DIU; 627*53ee8cc1Swenshuai.xi 628*53ee8cc1Swenshuai.xi typedef enum 629*53ee8cc1Swenshuai.xi { 630*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CMD_GET_FREE_STREAM_ID, 631*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CMD_INIT, 632*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CMD_SET_CONTROL, 633*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CMD_GET_CONTROL, 634*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CMD_PRE_SET_CONTROL, 635*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CMD_POST_SET_CONTROL, 636*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CMD_NUM, 637*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_CMD_MAX = E_VDEC_EX_V2_CMD_NUM, 638*53ee8cc1Swenshuai.xi } E_VDEC_EX_V2_IOCTL_CMD; 639*53ee8cc1Swenshuai.xi 640*53ee8cc1Swenshuai.xi //VDEC user command id 641*53ee8cc1Swenshuai.xi typedef enum 642*53ee8cc1Swenshuai.xi { 643*53ee8cc1Swenshuai.xi //Group1:Set Control command================================ 644*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SET_CONTROL_BASE = 0x0000, 645*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_REPEAT_LAST_FIELD, // Param: 1(ON), 0(OFF) 646*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_AVSYNC_REPEAT_TH, // Param:0x01 ~ 0xFF(repeat times), 0xFF:always repeat when av is not sync 647*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_DISP_ONE_FIELD, // Param: 1(ON), 0(OFF) 648*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_FD_MASK_DELAY_COUNT, // Param: unit is in vsync base for mute the fd_mask 649*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_FRC_OUTPUT, // Param: the address of VDEC_FRC_OutputParam 650*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_FRC_DROP_TYPE, // Param: 1(FRC_DROP_FIELD), 0(FRC_DROP_FRAME), default:0 651*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_FAST_DISPLAY, // Param: TRUE(Fast display), FALSE(Display until synced) 652*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_IGNORE_ERR_REF, // Param: TRUE(Ignore error reference), FALSE(Enable error reference handle) 653*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_FORCE_FOLLOW_DTV_SPEC, // Param: 1(ON), 0(OFF) 654*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_AVC_MIN_FRM_GAP, // Param: Set the theshold of H264 frame gap, 0xFFFFFFFF don't care frame gap 655*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_DISABLE_SEQ_CHG, // Param: 1(Disable), 0(Enable) 656*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SET_DISP_OUTSIDE_CTRL_MODE, // Param: 1(ON) used for Openmax, 0(OFF) used for mstreamer and mm mode ,default : off 657*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SET_DTV_USER_DATA_MODE, // Param: 0(Support normal DVB CC, default case), 1(Support ATSC DirectTV CC), 2,3,4(Reserved) 658*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SET_SINGLE_TASK_MODE, 659*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_AVC_DISABLE_ANTI_VDEAD, 660*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_DTV_RESET_MVD_PARSER, // Param: 0(Disable), 1(Enable) 661*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_PVR_FLUSH_FRAME_BUFFER, 662*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_FORCE_INTERLACE_MODE, 663*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_RELEASE_FD_MASK, // Param: 1 to release fd mask when zooming or slow motion 664*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_NULL, // E_VDEC_EX_USER_CMD_SET_DECODE_MODE 665*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SUPPORT_AVC_TO_MVC, // Param: 0(Do not support), 1(Support AVC to MVC) 666*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_3DLR_VIEW_EXCHANGE, // Param: 0(Disable), 1(View L/R exhange) 667*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SET_VSIZE_ALIGN, // Param: 0(Disable), 1(Enable) 668*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SHOW_DECODE_ORDER, // Param: 0(Disable), 1(Enable) 669*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_AVC_DISP_IGNORE_CROP, // Param: 0(Disable), 1(Enable) 670*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SET_DISP_FINISH_MODE, 671*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SET_AVSYNC_MODE, 672*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SUSPEND_DYNAMIC_SCALE, // Param: 0(Disable, non-suspend DS), 1(Enable, suspend DS) 673*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_FORCE_AUTO_MUTE, 674*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_AVC_NEW_SLOW_MOTION, // Param: 0(Disable), 1(Enable) 675*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_PUSH_DISPQ_WITH_REF_NUM, // Param: 0(Disable), 1(Enable) 676*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_DS_RESV_N_BUFFER, // Param: 0(Disable), 1(Enable) 677*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_RM_ENABLE_PTS_TBL, // Param: 0(Disable), 1(Enable) 678*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_FLUSH_PTS_BUF, 679*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SET_IDCT_MODE, // Param: 0(Original), 1(new IDCT) 680*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_DROP_ERR_FRAME, // Param: 0(Disable), 1(Enable) 681*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SET_CC608_INFO_ENHANCE_MODE, 682*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_IGNORE_PIC_OVERRUN, // Param: 0(Disable), 1(Enable) 683*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SET_SELF_SEQCHANGE, 684*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_AUTO_EXHAUST_ES_MODE, // Param: set the upper bound (arg[31:16]), and lower bound (arg[15:0])of ES level, Unit = 1KBytes, Auto drop display to consume ES data as soon as possible when ES level is higher than upper bound 685*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_CTL_SPEED_IN_DISP_ONLY, // Param: 0(Original: Dec and disp time), 1(In Disp only) 686*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_AVC_SUPPORT_REF_NUM_OVER_MAX_DPB_SIZE, // Param: 0(Disable), 1(Enable) 687*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_RETURN_INVALID_AFD, // Param: 0(Disable), 1(Enable) 688*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_FIELD_POLARITY_DISPLAY_ONE_FIELD,// Param : VDEC_EX_V2_Field_Polarity 689*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_AVC_FORCE_BROKEN_BY_US, // Param: 0(Disable), 1(Enable) 690*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SHOW_FIRST_FRAME_DIRECT, // Param: 0(Disable), 1(Enable), Push first frame to display queue directly.. 691*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_AVC_RESIZE_DOS_DISP_PEND_BUF, // Param: size of AVC display pending buffer for display outside mode 692*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SET_XC_LOW_DELAY_PARA, // Param: arg0 for diff_field_number... 693*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SET_SECURE_MODE, // Param: use enum VDEC_EX_SecureMode 694*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_RVU_SETTING_MODE, // Param: 0(Disable), 1(drop B-frame and force IDR) 695*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_FRAMERATE_HANDLING, // Arg 0~60000, 0: Disable, 1000 ~ 60000: Used the arg to set frame rate when the sequence did not have frame rate info. and arg is not zero. (The frame unit is (arg/1000)fps, Exp: 30000 = 30.000 fps), others: Do not thing. 696*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_DUAL_NON_BLOCK_MODE, // Param: 0(Disable), 1(Enable) 697*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_IGNORE_PIC_STRUCT_DISPLAY, // Param: 0(Disable), 1(Enable) Ignore Pic_struct when display progressive frame. 698*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_INPUT_PTS_FREERUN_MODE, // Param: 0(Disable), 1(Enable) Video free run when the difference between input PTS and current STC is large than E_HVD_CMD_FREERUN_THRESHOLD + 1s; 699*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_ERR_CONCEAL_SLICE_1ST_MB, // Param: 0(disable), Error concealment from current/last MB position; 1(enale) Error concealment from current slice first MB.(Need enable E_HVD_CMD_ERR_CONCEAL) 700*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SET_EXTERNAL_DS_BUFFER, // Param: External DS Buffer info. 701*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SET_MIN_TSP_DATA_SIZE, // Param: Resize HVD_FW_AVC_ES_MIN_TSP_DATA_SIZE 702*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SET_DMX_FRAMERATE, 703*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SET_DMX_FRAMERATEBASE, 704*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_ENABLE_CC_608_EXTERNAL_BUFFER, // Param: u32_ccinfo 32bits-->([31:8]+[7:0] = addr+size), addr is kb unit, if u32_ccinfo ==0, it will turn off this feature 705*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_ENABLE_CC_708_EXTERNAL_BUFFER, // Param: u32_ccinfo 32bits-->([31:8]+[7:0] = addr+size), addr is kb unit, if u32_ccinfo ==0, it will turn off this feature 706*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SET_TIME_INC_PREDICT_PARA, 707*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_ENABLE_DECODE_ENGINE_TIMEOUT, // Param: Enable/Disable decode timeout solution, timeout value unit:ms (VDEC_EX_Decode_Timeout_Param) 708*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_AUTO_FREE_ES, // Param: 0(Disable), 1(Enable) 709*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_FRAMEBUFFER_AUTO_MODE, //Param: 0(Disable),1(Enable), this cmd is used for MVD. 710*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SET_SMOOTH_REWIND, //enable/disable or support smooth rewind 711*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SET_ERROR_TOLERANCE, // Param: VDEC_EX_Err_Tolerance; bEnable: enable or disable; u8Tolerance: err_rate(0%~100%) 712*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_AUTO_DROP_DISPLAY_QUEUE, // Param: 0(Disable), N = 1~16: Drop display queue when display queue above than N frames. 713*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_USE_CPB_REMOVAL_DEALY, // Param: 0(Disable), 1(Enable) 714*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SKIP_N_FRAME, // Param: 0:disable, N = 1~63. Skip N frame. 715*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SET_PTS_US_MODE, //Param: 1(enable), 0(disable ) PTS output by micro second level, 716*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_AUTO_INSERT_DUMMY_DATA, //Param: 1(enable),0(disable), Enable/Disable utopia auto insert dummy pattern in SLQ/BBU mode. 717*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_DROP_ONE_PTS, 718*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_PVR_TIMESHIFT_SEAMLESS_MODE, 719*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_AUTO_REDUCE_ES_DATA, 720*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_RM_FORCE_MCU_MODE_ES, // Param: 0(Disable), 1(Enable) 721*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_FORCE_PROGRESSIVE_MODE, // Param: 1(enable),0(disable), Enable/Disable force progressive mode 722*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SET_FRAMEBUFF2, // Param[0]=Addr and Param[1]=size for the second frame buffer 723*53ee8cc1Swenshuai.xi 724*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_EXIT, 725*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_RST, 726*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_CHECK_DISPINFO_READY, 727*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SET_FRC_MODE, 728*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SET_DYNSCALING_PARAMS, 729*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SET_DBG_LEVEL, 730*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_PLAY, 731*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_PAUSE, 732*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_RESUME, 733*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_STEP_DISP, 734*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_STEP_DECODE, 735*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SET_TRICK_MODE, 736*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_PUSH_DECQ, 737*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_FLUSH, 738*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_ENABLE_LAST_FRAME_SHOW, 739*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SET_SPEED, 740*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SET_FREEZE_DISP, 741*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SET_BLUE_SCREEN, 742*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_RESET_PTS, 743*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_AVSYNC_ON, 744*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_AVSYNC_FREERUN_THRESHOLD, 745*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SET_EVENT_MULTICALLBACK, 746*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_UNSET_EVENT_MULTICALLBACK, 747*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_FIRE_DEC, 748*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SEEK_TO_PTS, 749*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SKIP_TO_PTS, 750*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_DISABLE_DEBLOCKING, 751*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_DISABLE_QUARTER_PIXEL, 752*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SET_AUTO_RM_LST_ZERO_BYTE, 753*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SET_BALANCE_BW, 754*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GEN_PATTERN, 755*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_MHEG_DECODE_IFRAME, 756*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_MHEG_RST_IFRAME_DEC, 757*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_CC_START_PARSING, 758*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_CC_STOP_PARSING, 759*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_CC_UPDATE_READ_PTR, 760*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SET_BLOCK_DISPLAY, 761*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_ENABLE_ES_BUFF_MALLOC, 762*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_DISPLAY_FRAME, 763*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_RELEASE_FRAME, 764*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_CAPTURE_FRAME, 765*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_CC_INIT, 766*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_CC_SET_CFG, 767*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_CC_SET_BUFF_START_ADDR, 768*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_CC_UPDATE_WRITE_ADDR, 769*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_CC_UPDATE_READ_ADDR, 770*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_CC_DISABLE_PARSING, 771*53ee8cc1Swenshuai.xi 772*53ee8cc1Swenshuai.xi 773*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_MVC_SET_CMD_BASE = 0x0800, 774*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_MVC_BBU2_PUSH_PACKET, // Param: Packet Info. 775*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_MVC_BBU2_FIRE_DECCMD, // Param: Non 776*53ee8cc1Swenshuai.xi 777*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_UT_SET_CMD_BASE = 0x0900, 778*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_UT_SET_DBG_MODE, // Param: for enable the specify dbg mode for UT 779*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_UT_CLR_DBG_MODE, // Param: for disable the specify dbg mode for UT 780*53ee8cc1Swenshuai.xi 781*53ee8cc1Swenshuai.xi //Group2:Get Control command================================ 782*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_CONTROL_BASE = 0x1000, 783*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_CHROMA_TYPE, 784*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_REAL_FRAMERATE, // Get Real FrameRate reported by decoder 785*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_COLOR_MATRIX, // Get color matrix coefficients reported by decoder 786*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_MAIN_STREAM_ID, // Get activated main stream ID 787*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_SUB_STREAM_ID, // Get activated sub stream ID 788*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_DYNSCALE_ENABLED, 789*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_FPA_SEI, //Get SEI info 790*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_U64PTS, 791*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_ORI_INTERLACE_MODE, 792*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_MBS_ONLY_FLAG, 793*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_CRC_VALUE, //Get frame Y/UV crc value 794*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_BBU_Q_NUM, 795*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_DISP_FRAME_NUM, 796*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_FPA_SEI_EX, //Get SEI info(enhancement) 797*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_ES_BUFFER_STATUS, //Get ES buffer over/under flow status 798*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_CODEC_TYPE, // Get Codec type 799*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_SHAREMEMORY_BASE, 800*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_IS_LEAST_DISPQ_SIZE_FLAG, 801*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_FIELD_PIC_FLAG, // Param: Get Field Pic Flag 802*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_SUPPORT_2ND_MVOP_INTERFACE, // Param: TRUE : support, FALSE : not support 803*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_FB_USAGE_MEM, // Get FrameBuufer Size needed by decoder 804*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_XC_LOW_DELAY_INT_STATE, // Get xc_low_delay int state... 805*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_VSYNC_BRIDGE_ADDR, 806*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_FRAME_INFO_EX, 807*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_FLUSH_PATTEN_ENTRY_NUM, 808*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_DS_BUF_MIU_SEL, //For those chips which has 3 MIU, use this get control to get correct miu select of DS buffer 809*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_FW_STATUS_FLAG, 810*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_HW_MAX_PIXEL, 811*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_FLOW_CONTROL_U64PTS_DIFF, // based on PTS table Rdptr and Wrptr, support TSP mode only 812*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_NEXT_DISP_FRAME_INFO_EXT, //replace of E_VDEC_EX_USER_CMD_GET_FRAME_INFO_EX 813*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_VSYNC_BRIDGE_EXT_ADDR, //get vsync bridge ext addr 814*53ee8cc1Swenshuai.xi 815*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_STATUS, 816*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_CHECK_DISPINFORDY, 817*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_IS_STEP_DISP_DONE, 818*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_IS_STEP_DECODE_DONE, 819*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_DISP_INFO, 820*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_IS_AVSYNC_ON, 821*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_IS_WITH_VALID_STREAM, 822*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_IS_DISP_FINISH, 823*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_IS_IFRAME_FOUND, 824*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_IS_SEQ_CHG, 825*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_IS_REACH_SYNC, 826*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_IS_START_SYNC, 827*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_IS_FREERUN, 828*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_IS_WITH_LOW_DELAY, 829*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_IS_ALL_BUFFER_EMPTY, 830*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_EXT_DISP_INFO, 831*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_DEC_FRAME_INFO, 832*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_DISP_FRAME_INFO, 833*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_DEC_TIMECODE, 834*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_DISP_TIMECODE, 835*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_EVENT_INFO, 836*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_ACTIVE_FORMAT, 837*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_COLOUR_PRIMARIES, 838*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_FW_VERSION, 839*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_GOP_CNT, 840*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_ES_WRITE_PTR, 841*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_ES_READ_PTR, 842*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_PTS, 843*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_NEXT_PTS, 844*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_VIDEO_PTS_STC_DELTA, 845*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_ERR_CODE, 846*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_ERR_CNT, 847*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_BITRATE, 848*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_FRAME_CNT, 849*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_SKIP_CNT, 850*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_DROP_CNT, 851*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_DISP_CNT, 852*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_DECQ_VACANCY, 853*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_IS_32_PULLDOWN, 854*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_IS_ALIVE, 855*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_IS_CC_AVAILABLE, 856*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_CC_INFO, 857*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_TRICK_MODE, 858*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_ACTIVE_CODEC_TYPE, 859*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_PATTERN_LEAST_LENGTH, 860*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_MHEG_IS_IFRAME_DECODING, 861*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_CC_GET_WRITE_PTR, 862*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_CC_GET_READ_PTR, 863*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_CC_GET_IS_OVERFLOW, 864*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_HW_KEY, 865*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_ES_BUFF_VACANCY, 866*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_ES_BUFF, 867*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_NEXT_DISP_FRAME, 868*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_CC_GET_INFO, 869*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_CC_GET_IS_RST_DONE, 870*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_CC_GET_IS_BUFF_OVERFLOW, 871*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_CC_GET_WRITE_ADDR, 872*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_CC_GET_READ_ADDR, 873*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GETLIBVER, 874*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GETINFO, 875*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_CHECKCAPS, 876*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_IS_FRAME_RDY, 877*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_DCV_SEI, 878*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_VUI_DISP_INFO, 879*53ee8cc1Swenshuai.xi 880*53ee8cc1Swenshuai.xi 881*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_MVC_GET_CMD_BASE = 0x1800, 882*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_MVC_SUB_FRAME_DISP_INFO, // Param: VDEC_FrameInfo pointer. 883*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_MVC_BBU2_DECQ_VACANCY, // Param: BBU2 Dec Q Vacancy. 884*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_MVC_ES2_READ_PTR, // Param: ES2 read pointer. 885*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_MVC_ES2_WRITE_PTR, // Param: ES2 Write pointer. 886*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_ES_QUANTITY, // Param: Get ES buffer Level. 887*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_GET_ES2_QUANTITY, // Param: Get ES2 buffer Level. 888*53ee8cc1Swenshuai.xi 889*53ee8cc1Swenshuai.xi //Group3:Preset Control command====================== 890*53ee8cc1Swenshuai.xi //Group3-1:Common system Preset Control command 891*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SYSTEM_PRESET_CONTROL_BASE = 0x2000, 892*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SYSTEM_PRESET_VPU_CLOCK, //Param: VDEC_EX_ClockSpeed 893*53ee8cc1Swenshuai.xi 894*53ee8cc1Swenshuai.xi //Group3-2:HVD System Preset Control command 895*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SYSTEM_PRESET_HVD_BASE = 0x2100, 896*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SYSTEM_PRESET_HVD_CLOCK, //Param: VDEC_EX_ClockSpeed 897*53ee8cc1Swenshuai.xi 898*53ee8cc1Swenshuai.xi //Group3-3:MVD System Preset Control command 899*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SYSTEM_PRESET_MVD_BASE = 0x2200, 900*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SYSTEM_PRESET_MVD_CLOCK, //Param: VDEC_EX_ClockSpeed 901*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_VPU_SECURITY_MODE, //Param: 0:disable,1:enable 902*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_PRESET_DECODE_MODE, 903*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_PRESET_ENABLETURBOMODE, 904*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_PRESETSINGLEDECODE, 905*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_PREGETSTATUS, 906*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SETPOWERSTATE, 907*53ee8cc1Swenshuai.xi 908*53ee8cc1Swenshuai.xi 909*53ee8cc1Swenshuai.xi //Group3-4:Preset Control command============================= 910*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_PRESET_CONTROL_BASE = 0x2300, 911*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_HVD_ONE_PENDING_BUFFER_MODE, //Param: 0(Disable), 1(Enable), use only one pending buffer instead of two for HVD 912*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_MVD_HWBUFFER_REMAPPING_MODE, //Param: 0(Disable), 1(Enable),Allcate HW buffer to start of frame buffer 913*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SET_SHAREMEMORY_BASE, 914*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_HVD_COL_BBU_MODE, //Param: HVD use colocated BBU mode, 0: disable, 1: enable /*johnny.ko*/ 915*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_HVD_IAPGN_BUF_SHARE_BW_MODE, //Param: HVD IAP GN Buffer address, 0xFFFFFFFF means disable 916*53ee8cc1Swenshuai.xi /***/E_VDEC_EX_V2_USER_CMD_DTV_DEBUG_MODE, 917*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_HVD_TS_IN_BBU_MODE, 918*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_AUTO_ARRANGE_FRAMEBUFFER_USAGE, //Param: 0:disable,1:enable, address:PA,size:unit is byte 919*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_THUMBNAIL_MODE, //Param: 0(Disable), 1(Enable), use small frame buffer to decdoe thumbnail 920*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_FORCE_8BIT_DEC_MODE, //Param: force 8bit decode mode, 0: disable, 1: enable 921*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_MFCODEC_MODE, 922*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_VDEC_FEATURE, //AP control VDEC features 923*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_DYNAMIC_CMA_MODE, //enable dynamic cma features 924*53ee8cc1Swenshuai.xi //Group4:Postset Control command====================== 925*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SYSTEM_POSTSET_CONTROL_BASE = 0x3000, 926*53ee8cc1Swenshuai.xi E_VDEC_EX_V2_USER_CMD_SYSTEM_POSTSET_CLEAR_PROCESS_RELATED, 927*53ee8cc1Swenshuai.xi 928*53ee8cc1Swenshuai.xi } VDEC_EX_V2_User_Cmd; 929*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 930*53ee8cc1Swenshuai.xi // Structure for Upper layer 931*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 932*53ee8cc1Swenshuai.xi typedef struct 933*53ee8cc1Swenshuai.xi { 934*53ee8cc1Swenshuai.xi MS_U32 u32Version; 935*53ee8cc1Swenshuai.xi MS_U32 u32Id; 936*53ee8cc1Swenshuai.xi } VDEC_EX_V2_StreamId; 937*53ee8cc1Swenshuai.xi 938*53ee8cc1Swenshuai.xi typedef struct 939*53ee8cc1Swenshuai.xi { 940*53ee8cc1Swenshuai.xi VDEC_EX_V2_StreamId* StreamID; 941*53ee8cc1Swenshuai.xi VDEC_EX_V2_User_Cmd eUserCmd; 942*53ee8cc1Swenshuai.xi void* param[8]; // at most 8 param 943*53ee8cc1Swenshuai.xi void* pRet; 944*53ee8cc1Swenshuai.xi }VDEC_EX_V2_IO_Param; 945*53ee8cc1Swenshuai.xi 946*53ee8cc1Swenshuai.xi typedef struct 947*53ee8cc1Swenshuai.xi { 948*53ee8cc1Swenshuai.xi VDEC_EX_V2_Stream eStream; 949*53ee8cc1Swenshuai.xi VDEC_EX_V2_CodecType eCodecType; 950*53ee8cc1Swenshuai.xi } VDEC_EX_V2_CodecInfo; 951*53ee8cc1Swenshuai.xi 952*53ee8cc1Swenshuai.xi /// Configurations of f/w decode mode 953*53ee8cc1Swenshuai.xi typedef struct 954*53ee8cc1Swenshuai.xi { 955*53ee8cc1Swenshuai.xi VDEC_EX_V2_DEC_MODE eDecMod; 956*53ee8cc1Swenshuai.xi VDEC_EX_V2_CodecInfo pstCodecInfo[VDEC_EX_V2_MAX_DEC_NUM]; 957*53ee8cc1Swenshuai.xi MS_U8 u8CodecCnt; 958*53ee8cc1Swenshuai.xi MS_U8 u8ArgSize; 959*53ee8cc1Swenshuai.xi MS_U32 u32Arg; //ref VDEC_EX_DEC_MODE_ARG enum 960*53ee8cc1Swenshuai.xi } VDEC_EX_V2_DecModCfg; 961*53ee8cc1Swenshuai.xi 962*53ee8cc1Swenshuai.xi typedef struct 963*53ee8cc1Swenshuai.xi { 964*53ee8cc1Swenshuai.xi MS_BOOL bEnable; // 0 : disable , 1:enable 965*53ee8cc1Swenshuai.xi MS_U8 u8DisplayTop; // 0: display top, 1: display bottom 966*53ee8cc1Swenshuai.xi }VDEC_EX_V2_Field_Polarity; 967*53ee8cc1Swenshuai.xi 968*53ee8cc1Swenshuai.xi typedef struct 969*53ee8cc1Swenshuai.xi { 970*53ee8cc1Swenshuai.xi MS_U32 u32version; 971*53ee8cc1Swenshuai.xi MS_U32 u32size; 972*53ee8cc1Swenshuai.xi } VDEC_EX_V2_VerCtl; 973*53ee8cc1Swenshuai.xi 974*53ee8cc1Swenshuai.xi /// Data structure of CC Configuration 975*53ee8cc1Swenshuai.xi typedef struct 976*53ee8cc1Swenshuai.xi { 977*53ee8cc1Swenshuai.xi VDEC_EX_V2_CCFormat eFormat; 978*53ee8cc1Swenshuai.xi VDEC_EX_V2_CCType eType; 979*53ee8cc1Swenshuai.xi MS_VIRT u32BufStAdd; 980*53ee8cc1Swenshuai.xi MS_U32 u32BufSize; 981*53ee8cc1Swenshuai.xi } VDEC_EX_V2_CCCfg; 982*53ee8cc1Swenshuai.xi 983*53ee8cc1Swenshuai.xi /// information for display setting 984*53ee8cc1Swenshuai.xi typedef struct 985*53ee8cc1Swenshuai.xi { 986*53ee8cc1Swenshuai.xi ///bitstream horizontal size 987*53ee8cc1Swenshuai.xi MS_U16 u16HorSize; 988*53ee8cc1Swenshuai.xi ///bitstream vertical size 989*53ee8cc1Swenshuai.xi MS_U16 u16VerSize; 990*53ee8cc1Swenshuai.xi ///frame rate 991*53ee8cc1Swenshuai.xi MS_U32 u32FrameRate; 992*53ee8cc1Swenshuai.xi ///interlace flag 993*53ee8cc1Swenshuai.xi MS_U8 u8Interlace; 994*53ee8cc1Swenshuai.xi ///active frame code 995*53ee8cc1Swenshuai.xi MS_U8 u8AFD; 996*53ee8cc1Swenshuai.xi ///Sample aspect rate width 997*53ee8cc1Swenshuai.xi MS_U16 u16SarWidth; 998*53ee8cc1Swenshuai.xi ///Sample aspect rate height 999*53ee8cc1Swenshuai.xi MS_U16 u16SarHeight; 1000*53ee8cc1Swenshuai.xi ///right cropping 1001*53ee8cc1Swenshuai.xi MS_U16 u16CropRight; 1002*53ee8cc1Swenshuai.xi ///left cropping 1003*53ee8cc1Swenshuai.xi MS_U16 u16CropLeft; 1004*53ee8cc1Swenshuai.xi ///bottom cropping 1005*53ee8cc1Swenshuai.xi MS_U16 u16CropBottom; 1006*53ee8cc1Swenshuai.xi ///top cropping 1007*53ee8cc1Swenshuai.xi MS_U16 u16CropTop; 1008*53ee8cc1Swenshuai.xi ///pitch 1009*53ee8cc1Swenshuai.xi MS_U16 u16Pitch; 1010*53ee8cc1Swenshuai.xi ///interval of PTS 1011*53ee8cc1Swenshuai.xi MS_U16 u16PTSInterval; 1012*53ee8cc1Swenshuai.xi ///MPEG1 flag 1013*53ee8cc1Swenshuai.xi MS_U8 u8MPEG1; 1014*53ee8cc1Swenshuai.xi ///play mode (fixme) 1015*53ee8cc1Swenshuai.xi MS_U8 u8PlayMode; 1016*53ee8cc1Swenshuai.xi ///FRC mode 1017*53ee8cc1Swenshuai.xi MS_U8 u8FrcMode; 1018*53ee8cc1Swenshuai.xi ///aspect ratio code 1019*53ee8cc1Swenshuai.xi MS_U8 u8AspectRate; 1020*53ee8cc1Swenshuai.xi ///if FALSE, set VOP as mono mode (only for H264) 1021*53ee8cc1Swenshuai.xi MS_BOOL bWithChroma; 1022*53ee8cc1Swenshuai.xi /// if true, color space is xvYCC (Y from 16 to 235 and Cb , Cr from 16 to 240). 1023*53ee8cc1Swenshuai.xi /// if false, color space is BT.601/709 (Y from 0 to 255 and Cb , Cr from 0 to 255). 1024*53ee8cc1Swenshuai.xi /// only MPEG might be with BT.601/709 1025*53ee8cc1Swenshuai.xi MS_BOOL bColorInXVYCC; 1026*53ee8cc1Swenshuai.xi ///Dynamic scaling buffer address 1027*53ee8cc1Swenshuai.xi MS_VIRT u32DynScalingAddr; 1028*53ee8cc1Swenshuai.xi ///Dynamic scaling buffer size 1029*53ee8cc1Swenshuai.xi MS_U32 u32DynScalingSize; 1030*53ee8cc1Swenshuai.xi ///Dynamic scaling depth 1031*53ee8cc1Swenshuai.xi MS_U8 u8DynScalingDepth; 1032*53ee8cc1Swenshuai.xi ///Dynamic scaling DS buffer on miu1 or miu0 1033*53ee8cc1Swenshuai.xi MS_BOOL bEnableMIUSel; 1034*53ee8cc1Swenshuai.xi ///Display width 1035*53ee8cc1Swenshuai.xi MS_U32 u32AspectWidth; 1036*53ee8cc1Swenshuai.xi ///Display height 1037*53ee8cc1Swenshuai.xi MS_U32 u32AspectHeight; 1038*53ee8cc1Swenshuai.xi } VDEC_EX_V2_DispInfo; 1039*53ee8cc1Swenshuai.xi 1040*53ee8cc1Swenshuai.xi /// system configuration 1041*53ee8cc1Swenshuai.xi typedef struct 1042*53ee8cc1Swenshuai.xi { 1043*53ee8cc1Swenshuai.xi ///FW binary start address 1044*53ee8cc1Swenshuai.xi MS_PHY u32FWBinaryAddr; 1045*53ee8cc1Swenshuai.xi ///FW binary size 1046*53ee8cc1Swenshuai.xi MS_U32 u32FWBinarySize; 1047*53ee8cc1Swenshuai.xi ///FW code buffer start address 1048*53ee8cc1Swenshuai.xi MS_PHY u32CodeBufAddr; 1049*53ee8cc1Swenshuai.xi ///FW code buffer size 1050*53ee8cc1Swenshuai.xi MS_U32 u32CodeBufSize; 1051*53ee8cc1Swenshuai.xi ///frame buffer start address 1052*53ee8cc1Swenshuai.xi MS_PHY u32FrameBufAddr; 1053*53ee8cc1Swenshuai.xi ///frame buffer size 1054*53ee8cc1Swenshuai.xi MS_U32 u32FrameBufSize; 1055*53ee8cc1Swenshuai.xi ///bitstream buffer start address 1056*53ee8cc1Swenshuai.xi MS_PHY u32BitstreamBufAddr; 1057*53ee8cc1Swenshuai.xi ///bitstream buffer size 1058*53ee8cc1Swenshuai.xi MS_U32 u32BitstreamBufSize; 1059*53ee8cc1Swenshuai.xi ///driver process buffer start address 1060*53ee8cc1Swenshuai.xi MS_PHY u32DrvProcBufAddr; 1061*53ee8cc1Swenshuai.xi ///driver process buffer size 1062*53ee8cc1Swenshuai.xi MS_U32 u32DrvProcBufSize; 1063*53ee8cc1Swenshuai.xi ///vlc table Binary address (RM only) 1064*53ee8cc1Swenshuai.xi MS_PHY u32VlcBinarySrcAddr; 1065*53ee8cc1Swenshuai.xi ///vld table Binary size 1066*53ee8cc1Swenshuai.xi MS_U32 u32VlcTabBinarySize; 1067*53ee8cc1Swenshuai.xi ///debug level setting 1068*53ee8cc1Swenshuai.xi VDEC_EX_V2_DbgLevel eDbgMsgLevel; 1069*53ee8cc1Swenshuai.xi ///debug level setting 1070*53ee8cc1Swenshuai.xi VDEC_EX_V2_FWSourceType eFWSourceType; 1071*53ee8cc1Swenshuai.xi } VDEC_EX_V2_SysCfg; 1072*53ee8cc1Swenshuai.xi 1073*53ee8cc1Swenshuai.xi /// video information 1074*53ee8cc1Swenshuai.xi typedef struct 1075*53ee8cc1Swenshuai.xi { 1076*53ee8cc1Swenshuai.xi ///input source mode 1077*53ee8cc1Swenshuai.xi VDEC_EX_V2_SrcMode eSrcMode; 1078*53ee8cc1Swenshuai.xi /// timestamp type of command queue 1079*53ee8cc1Swenshuai.xi VDEC_EX_V2_TimeStampType eTimeStampType; 1080*53ee8cc1Swenshuai.xi ///MJPEG scale factor 1081*53ee8cc1Swenshuai.xi VDEC_EX_V2_MJpegScaleFactor eMJpegScaleFactor; 1082*53ee8cc1Swenshuai.xi /// should be TRUE when codec type is H264 and container is MKV and MP4(MOV) 1083*53ee8cc1Swenshuai.xi MS_BOOL bWithoutNalStCode; 1084*53ee8cc1Swenshuai.xi /// needness when CodecType is MJPEG and divx311 1085*53ee8cc1Swenshuai.xi //MS_U16 u16FrameRate; 1086*53ee8cc1Swenshuai.xi MS_U32 u32FrameRate; 1087*53ee8cc1Swenshuai.xi MS_U32 u32FrameRateBase; 1088*53ee8cc1Swenshuai.xi /// if divx311; use u16Width[0]; only need other elements when RV8 1089*53ee8cc1Swenshuai.xi MS_U16 u16Width[8]; 1090*53ee8cc1Swenshuai.xi /// if divx311; use u16Height[0]; only need other elements when RV8 1091*53ee8cc1Swenshuai.xi MS_U16 u16Height[8]; 1092*53ee8cc1Swenshuai.xi /// video number sizes (for RM) 1093*53ee8cc1Swenshuai.xi MS_U16 u16NumSizes; 1094*53ee8cc1Swenshuai.xi } VDEC_EX_V2_VideoInfo; 1095*53ee8cc1Swenshuai.xi 1096*53ee8cc1Swenshuai.xi /// frame information 1097*53ee8cc1Swenshuai.xi typedef struct 1098*53ee8cc1Swenshuai.xi { 1099*53ee8cc1Swenshuai.xi /// frame buffer base + the start offset of current displayed luma data. Unit: byte. 1100*53ee8cc1Swenshuai.xi MS_PHY u32LumaAddr; 1101*53ee8cc1Swenshuai.xi /// frame buffer base + the start offset of current displayed chroma data. Unit: byte. 1102*53ee8cc1Swenshuai.xi MS_PHY u32ChromaAddr; 1103*53ee8cc1Swenshuai.xi /// Time stamp(DTS, PTS) of current displayed frame. Unit: ms (todo: 90khz) 1104*53ee8cc1Swenshuai.xi MS_U32 u32TimeStamp; 1105*53ee8cc1Swenshuai.xi /// low part of ID number 1106*53ee8cc1Swenshuai.xi MS_U32 u32ID_L; 1107*53ee8cc1Swenshuai.xi /// high part of ID number 1108*53ee8cc1Swenshuai.xi MS_U32 u32ID_H; 1109*53ee8cc1Swenshuai.xi /// pitch 1110*53ee8cc1Swenshuai.xi MS_U16 u16Pitch; 1111*53ee8cc1Swenshuai.xi /// width 1112*53ee8cc1Swenshuai.xi MS_U16 u16Width; 1113*53ee8cc1Swenshuai.xi /// hight 1114*53ee8cc1Swenshuai.xi MS_U16 u16Height; 1115*53ee8cc1Swenshuai.xi ///< Frame type: I, P, B frame 1116*53ee8cc1Swenshuai.xi VDEC_EX_V2_FrameType eFrameType; 1117*53ee8cc1Swenshuai.xi ///< Field type: Top, Bottom, Both 1118*53ee8cc1Swenshuai.xi VDEC_EX_V2_FieldType eFieldType; 1119*53ee8cc1Swenshuai.xi } VDEC_EX_V2_FrameInfo; 1120*53ee8cc1Swenshuai.xi 1121*53ee8cc1Swenshuai.xi typedef struct 1122*53ee8cc1Swenshuai.xi { 1123*53ee8cc1Swenshuai.xi VDEC_EX_V2_FrameInfo sFrameInfo; 1124*53ee8cc1Swenshuai.xi 1125*53ee8cc1Swenshuai.xi MS_PHY u32LumaAddr_2bit; 1126*53ee8cc1Swenshuai.xi MS_PHY u32ChromaAddr_2bit; 1127*53ee8cc1Swenshuai.xi MS_U8 u8LumaBitdepth; 1128*53ee8cc1Swenshuai.xi MS_U8 u8ChromaBitdepth; 1129*53ee8cc1Swenshuai.xi MS_U16 u16Pitch_2bit; 1130*53ee8cc1Swenshuai.xi 1131*53ee8cc1Swenshuai.xi MS_U8 u8Reserved[64]; 1132*53ee8cc1Swenshuai.xi } VDEC_EX_V2_FrameInfoEX; 1133*53ee8cc1Swenshuai.xi 1134*53ee8cc1Swenshuai.xi //Extension of frame info(VDEC_EX_FrameInfoEX) 1135*53ee8cc1Swenshuai.xi typedef struct 1136*53ee8cc1Swenshuai.xi { 1137*53ee8cc1Swenshuai.xi VDEC_EX_V2_VerCtl stVerCtl; /// version : 0, 1138*53ee8cc1Swenshuai.xi VDEC_EX_V2_FrameInfo sFrameInfo; 1139*53ee8cc1Swenshuai.xi MS_PHY u32LumaAddr_2bit; 1140*53ee8cc1Swenshuai.xi MS_PHY u32ChromaAddr_2bit; 1141*53ee8cc1Swenshuai.xi MS_PHY u32LumaAddrI; 1142*53ee8cc1Swenshuai.xi MS_PHY u32LumaAddrI_2bit; 1143*53ee8cc1Swenshuai.xi MS_PHY u32ChromaAddrI; 1144*53ee8cc1Swenshuai.xi MS_PHY u32ChromaAddrI_2bit; 1145*53ee8cc1Swenshuai.xi MS_U32 u32MFCodecInfo; 1146*53ee8cc1Swenshuai.xi MS_U32 u32LumaMFCbitlen; 1147*53ee8cc1Swenshuai.xi MS_U32 u32ChromaMFCbitlen; 1148*53ee8cc1Swenshuai.xi MS_U16 u16Pitch_2bit; 1149*53ee8cc1Swenshuai.xi MS_U8 u8LumaBitdepth; 1150*53ee8cc1Swenshuai.xi MS_U8 u8ChromaBitdepth; 1151*53ee8cc1Swenshuai.xi ////HVD_MasteringDisplayColourVolume// 1152*53ee8cc1Swenshuai.xi MS_U32 maxLuminance; 1153*53ee8cc1Swenshuai.xi MS_U32 minLuminance; 1154*53ee8cc1Swenshuai.xi MS_U16 primaries[3][2]; 1155*53ee8cc1Swenshuai.xi MS_U16 whitePoint[2]; 1156*53ee8cc1Swenshuai.xi MS_U8 Frm_Info_Ext_avail; ///bit[1]: SEI_Enabled, bit[0]: colur_description_present_flag 1157*53ee8cc1Swenshuai.xi ////colour_description//////////// 1158*53ee8cc1Swenshuai.xi MS_U8 colour_primaries; // u(8) 1159*53ee8cc1Swenshuai.xi MS_U8 transfer_characteristics; // u(8) 1160*53ee8cc1Swenshuai.xi MS_U8 matrix_coefficients; // u(8) 1161*53ee8cc1Swenshuai.xi } VDEC_EX_V2_FrameInfoExt; 1162*53ee8cc1Swenshuai.xi 1163*53ee8cc1Swenshuai.xi typedef struct 1164*53ee8cc1Swenshuai.xi { 1165*53ee8cc1Swenshuai.xi MS_BOOL bUsed; 1166*53ee8cc1Swenshuai.xi MS_BOOL bColourVolumeSEIEnabled; 1167*53ee8cc1Swenshuai.xi MS_U32 u32MaxLuminance; 1168*53ee8cc1Swenshuai.xi MS_U32 u32MinLuminance; 1169*53ee8cc1Swenshuai.xi MS_U16 u16Primaries[3][2]; 1170*53ee8cc1Swenshuai.xi MS_U16 u16WhitePoint[2]; 1171*53ee8cc1Swenshuai.xi }VDEC_EX_V2_DisplayColourVolume_SEI; 1172*53ee8cc1Swenshuai.xi 1173*53ee8cc1Swenshuai.xi typedef struct 1174*53ee8cc1Swenshuai.xi { 1175*53ee8cc1Swenshuai.xi VDEC_EX_V2_FrameInfoExt sFrameInfoExt; 1176*53ee8cc1Swenshuai.xi ////HVD_MasteringDisplayColourVolume// 1177*53ee8cc1Swenshuai.xi VDEC_EX_V2_DisplayColourVolume_SEI sDisplay_colour_volume; 1178*53ee8cc1Swenshuai.xi MS_U8 u8Frm_Info_Ext_avail; ///bit[1]: SEI_Enabled, bit[0]: colur_description_present_flag 1179*53ee8cc1Swenshuai.xi ////colour_description//////////// 1180*53ee8cc1Swenshuai.xi MS_U8 u8Colour_primaries; // u(8) 1181*53ee8cc1Swenshuai.xi MS_U8 u8Transfer_characteristics; // u(8) 1182*53ee8cc1Swenshuai.xi MS_U8 u8Matrix_coefficients; // u(8) 1183*53ee8cc1Swenshuai.xi } VDEC_EX_V2_FrameInfoExt_v2; 1184*53ee8cc1Swenshuai.xi 1185*53ee8cc1Swenshuai.xi /// Extension display information 1186*53ee8cc1Swenshuai.xi typedef struct 1187*53ee8cc1Swenshuai.xi { 1188*53ee8cc1Swenshuai.xi /// vertical size from sequene_display_extension 1189*53ee8cc1Swenshuai.xi MS_U16 u16VSize; 1190*53ee8cc1Swenshuai.xi /// horizontal size from sequene_display_extension 1191*53ee8cc1Swenshuai.xi MS_U16 u16HSize; 1192*53ee8cc1Swenshuai.xi /// vertical offset from picture_display_extension 1193*53ee8cc1Swenshuai.xi MS_S16 s16VOffset; 1194*53ee8cc1Swenshuai.xi /// horizontal offset from picture_display_extension 1195*53ee8cc1Swenshuai.xi MS_S16 s16HOffset; 1196*53ee8cc1Swenshuai.xi } VDEC_EX_V2_ExtDispInfo; 1197*53ee8cc1Swenshuai.xi 1198*53ee8cc1Swenshuai.xi /// display frame information 1199*53ee8cc1Swenshuai.xi typedef struct 1200*53ee8cc1Swenshuai.xi { 1201*53ee8cc1Swenshuai.xi ///< frame information 1202*53ee8cc1Swenshuai.xi VDEC_EX_V2_FrameInfo stFrmInfo; 1203*53ee8cc1Swenshuai.xi ///< firmware private data 1204*53ee8cc1Swenshuai.xi MS_U32 u32PriData; 1205*53ee8cc1Swenshuai.xi ///< index used by apiVDEC to manage VDEC_DispQ[][] 1206*53ee8cc1Swenshuai.xi MS_U32 u32Idx; 1207*53ee8cc1Swenshuai.xi } VDEC_EX_V2_DispFrame; 1208*53ee8cc1Swenshuai.xi 1209*53ee8cc1Swenshuai.xi /// time code structure 1210*53ee8cc1Swenshuai.xi typedef struct 1211*53ee8cc1Swenshuai.xi { 1212*53ee8cc1Swenshuai.xi /// time_code_hours 1213*53ee8cc1Swenshuai.xi MS_U8 u8TimeCodeHr; 1214*53ee8cc1Swenshuai.xi /// time_code_minutes 1215*53ee8cc1Swenshuai.xi MS_U8 u8TimeCodeMin; 1216*53ee8cc1Swenshuai.xi /// time_code_seconds 1217*53ee8cc1Swenshuai.xi MS_U8 u8TimeCodeSec; 1218*53ee8cc1Swenshuai.xi /// time_code_pictures 1219*53ee8cc1Swenshuai.xi MS_U8 u8TimeCodePic; 1220*53ee8cc1Swenshuai.xi /// drop_frame_flag 1221*53ee8cc1Swenshuai.xi MS_U8 u8DropFrmFlag; 1222*53ee8cc1Swenshuai.xi /// reserved fields for 4-byte alignment 1223*53ee8cc1Swenshuai.xi MS_U8 u8Reserved[3]; 1224*53ee8cc1Swenshuai.xi } VDEC_EX_V2_TimeCode; 1225*53ee8cc1Swenshuai.xi 1226*53ee8cc1Swenshuai.xi /// vdec frame buffer reduction 1227*53ee8cc1Swenshuai.xi typedef struct 1228*53ee8cc1Swenshuai.xi { 1229*53ee8cc1Swenshuai.xi VDEC_EX_V2_FBReductionType eLumaFBReduction; 1230*53ee8cc1Swenshuai.xi VDEC_EX_V2_FBReductionType eChromaFBReduction; 1231*53ee8cc1Swenshuai.xi MS_BOOL bEnableAutoMode; /// 0: Disable, 1: Enable 1232*53ee8cc1Swenshuai.xi } VDEC_EX_V2_FBReduction; 1233*53ee8cc1Swenshuai.xi 1234*53ee8cc1Swenshuai.xi /// Initial parameter 1235*53ee8cc1Swenshuai.xi typedef struct 1236*53ee8cc1Swenshuai.xi { 1237*53ee8cc1Swenshuai.xi /// init param version : 0 1238*53ee8cc1Swenshuai.xi MS_U32 u32Version; 1239*53ee8cc1Swenshuai.xi /// codec type 1240*53ee8cc1Swenshuai.xi VDEC_EX_V2_CodecType eCodecType; 1241*53ee8cc1Swenshuai.xi /// system configuration 1242*53ee8cc1Swenshuai.xi VDEC_EX_V2_SysCfg SysConfig; 1243*53ee8cc1Swenshuai.xi /// video information from container 1244*53ee8cc1Swenshuai.xi VDEC_EX_V2_VideoInfo VideoInfo; 1245*53ee8cc1Swenshuai.xi /// dynamic scaling control bit 1246*53ee8cc1Swenshuai.xi MS_BOOL EnableDynaScale; 1247*53ee8cc1Swenshuai.xi /// switch for display decode error frame or not 1248*53ee8cc1Swenshuai.xi MS_BOOL bDisableDropErrFrame; 1249*53ee8cc1Swenshuai.xi /// switch for error concealment 1250*53ee8cc1Swenshuai.xi MS_BOOL bDisableErrConceal; 1251*53ee8cc1Swenshuai.xi /// enable repeat last field when repeat happened at interlace stream 1252*53ee8cc1Swenshuai.xi MS_BOOL bRepeatLastField; 1253*53ee8cc1Swenshuai.xi /// threshold to judge error frame 1254*53ee8cc1Swenshuai.xi MS_U8 u8ErrThreshold; 1255*53ee8cc1Swenshuai.xi /// dynamic scaling virtual box Width 1256*53ee8cc1Swenshuai.xi MS_U32 u32DSVirtualBoxWidth; 1257*53ee8cc1Swenshuai.xi /// dynamic scaling virtual box Height 1258*53ee8cc1Swenshuai.xi MS_U32 u32DSVirtualBoxHeight; 1259*53ee8cc1Swenshuai.xi /// vdec frame buffer reduction setting 1260*53ee8cc1Swenshuai.xi VDEC_EX_V2_FBReduction stFBReduction; 1261*53ee8cc1Swenshuai.xi } VDEC_EX_V2_InitParam; 1262*53ee8cc1Swenshuai.xi 1263*53ee8cc1Swenshuai.xi /// Decode Command 1264*53ee8cc1Swenshuai.xi typedef struct 1265*53ee8cc1Swenshuai.xi { 1266*53ee8cc1Swenshuai.xi /// ID (high 4-bytes) 1267*53ee8cc1Swenshuai.xi MS_U32 u32ID_H; 1268*53ee8cc1Swenshuai.xi /// ID (low 4-bytes) 1269*53ee8cc1Swenshuai.xi MS_U32 u32ID_L; 1270*53ee8cc1Swenshuai.xi /// start address of payload 1271*53ee8cc1Swenshuai.xi MS_VIRT u32StAddr; 1272*53ee8cc1Swenshuai.xi /// size of payload 1273*53ee8cc1Swenshuai.xi MS_U32 u32Size; 1274*53ee8cc1Swenshuai.xi /// timestamp of payload 1275*53ee8cc1Swenshuai.xi MS_U32 u32Timestamp; 1276*53ee8cc1Swenshuai.xi } VDEC_EX_V2_DecCmd; 1277*53ee8cc1Swenshuai.xi 1278*53ee8cc1Swenshuai.xi /// Display Command 1279*53ee8cc1Swenshuai.xi typedef struct 1280*53ee8cc1Swenshuai.xi { 1281*53ee8cc1Swenshuai.xi /// ID (high 4-bytes) 1282*53ee8cc1Swenshuai.xi MS_U32 u32ID_H; 1283*53ee8cc1Swenshuai.xi /// ID (low 4-bytes) 1284*53ee8cc1Swenshuai.xi MS_U32 u32ID_L; 1285*53ee8cc1Swenshuai.xi /// action of command 1286*53ee8cc1Swenshuai.xi VDEC_EX_V2_DispCmdAction eAction; 1287*53ee8cc1Swenshuai.xi } VDEC_EX_V2_DispCmd; 1288*53ee8cc1Swenshuai.xi 1289*53ee8cc1Swenshuai.xi typedef struct 1290*53ee8cc1Swenshuai.xi { 1291*53ee8cc1Swenshuai.xi MS_U32 u32Version; 1292*53ee8cc1Swenshuai.xi /// top, bottom or frame 1293*53ee8cc1Swenshuai.xi VDEC_EX_V2_PicStructure u8PicStructure; 1294*53ee8cc1Swenshuai.xi MS_U8 u8TopFieldFirst; 1295*53ee8cc1Swenshuai.xi MS_U16 u16TempRef; 1296*53ee8cc1Swenshuai.xi MS_U32 u32Pts; 1297*53ee8cc1Swenshuai.xi /// address of cc data 1298*53ee8cc1Swenshuai.xi MS_U32 u32UserDataBuf; 1299*53ee8cc1Swenshuai.xi /// size of cc data 1300*53ee8cc1Swenshuai.xi MS_U32 u32UserDataSize; 1301*53ee8cc1Swenshuai.xi ///< Frame type: I, P, B frame 1302*53ee8cc1Swenshuai.xi VDEC_EX_V2_FrameType eFrameType; 1303*53ee8cc1Swenshuai.xi } VDEC_EX_V2_CC_Info; 1304*53ee8cc1Swenshuai.xi 1305*53ee8cc1Swenshuai.xi ///CC input parameters for mstar proprietary CC library 1306*53ee8cc1Swenshuai.xi typedef struct 1307*53ee8cc1Swenshuai.xi { 1308*53ee8cc1Swenshuai.xi MS_U32 u32Ver; ///version of this structure 1309*53ee8cc1Swenshuai.xi MS_U32 u32Val; 1310*53ee8cc1Swenshuai.xi } VDEC_EX_V2_CC_InputPara; 1311*53ee8cc1Swenshuai.xi 1312*53ee8cc1Swenshuai.xi typedef struct 1313*53ee8cc1Swenshuai.xi { 1314*53ee8cc1Swenshuai.xi MS_U32 u32OutputFrameRate; ///< output frame rate, unit:vsync count 1315*53ee8cc1Swenshuai.xi MS_U8 u8Interlace; ///< output scan:0:progress, 1:interlace 1316*53ee8cc1Swenshuai.xi } VDEC_EX_V2_FRC_OutputParam; 1317*53ee8cc1Swenshuai.xi 1318*53ee8cc1Swenshuai.xi 1319*53ee8cc1Swenshuai.xi typedef void (*VDEC_EX_V2_EventCb)(MS_U32 eFlag, void *param); 1320*53ee8cc1Swenshuai.xi 1321*53ee8cc1Swenshuai.xi typedef struct 1322*53ee8cc1Swenshuai.xi { 1323*53ee8cc1Swenshuai.xi MS_U8 u8Frm_packing_arr_cnl_flag; 1324*53ee8cc1Swenshuai.xi MS_U8 u8Frm_packing_arr_type; 1325*53ee8cc1Swenshuai.xi MS_U8 u8content_interpretation_type; 1326*53ee8cc1Swenshuai.xi MS_U8 u1Quincunx_sampling_flag; 1327*53ee8cc1Swenshuai.xi 1328*53ee8cc1Swenshuai.xi MS_U8 u1Spatial_flipping_flag; 1329*53ee8cc1Swenshuai.xi MS_U8 u1Frame0_flipping_flag; 1330*53ee8cc1Swenshuai.xi MS_U8 u1Field_views_flag; 1331*53ee8cc1Swenshuai.xi MS_U8 u1Current_frame_is_frame0_flag; 1332*53ee8cc1Swenshuai.xi 1333*53ee8cc1Swenshuai.xi MS_U8 u1Frame0_self_contained_flag; 1334*53ee8cc1Swenshuai.xi MS_U8 u1Frame1_self_contained_flag; 1335*53ee8cc1Swenshuai.xi MS_U8 u4Frame0_grid_position_x; 1336*53ee8cc1Swenshuai.xi MS_U8 u4Frame0_grid_position_y; 1337*53ee8cc1Swenshuai.xi 1338*53ee8cc1Swenshuai.xi MS_U8 u4Frame1_grid_position_x; 1339*53ee8cc1Swenshuai.xi MS_U8 u4Frame1_grid_position_y; 1340*53ee8cc1Swenshuai.xi MS_U8 u8Reserved01; 1341*53ee8cc1Swenshuai.xi MS_U8 u8Reserved02; 1342*53ee8cc1Swenshuai.xi }VDEC_EX_V2_Frame_packing_SEI; 1343*53ee8cc1Swenshuai.xi 1344*53ee8cc1Swenshuai.xi typedef struct 1345*53ee8cc1Swenshuai.xi { 1346*53ee8cc1Swenshuai.xi VDEC_EX_V2_VerCtl stVerCtl; /// version : 0, 1347*53ee8cc1Swenshuai.xi /// size : sizeof(VDEC_EX_Frame_packing_SEI_EX) 1348*53ee8cc1Swenshuai.xi MS_BOOL bIsCropInfo; 1349*53ee8cc1Swenshuai.xi MS_BOOL bValid; 1350*53ee8cc1Swenshuai.xi MS_BOOL bUsed; 1351*53ee8cc1Swenshuai.xi MS_U8 u8Frm_packing_arr_cnl_flag; 1352*53ee8cc1Swenshuai.xi MS_U8 u8Frm_packing_arr_type; 1353*53ee8cc1Swenshuai.xi MS_U8 u8content_interpretation_type; 1354*53ee8cc1Swenshuai.xi MS_U8 u1Quincunx_sampling_flag; 1355*53ee8cc1Swenshuai.xi MS_U8 u1Spatial_flipping_flag; 1356*53ee8cc1Swenshuai.xi MS_U8 u1Frame0_flipping_flag; 1357*53ee8cc1Swenshuai.xi MS_U8 u1Field_views_flag; 1358*53ee8cc1Swenshuai.xi MS_U8 u1Current_frame_is_frame0_flag; 1359*53ee8cc1Swenshuai.xi MS_U8 u1Frame0_self_contained_flag; 1360*53ee8cc1Swenshuai.xi MS_U8 u1Frame1_self_contained_flag; 1361*53ee8cc1Swenshuai.xi MS_U8 u4Frame0_grid_position_x; 1362*53ee8cc1Swenshuai.xi MS_U8 u4Frame0_grid_position_y; 1363*53ee8cc1Swenshuai.xi MS_U8 u4Frame1_grid_position_x; 1364*53ee8cc1Swenshuai.xi MS_U8 u4Frame1_grid_position_y; 1365*53ee8cc1Swenshuai.xi MS_U32 u32DataBuff; 1366*53ee8cc1Swenshuai.xi MS_U32 u32DataSize; 1367*53ee8cc1Swenshuai.xi MS_U32 left; 1368*53ee8cc1Swenshuai.xi MS_U32 right; 1369*53ee8cc1Swenshuai.xi MS_U32 top; 1370*53ee8cc1Swenshuai.xi MS_U32 bottom; 1371*53ee8cc1Swenshuai.xi } VDEC_EX_V2_Frame_packing_SEI_EX; 1372*53ee8cc1Swenshuai.xi 1373*53ee8cc1Swenshuai.xi typedef struct 1374*53ee8cc1Swenshuai.xi { 1375*53ee8cc1Swenshuai.xi MS_BOOL bAspect_ratio_info_present_flag; // u(1) 1376*53ee8cc1Swenshuai.xi MS_U8 u8Aspect_ratio_idc; // u(8) 1377*53ee8cc1Swenshuai.xi MS_U16 u16Sar_width; // u(16) 1378*53ee8cc1Swenshuai.xi MS_U16 u16Sar_height; // u(16) 1379*53ee8cc1Swenshuai.xi MS_BOOL bOverscan_info_present_flag; // u(1) 1380*53ee8cc1Swenshuai.xi MS_BOOL bOverscan_appropriate_flag; // u(1) 1381*53ee8cc1Swenshuai.xi MS_BOOL bVideo_signal_type_present_flag; // u(1) 1382*53ee8cc1Swenshuai.xi MS_U8 u8Video_format; // u(3) 1383*53ee8cc1Swenshuai.xi MS_BOOL bVideo_full_range_flag; // u(1) 1384*53ee8cc1Swenshuai.xi MS_BOOL bColour_description_present_flag; // u(1) 1385*53ee8cc1Swenshuai.xi MS_U8 u8Colour_primaries; // u(8) 1386*53ee8cc1Swenshuai.xi MS_U8 u8Transfer_characteristics; // u(8) 1387*53ee8cc1Swenshuai.xi MS_U8 u8Matrix_coefficients; // u(8) 1388*53ee8cc1Swenshuai.xi MS_BOOL bChroma_location_info_present_flag; // u(1) 1389*53ee8cc1Swenshuai.xi MS_U8 u8Chroma_sample_loc_type_top_field; // ue(v) 0~5 1390*53ee8cc1Swenshuai.xi MS_U8 u8Chroma_sample_loc_type_bottom_field; // ue(v) 0~5 1391*53ee8cc1Swenshuai.xi MS_BOOL bTiming_info_present_flag; // u(1) 1392*53ee8cc1Swenshuai.xi MS_BOOL bFixed_frame_rate_flag; // u(1) 1393*53ee8cc1Swenshuai.xi MS_U32 u32Num_units_in_tick; // u(32) 1394*53ee8cc1Swenshuai.xi MS_U32 u32Time_scale; // u(32) 1395*53ee8cc1Swenshuai.xi } VDEC_EX_V2_AVC_VUI_DISP_INFO; 1396*53ee8cc1Swenshuai.xi 1397*53ee8cc1Swenshuai.xi //CRC value 1398*53ee8cc1Swenshuai.xi typedef struct 1399*53ee8cc1Swenshuai.xi { 1400*53ee8cc1Swenshuai.xi MS_U32 u32HorSize; 1401*53ee8cc1Swenshuai.xi MS_U32 u32VerSize; 1402*53ee8cc1Swenshuai.xi MS_U32 u32Strip; 1403*53ee8cc1Swenshuai.xi MS_VIRT u32LumaStartAddr; 1404*53ee8cc1Swenshuai.xi MS_VIRT u32ChromaStartAddr; 1405*53ee8cc1Swenshuai.xi }VDEC_EX_V2_CrcIn; 1406*53ee8cc1Swenshuai.xi 1407*53ee8cc1Swenshuai.xi typedef struct 1408*53ee8cc1Swenshuai.xi { 1409*53ee8cc1Swenshuai.xi MS_U32 u32LumaCRC; 1410*53ee8cc1Swenshuai.xi MS_U32 u32ChromaCRC; 1411*53ee8cc1Swenshuai.xi }VDEC_EX_V2_CrcOut; 1412*53ee8cc1Swenshuai.xi 1413*53ee8cc1Swenshuai.xi typedef struct 1414*53ee8cc1Swenshuai.xi { 1415*53ee8cc1Swenshuai.xi VDEC_EX_V2_CrcIn stCrcIn; 1416*53ee8cc1Swenshuai.xi VDEC_EX_V2_CrcOut stCrcOut; 1417*53ee8cc1Swenshuai.xi }VDEC_EX_V2_CrcValue; 1418*53ee8cc1Swenshuai.xi 1419*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 1420*53ee8cc1Swenshuai.xi // Function pointer for Upper layer 1421*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 1422*53ee8cc1Swenshuai.xi 1423*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 1424*53ee8cc1Swenshuai.xi // API for Upper layer 1425*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 1426*53ee8cc1Swenshuai.xi 1427*53ee8cc1Swenshuai.xi void VDEC_EX_V2_RegisterToUtopia(FUtopiaOpen ModuleType); 1428*53ee8cc1Swenshuai.xi MS_U32 VDEC_EX_V2_Open(void** ppInstance, const void* const pAttribute); 1429*53ee8cc1Swenshuai.xi MS_U32 VDEC_EX_V2_Close(void* pInstance); 1430*53ee8cc1Swenshuai.xi MS_U32 VDEC_EX_V2_IOctl(void* pInstance, MS_U32 u32Cmd, void* pArgs); 1431*53ee8cc1Swenshuai.xi 1432*53ee8cc1Swenshuai.xi #ifdef __cplusplus 1433*53ee8cc1Swenshuai.xi } 1434*53ee8cc1Swenshuai.xi #endif 1435*53ee8cc1Swenshuai.xi 1436*53ee8cc1Swenshuai.xi #endif 1437*53ee8cc1Swenshuai.xi #undef _VDEC_EX_V2_H_ 1438*53ee8cc1Swenshuai.xi #endif //_VDEC_EX_V2_H_ 1439