1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. 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If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 78 #ifndef _VDEC_EX_V2_H_ 79 #define _VDEC_EX_V2_H_ 80 81 #if !defined(MSOS_TYPE_NUTTX) || defined(SUPPORT_X_MODEL_FEATURE) 82 #ifdef __cplusplus 83 extern "C" 84 { 85 #endif 86 87 #include "MsTypes.h" 88 //------------------------------------------------------------------------------------------------- 89 // Define for Upper layer 90 //------------------------------------------------------------------------------------------------- 91 //------------------------------------------------------------------------------------------------- 92 // Macro and Define 93 //------------------------------------------------------------------------------------------------- 94 #define MSIF_VDEC_EX_V2_LIB_CODE {'V','E','X','2'} 95 #define MSIF_VDEC_EX_V2_LIBVER {'0','5'} 96 #define MSIF_VDEC_EX_V2_BUILDNUM {'0','3'} 97 #define MSIF_VDEC_EX_V2_CHANGELIST {'0','0','6','9','3','0','7','7'} 98 99 /// Version string. 100 #define VDEC_EX_V2_API_VERSION /* Character String for DRV/API version */ \ 101 MSIF_TAG, /* 'MSIF' */ \ 102 MSIF_CLASS, /* '00' */ \ 103 MSIF_CUS, /* 0x0000 */ \ 104 MSIF_MOD, /* 0x0000 */ \ 105 MSIF_CHIP, \ 106 MSIF_CPU, \ 107 MSIF_VDEC_EX_V2_LIB_CODE, /* IP__ */ \ 108 MSIF_VDEC_EX_V2_LIBVER, /* 0.0 ~ Z.Z */ \ 109 MSIF_VDEC_EX_V2_BUILDNUM, /* 00 ~ 99 */ \ 110 MSIF_VDEC_EX_V2_CHANGELIST, /* CL# */ \ 111 MSIF_OS 112 113 #define VDEC_EX_V2_DEFAULT_DBG_MSG_LEVEL E_VDEC_EX_DBG_LEVEL_DBG 114 #define VDEC_EX_V2_RVD_BROKEN_BY_US 0x80000000 115 #define VDEC_EX_V2_MVD_PIC_START_FLAG 0x40000000 116 117 #define VDEC_EX_V2_BIT(_bit_) (1 << (_bit_)) 118 119 #define VDEC_EX_V2_FPA_TYPE_CHECKERBOARD_INTERLEAVING 0 120 #define VDEC_EX_V2_FPA_TYPE_COLUMN_INTERLEAVEING 1 121 #define VDEC_EX_V2_FPA_TYPE_ROW_INTERLEAVEING 2 122 #define VDEC_EX_V2_FPA_TYPE_SIDE_BY_SIDE_PACKING 3 123 #define VDEC_EX_V2_FPA_TYPE_TOP_BOTTOM_PACKING 4 124 #define VDEC_EX_V2_FPA_TYPE_TEMPORAL_INTERLEAVING_FRM 5 125 #define VDEC_EX_V2_MAX_DEC_NUM 2 126 127 #define VDEC_CAP_DYNAMIC_CMA 128 #define VDEC_CAP_DISABLE_HEVC_10BITS // MApi_VDEC_EX_PreSetControl((VDEC_StreamId *)pHandle, E_VDEC_EX_USER_CMD_VDEC_FEATURE, E_VDEC_EX_FEATURE_FORCE_MAIN_PROFILE); 129 //------------------------------------------------------------------------------------------------- 130 // Type and Structure 131 //------------------------------------------------------------------------------------------------- 132 133 //------------------------------------------------------------------------------------------------- 134 // Enum for Upper layer 135 //------------------------------------------------------------------------------------------------- 136 typedef enum 137 { 138 E_VDEC_EX_V2_MAIN_STREAM = 0, 139 E_VDEC_EX_V2_SUB_STREAM, 140 } VDEC_EX_V2_Stream; 141 142 /// decoder event enumerator. 143 typedef enum 144 { 145 /// turn off all event 146 E_VDEC_E_V2_EVENT_OFF = 0x00, 147 /// display one frame/field 148 E_VDEC_EX_V2_EVENT_DISP_ONE = VDEC_EX_V2_BIT(0), 149 /// repeat one frame/field 150 E_VDEC_EX_V2_EVENT_DISP_REPEAT = VDEC_EX_V2_BIT(1), 151 /// one CC data should be displayed 152 E_VDEC_EX_V2_EVENT_DISP_WITH_CC = VDEC_EX_V2_BIT(2), 153 /// decode one frame 154 E_VDEC_EX_V2_EVENT_DEC_ONE = VDEC_EX_V2_BIT(3), 155 /// decode one I frame 156 E_VDEC_EX_V2_EVENT_DEC_I = VDEC_EX_V2_BIT(4), 157 /// decode error 158 E_VDEC_EX_V2_EVENT_DEC_ERR = VDEC_EX_V2_BIT(5), 159 /// display information is changed 160 E_VDEC_EX_V2_EVENT_DISP_INFO_CHG = VDEC_EX_V2_BIT(6), 161 /// find user data 162 E_VDEC_EX_V2_EVENT_USER_DATA_FOUND = VDEC_EX_V2_BIT(7), 163 /// display information ready after be changed 164 E_VDEC_EX_V2_EVENT_DISP_INFO_RDY = VDEC_EX_V2_BIT(8), 165 /// first frame decoded 166 E_VDEC_EX_V2_EVENT_FIRST_FRAME = VDEC_EX_V2_BIT(9), 167 /// first picture found 168 E_VDEC_EX_V2_EVENT_PIC_FOUND = VDEC_EX_V2_BIT(10), 169 /// video is ready to display (no garbage and avsync done) 170 E_VDEC_EX_V2_EVENT_VIDEO_UNMUTE = VDEC_EX_V2_BIT(11), 171 /// new sequence header found 172 E_VDEC_EX_V2_EVENT_SEQ_HDR_FOUND = VDEC_EX_V2_BIT(12), 173 /// active format description found 174 E_VDEC_EX_V2_EVENT_AFD_FOUND = VDEC_EX_V2_BIT(13), 175 // ES data invalid 176 E_VDEC_EX_V2_EVENT_ES_DATA_ERR = VDEC_EX_V2_BIT(14), 177 178 } VDEC_EX_V2_EventFlag; 179 180 //define VDEC CB type 181 typedef enum 182 { 183 E_VDEC_EX_V2_CB_MAIN = 0, 184 E_VDEC_EX_V2_CB_SUB, 185 } VDEC_EX_V2_CB_TYPE; 186 187 /// codec type enumerator 188 typedef enum 189 { 190 ///unsupported codec type 191 E_VDEC_EX_V2_CODEC_TYPE_NONE = 0, 192 ///MPEG 1/2 193 E_VDEC_EX_V2_CODEC_TYPE_MPEG2, 194 ///H263 (short video header) 195 E_VDEC_EX_V2_CODEC_TYPE_H263, 196 ///MPEG4 (default) 197 E_VDEC_EX_V2_CODEC_TYPE_MPEG4, 198 ///MPEG4 (Divx311) 199 E_VDEC_EX_V2_CODEC_TYPE_DIVX311, 200 ///MPEG4 (Divx412) 201 E_VDEC_EX_V2_CODEC_TYPE_DIVX412, 202 ///FLV 203 E_VDEC_EX_V2_CODEC_TYPE_FLV, 204 ///VC1 advanced profile (VC1) 205 E_VDEC_EX_V2_CODEC_TYPE_VC1_ADV, 206 ///VC1 main profile (RCV) 207 E_VDEC_EX_V2_CODEC_TYPE_VC1_MAIN, 208 ///Real Video version 8 209 E_VDEC_EX_V2_CODEC_TYPE_RV8, 210 ///Real Video version 9 and 10 211 E_VDEC_EX_V2_CODEC_TYPE_RV9, 212 ///H264 213 E_VDEC_EX_V2_CODEC_TYPE_H264, 214 ///AVS 215 E_VDEC_EX_V2_CODEC_TYPE_AVS, 216 ///MJPEG 217 E_VDEC_EX_V2_CODEC_TYPE_MJPEG, 218 ///MVC 219 E_VDEC_EX_V2_CODEC_TYPE_MVC, 220 ///VP8 221 E_VDEC_EX_V2_CODEC_TYPE_VP8, 222 E_VDEC_EX_V2_CODEC_TYPE_NUM 223 } VDEC_EX_V2_CodecType; 224 225 /// input source select enumerator 226 typedef enum 227 { 228 ///DTV mode 229 E_VDEC_EX_V2_SRC_MODE_DTV = 0, 230 ///TS file mode 231 E_VDEC_EX_V2_SRC_MODE_TS_FILE, 232 ///generic file mode 233 E_VDEC_EX_V2_SRC_MODE_FILE, 234 /// TS file and dual ES buffer mode 235 E_VDEC_EX_V2_SRC_MODE_TS_FILE_DUAL_ES, 236 ///generic file and dual ES buffer mode 237 E_VDEC_EX_V2_SRC_MODE_FILE_DUAL_ES, 238 } VDEC_EX_V2_SrcMode; 239 240 /// function return enumerator 241 typedef enum 242 { 243 ///failed 244 E_VDEC_EX_V2_FAIL = 0, 245 ///success 246 E_VDEC_EX_V2_OK, 247 ///invalid parameter 248 E_VDEC_EX_V2_RET_INVALID_PARAM, 249 ///access not allow 250 E_VDEC_EX_V2_RET_ILLEGAL_ACCESS, 251 ///hardware abnormal 252 E_VDEC_EX_V2_RET_HARDWARE_BREAKDOWN, 253 ///unsupported 254 E_VDEC_EX_V2_RET_UNSUPPORTED, 255 ///timeout 256 E_VDEC_EX_V2_RET_TIMEOUT, 257 ///not ready 258 E_VDEC_EX_V2_RET_NOT_READY, 259 ///not initial 260 E_VDEC_EX_V2_RET_NOT_INIT, 261 ///not exit after last initialization 262 E_VDEC_EX_V2_RET_NOT_EXIT, 263 ///not running, counter does not change 264 E_VDEC_EX_V2_RET_NOT_RUNNING, 265 ///max value 266 E_VDEC_EX_V2_RET_NUM, 267 } VDEC_EX_V2_Result; 268 269 /// Action enumerator of display commands 270 typedef enum 271 { 272 /// Action- display frame 273 E_VDEC_EX_V2_DISP_ACTION_DISPLAY = 1, 274 /// Action - release frame 275 E_VDEC_EX_V2_DISP_ACTION_RELEASE, 276 } VDEC_EX_V2_DispCmdAction; 277 278 /// Freeze picture select after flush decoder 279 typedef enum 280 { 281 /// Freeze at current display picture 282 E_VDEC_EX_V2_FREEZE_AT_CUR_PIC = 1, 283 /// freeze at the latest decode picture 284 E_VDEC_EX_V2_FREEZE_AT_LAST_PIC, 285 } VDEC_EX_V2_FreezePicSelect; 286 287 /// error code enumerator 288 typedef enum 289 { 290 E_VDEC_EX_V2_ERR_CODE_BASE = 0x01000000, 291 E_VDEC_EX_V2_ERR_CODE_NOT_SUPPORT, 292 E_VDEC_EX_V2_ERR_CODE_ILLEGAL_ACCESS, 293 E_VDEC_EX_V2_ERR_CODE_FRMRATE_NOT_SUPPORT, 294 E_VDEC_EX_V2_ERR_CODE_DIVX_PLUS_UNSUPPORTED, 295 296 E_VDEC_EX_V2_MVD_ERR_CODE_BASE = 0x02000000, 297 E_VDEC_EX_V2_MVD_ERR_CODE_SHAPE, 298 E_VDEC_EX_V2_MVD_ERR_CODE_USED_SPRITE, 299 E_VDEC_EX_V2_MVD_ERR_CODE_NOT_8_BIT, //error_status : bits per pixel 300 E_VDEC_EX_V2_MVD_ERR_CODE_NERPRED_ENABLE, 301 E_VDEC_EX_V2_MVD_ERR_CODE_REDUCED_RES_ENABLE, 302 E_VDEC_EX_V2_MVD_ERR_CODE_SCALABILITY, 303 E_VDEC_EX_V2_MVD_ERR_CODE_OTHER, 304 E_VDEC_EX_V2_MVD_ERR_CODE_H263_ERROR, 305 E_VDEC_EX_V2_MVD_ERR_CODE_RES_NOT_SUPPORT, //error_status : none 306 E_VDEC_EX_V2_MVD_ERR_CODE_MPEG4_NOT_SUPPORT, //error_status : none 307 E_VDEC_EX_V2_MVD_ERR_CODE_VC1_NOT_SUPPORT, //error_status : none 308 E_VDEC_EX_V2_MVD_ERR_CODE_RCV_ERROR_OCCUR, 309 310 E_VDEC_EX_V2_HVD_ERR_CODE_BASE = 0x03000000, 311 E_VDEC_EX_V2_HVD_ERR_CODE_GENERAL_BASE = (0x0000|E_VDEC_EX_HVD_ERR_CODE_BASE), 312 E_VDEC_EX_V2_HVD_ERR_CODE_OUT_OF_SPEC , 313 E_VDEC_EX_V2_HVD_ERR_CODE_UNKNOW_ERR, 314 E_VDEC_EX_V2_HVD_ERR_CODE_HW_BREAK_DOWN, 315 E_VDEC_EX_V2_HVD_ERR_CODE_HW_DEC_TIMEOUT, 316 E_VDEC_EX_V2_HVD_ERR_CODE_OUT_OF_MEMORY, 317 E_VDEC_EX_V2_HVD_ERR_CODE_UNKNOWN_CODEC, 318 // AVC 319 E_VDEC_EX_V2_HVD_ERR_CODE_AVC_BASE = (0x1000|E_VDEC_EX_HVD_ERR_CODE_BASE), 320 E_VDEC_EX_V2_HVD_ERR_CODE_AVC_SPS_BROKEN, 321 E_VDEC_EX_V2_HVD_ERR_CODE_AVC_SPS_NOT_IN_SPEC, 322 E_VDEC_EX_V2_HVD_ERR_CODE_AVC_SPS_NOT_ENOUGH_FRM, // DPB size at specified level is smaller than the specified number of reference frames. This is not allowed 323 E_VDEC_EX_V2_HVD_ERR_CODE_AVC_PPS_BROKEN, // PPS is not valid 324 E_VDEC_EX_V2_HVD_ERR_CODE_AVC_REF_LIST, 325 E_VDEC_EX_V2_HVD_ERR_CODE_AVC_NO_REF, 326 E_VDEC_EX_V2_HVD_ERR_CODE_AVC_RES, // out of supported resolution 327 // AVS 328 E_VDEC_EX_V2_HVD_ERR_CODE_AVS_BASE = (0x2000|E_VDEC_EX_HVD_ERR_CODE_BASE), 329 E_VDEC_EX_V2_HVD_ERR_CODE_AVS_RES, // out of supported resolution 330 // RM 331 E_VDEC_EX_V2_HVD_ERR_CODE_RM_BASE = (0x3000|E_VDEC_EX_HVD_ERR_CODE_BASE), 332 E_VDEC_EX_V2_HVD_ERR_CODE_RM_PACKET_HEADER, 333 E_VDEC_EX_V2_HVD_ERR_CODE_RM_FRAME_HEADER, 334 E_VDEC_EX_V2_HVD_ERR_CODE_RM_SLICE_HEADER, 335 E_VDEC_EX_V2_HVD_ERR_CODE_RM_BYTE_CNT, 336 E_VDEC_EX_V2_HVD_ERR_CODE_RM_DISP_TIMEOUT, 337 E_VDEC_EX_V2_HVD_ERR_CODE_RM_NO_REF, 338 E_VDEC_EX_V2_HVD_ERR_CODE_RM_RES, // out of supported resolution 339 E_VDEC_EX_V2_HVD_ERR_CODE_RM_VLC, 340 E_VDEC_EX_V2_HVD_ERR_CODE_RM_SIZE_OUT_FB_LAYOUT, 341 342 E_VDEC_EX_V2_RVD_ERR_CODE_BASE = 0x04000000, 343 E_VDEC_EX_V2_RVD_ERR_CODE_PACKET_HEADER, ///< packet header version error 344 E_VDEC_EX_V2_RVD_ERR_CODE_FRAME_HEADER, ///< frame type error 345 E_VDEC_EX_V2_RVD_ERR_CODE_SLICE_HEADER, ///<slice header error 346 E_VDEC_EX_V2_RVD_ERR_CODE_DECODE_TIMEOUT,///< decode MB timeout 347 E_VDEC_EX_V2_RVD_ERR_CODE_OUT_OF_MEMORY, ///< frame buffer is out of memory 348 E_VDEC_EX_V2_RVD_ERR_CODE_BYTE_POS, ///< can not find in ID table 349 E_VDEC_EX_V2_RVD_ERR_CODE_DISPLAY_TIMEOUT, 350 351 E_VDEC_EX_V2_MJPEG_ERR_CODE_BASE = 0x05000000, 352 E_VDEC_EX_V2_HVD_ERR_CODE_MJPEG_RES, 353 } VDEC_EX_V2_ErrCode; 354 355 /// frame rate conversion mode enumerator 356 typedef enum 357 { 358 /// disable FRC mode. 359 E_VDEC_EX_V2_FRC_NORMAL = 0, 360 /// output rate is twice of input rate (ex. 30p to 60p) 361 E_VDEC_EX_V2_FRC_DISP_TWICE, 362 /// 3:2 pulldown mode (ex. 24p to 60i or 60p) 363 E_VDEC_EX_V2_FRC_3_2_PULLDOWN, 364 /// PAL to NTSC conversion (50i to 60i) 365 E_VDEC_EX_V2_FRC_PAL_TO_NTSC, 366 /// NTSC to PAL conversion (60i to 50i) 367 E_VDEC_EX_V2_FRC_NTSC_TO_PAL, 368 /// output rate 50P ->60P 369 E_VDEC_EX_V2_FRC_MODE_50P_60P, 370 /// output rate 60P ->50P 371 E_VDEC_EX_V2_FRC_MODE_60P_50P, 372 } VDEC_EX_V2_FrcMode; 373 374 /// trick decode mode enumerator 375 typedef enum 376 { 377 /// decode all frame 378 E_VDEC_EX_V2_TRICK_DEC_ALL = 0, 379 /// decode all except of non-reference frame 380 E_VDEC_EX_V2_TRICK_DEC_IP, 381 /// only decode I frame 382 E_VDEC_EX_V2_TRICK_DEC_I, 383 E_VDEC_EX_V2_TRICK_DEC_NUM 384 } VDEC_EX_V2_TrickDec; 385 386 /// display speed setting enumerator 387 typedef enum 388 { 389 /// default speed type 390 E_VDEC_EX_V2_SPEED_DEFAULT = 0, 391 /// fast display 392 E_VDEC_EX_V2_SPEED_FAST, 393 /// slow display 394 E_VDEC_EX_V2_SPEED_SLOW, 395 } VDEC_EX_V2_SpeedType; 396 397 /// The display speed enumerator 398 typedef enum 399 { 400 /// Normal display speed. 401 E_VDEC_EX_V2_DISP_SPEED_1X = 1, 402 /// 2X 403 E_VDEC_EX_V2_DISP_SPEED_2X = 2, 404 /// 4X 405 E_VDEC_EX_V2_DISP_SPEED_4X = 4, 406 /// 8X 407 E_VDEC_EX_V2_DISP_SPEED_8X = 8, 408 /// 16X 409 E_VDEC_EX_V2_DISP_SPEED_16X = 16, 410 /// 32X 411 E_VDEC_EX_V2_DISP_SPEED_32X = 32, 412 } VDEC_EX_V2_DispSpeed; 413 414 /// motion JPEG down scale factor enumerator 415 typedef enum 416 { 417 ///original size 418 E_VDEC_EX_V2_MJPEG_SCALE_1to1 = 0, 419 ///down scale to 1/2 420 E_VDEC_EX_V2_MJPEG_SCALE_2to1, 421 ///down scale to 1/4 422 E_VDEC_EX_V2_MJPEG_SCALE_4to1, 423 ///down scale to 1/8 424 E_VDEC_EX_V2_MJPEG_SCALE_8to1, 425 } VDEC_EX_V2_MJpegScaleFactor; 426 427 /// timestamp type of command queue 428 typedef enum 429 { 430 ///without timestamp information 431 E_VDEC_EX_V2_TIME_STAMP_NONE = 0, 432 ///PTS (Presentation Time Stamp) 433 E_VDEC_EX_V2_TIME_STAMP_PTS, 434 ///DTS (Decode Time Stamp) 435 E_VDEC_EX_V2_TIME_STAMP_DTS, 436 ///STS (Sorted Time Stamp) 437 E_VDEC_EX_V2_TIME_STAMP_STS, 438 } VDEC_EX_V2_TimeStampType; 439 440 /// The debug level of VDEC 441 typedef enum 442 { 443 /// disable all uart message. 444 E_VDEC_EX_V2_DBG_LEVEL_NONE = 0, 445 /// Only output error message 446 E_VDEC_EX_V2_DBG_LEVEL_ERR, 447 /// output general message, and above. 448 E_VDEC_EX_V2_DBG_LEVEL_INFO, 449 /// output debug message, and above. 450 E_VDEC_EX_V2_DBG_LEVEL_DBG, 451 /// output function tracing message, and above. 452 E_VDEC_EX_V2_DBG_LEVEL_TRACE, 453 /// output FW message. 454 E_VDEC_EX_V2_DBG_LEVEL_FW, 455 } VDEC_EX_V2_DbgLevel; 456 457 /// Type of FW source 458 typedef enum 459 { 460 E_VDEC_EX_V2_FW_SOURCE_NONE, 461 E_VDEC_EX_V2_FW_SOURCE_DRAM, 462 E_VDEC_EX_V2_FW_SOURCE_FLASH, 463 }VDEC_EX_V2_FWSourceType; 464 465 /// Format of CC (Closed Caption) 466 typedef enum 467 { 468 E_VDEC_EX_V2_CC_NONE = 0x00, 469 E_VDEC_EX_V2_CC_608 = 0x01, //For CC608 or 157 470 E_VDEC_EX_V2_CC_708 = 0x02, //For CC708 471 E_VDEC_EX_V2_CC_UNPACKED = 0x03, 472 } VDEC_EX_V2_CCFormat; 473 474 /// Type of CC 475 typedef enum 476 { 477 E_VDEC_EX_V2_CC_TYPE_NONE = 0, 478 E_VDEC_EX_V2_CC_TYPE_NTSC_FIELD1 = 1, 479 E_VDEC_EX_V2_CC_TYPE_NTSC_FIELD2 = 2, 480 E_VDEC_EX_V2_CC_TYPE_DTVCC = 3, 481 E_VDEC_EX_V2_CC_TYPE_NTSC_TWOFIELD = 4, 482 } VDEC_EX_V2_CCType; 483 484 typedef enum 485 { 486 E_VDEC_EX_V2_CC_GET_BUFF_START = 0x1, 487 E_VDEC_EX_V2_CC_GET_BUFF_SIZE, 488 E_VDEC_EX_V2_CC_GET_708_ENABLE 489 } VDEC_EX_V2_CCInfoCmd; 490 491 typedef enum 492 { 493 E_VDEC_EX_V2_STAGE_STOP = 0, 494 E_VDEC_EX_V2_STAGE_INIT, 495 E_VDEC_EX_V2_STAGE_PLAY, 496 E_VDEC_EX_V2_STAGE_PAUSE, 497 } VDEC_EX_V2_Stage; 498 499 typedef enum 500 { 501 /// Used before MApi_VDEC_EX_Flush(). 502 E_VDEC_EX_V2_PATTERN_FLUSH = 0, 503 /// Used after MApi_VDEC_EX_EnableLastFrameShow(). 504 E_VDEC_EX_V2_PATTERN_FILEEND, 505 }VDEC_EX_V2_PatternType; 506 507 typedef struct 508 { 509 MS_BOOL bInit; 510 MS_BOOL bIdle; 511 VDEC_EX_V2_Stage eStage; 512 } VDEC_EX_V2_Status; 513 514 typedef struct 515 { 516 MS_U32 u32Tmp; 517 } VDEC_EX_V2_Info; 518 519 typedef enum 520 { 521 E_VDEC_EX_V2_FRM_TYPE_I = 0, 522 E_VDEC_EX_V2_FRM_TYPE_P, 523 E_VDEC_EX_V2_FRM_TYPE_B, 524 E_VDEC_EX_V2_FRM_TYPE_OTHER, 525 E_VDEC_EX_V2_FRM_TYPE_NUM 526 } VDEC_EX_V2_FrameType; 527 528 typedef enum 529 { 530 ///< no field. 531 E_VDEC_EX_V2_FIELDTYPE_NONE, 532 ///< Top field only. 533 E_VDEC_EX_V2_FIELDTYPE_TOP, 534 ///< Bottom field only. 535 E_VDEC_EX_V2_FIELDTYPE_BOTTOM, 536 ///< Both fields. 537 E_VDEC_EX_V2_FIELDTYPE_BOTH, 538 E_VDEC_EX_V2_FIELDTYPE_NUM 539 } VDEC_EX_V2_FieldType; 540 541 typedef enum 542 { 543 E_VDEC_EX_V2_PATTERN_BEFORE_FRM = 0, 544 E_VDEC_EX_V2_PATTERN_AFTER_FRM, 545 E_VDEC_EX_V2_PATTERN_SKIP_DATA, 546 } VDEC_EX_V2_PatchPattern; 547 548 typedef enum 549 { 550 E_VDEC_EX_V2_PIC_STRUCTURE_RSV = 0, //reserved 551 E_VDEC_EX_V2_PIC_STRUCTURE_TOP, 552 E_VDEC_EX_V2_PIC_STRUCTURE_BOT, 553 E_VDEC_EX_V2_PIC_STRCUTURE_FRM, 554 } VDEC_EX_V2_PicStructure; 555 556 //VDEC FB reduction type 557 typedef enum 558 { 559 VDEC_EX_V2_FB_REDUCTION_NONE = 0, 560 VDEC_EX_V2_FB_REDUCTION_1_2, 561 VDEC_EX_V2_FB_REDUCTION_1_4 562 } VDEC_EX_V2_FBReductionType; 563 564 //VDEC set debug mode 565 typedef enum 566 { 567 E_VDEC_EX_V2_DBG_MODE_BYPASS_INSERT_START_CODE = 0, /// for UT 568 E_VDEC_EX_V2_DBG_MODE_BYPASS_DIVX_MC_PATCH, /// for UT 569 E_VDEC_EX_V2_DBG_MODE_NUM 570 } VDEC_EX_V2_DbgMode; 571 572 //VDEC set clock speed 573 typedef enum 574 { 575 E_VDEC_EX_V2_CLOCK_SPEED_NONE = 0, 576 E_VDEC_EX_V2_CLOCK_SPEED_HIGHEST, 577 E_VDEC_EX_V2_CLOCK_SPEED_HIGH, 578 E_VDEC_EX_V2_CLOCK_SPEED_MEDIUM, 579 E_VDEC_EX_V2_CLOCK_SPEED_LOW, 580 E_VDEC_EX_V2_CLOCK_SPEED_LOWEST, 581 E_VDEC_EX_V2_CLOCK_SPEED_DEFAULT, 582 } VDEC_EX_V2_ClockSpeed; 583 584 //VDEC FW TYPE 585 typedef enum 586 { 587 E_VDEC_EX_V2_FW_TYPE_MVD = 0, 588 E_VDEC_EX_V2_FW_TYPE_HVD, 589 } VDEC_EX_V2_FwType; 590 591 /// DecodeMode for f/w tasks 592 typedef enum 593 { 594 E_VDEC_EX_V2_DEC_MODE_DUAL_INDIE = 0, ///< Two independent tasks 595 E_VDEC_EX_V2_DEC_MODE_DUAL_3D, ///< Two dependent tasks for 3D 596 E_VDEC_EX_V2_DEC_MODE_SINGLE, ///< One task use the whole SRAM 597 E_VDEC_EX_V2_DEC_MODE_MVC = E_VDEC_EX_DEC_MODE_SINGLE, 598 } VDEC_EX_V2_DEC_MODE; 599 600 601 /// argument of DecodeMode structure for f/w tasks 602 typedef enum 603 { 604 //Group1:Set Korea3DTV mode 605 E_VDEC_EX_V2_DEC_KR3D_MODE_BASE = 0x0000, 606 E_VDEC_EX_V2_DEC_KR3D_INTERLACE_MODE = E_VDEC_EX_DEC_KR3D_MODE_BASE, 607 E_VDEC_EX_V2_DEC_KR3D_FORCE_P_MODE, 608 E_VDEC_EX_V2_DEC_KR3D_INTERLACE_TWO_PITCH, 609 E_VDEC_EX_V2_DEC_KR3D_FORCE_P_TWO_PITCH, 610 611 //Group2:Set PIP mode 612 E_VDEC_EX_V2_DEC_PIP_MODE_BASE = 0x1000, 613 E_VDEC_EX_V2_DEC_PIP_SYNC_INDIE = E_VDEC_EX_DEC_PIP_MODE_BASE, 614 E_VDEC_EX_V2_DEC_PIP_SYNC_MAIN_STC, 615 E_VDEC_EX_V2_DEC_PIP_SYNC_SWITCH 616 } VDEC_EX_V2_DEC_MODE_ARG; 617 618 typedef enum 619 { 620 E_VDEC_EX_V2_DIU_DRAM = 0, //MCU mode 621 E_VDEC_EX_V2_DIU_HVD = 1, 622 E_VDEC_EX_V2_DIU_MVD = 2, 623 E_VDEC_EX_V2_DIU_HVD_3DLR = 3, //MVC 624 E_VDEC_EX_V2_DIU_MVD_3DLR = 4, //Korea3D, WMV3D 625 E_VDEC_EX_V2_DIU_UNKNOWN = -1 626 } VDEC_EX_V2_DIU; 627 628 typedef enum 629 { 630 E_VDEC_EX_V2_CMD_GET_FREE_STREAM_ID, 631 E_VDEC_EX_V2_CMD_INIT, 632 E_VDEC_EX_V2_CMD_SET_CONTROL, 633 E_VDEC_EX_V2_CMD_GET_CONTROL, 634 E_VDEC_EX_V2_CMD_PRE_SET_CONTROL, 635 E_VDEC_EX_V2_CMD_POST_SET_CONTROL, 636 E_VDEC_EX_V2_CMD_NUM, 637 E_VDEC_EX_V2_CMD_MAX = E_VDEC_EX_V2_CMD_NUM, 638 } E_VDEC_EX_V2_IOCTL_CMD; 639 640 //VDEC user command id 641 typedef enum 642 { 643 //Group1:Set Control command================================ 644 E_VDEC_EX_V2_USER_CMD_SET_CONTROL_BASE = 0x0000, 645 E_VDEC_EX_V2_USER_CMD_REPEAT_LAST_FIELD, // Param: 1(ON), 0(OFF) 646 E_VDEC_EX_V2_USER_CMD_AVSYNC_REPEAT_TH, // Param:0x01 ~ 0xFF(repeat times), 0xFF:always repeat when av is not sync 647 E_VDEC_EX_V2_USER_CMD_DISP_ONE_FIELD, // Param: 1(ON), 0(OFF) 648 E_VDEC_EX_V2_USER_CMD_FD_MASK_DELAY_COUNT, // Param: unit is in vsync base for mute the fd_mask 649 E_VDEC_EX_V2_USER_CMD_FRC_OUTPUT, // Param: the address of VDEC_FRC_OutputParam 650 E_VDEC_EX_V2_USER_CMD_FRC_DROP_TYPE, // Param: 1(FRC_DROP_FIELD), 0(FRC_DROP_FRAME), default:0 651 E_VDEC_EX_V2_USER_CMD_FAST_DISPLAY, // Param: TRUE(Fast display), FALSE(Display until synced) 652 E_VDEC_EX_V2_USER_CMD_IGNORE_ERR_REF, // Param: TRUE(Ignore error reference), FALSE(Enable error reference handle) 653 E_VDEC_EX_V2_USER_CMD_FORCE_FOLLOW_DTV_SPEC, // Param: 1(ON), 0(OFF) 654 E_VDEC_EX_V2_USER_CMD_AVC_MIN_FRM_GAP, // Param: Set the theshold of H264 frame gap, 0xFFFFFFFF don't care frame gap 655 E_VDEC_EX_V2_USER_CMD_DISABLE_SEQ_CHG, // Param: 1(Disable), 0(Enable) 656 E_VDEC_EX_V2_USER_CMD_SET_DISP_OUTSIDE_CTRL_MODE, // Param: 1(ON) used for Openmax, 0(OFF) used for mstreamer and mm mode ,default : off 657 E_VDEC_EX_V2_USER_CMD_SET_DTV_USER_DATA_MODE, // Param: 0(Support normal DVB CC, default case), 1(Support ATSC DirectTV CC), 2,3,4(Reserved) 658 E_VDEC_EX_V2_USER_CMD_SET_SINGLE_TASK_MODE, 659 E_VDEC_EX_V2_USER_CMD_AVC_DISABLE_ANTI_VDEAD, 660 E_VDEC_EX_V2_USER_CMD_DTV_RESET_MVD_PARSER, // Param: 0(Disable), 1(Enable) 661 E_VDEC_EX_V2_USER_CMD_PVR_FLUSH_FRAME_BUFFER, 662 E_VDEC_EX_V2_USER_CMD_FORCE_INTERLACE_MODE, 663 E_VDEC_EX_V2_USER_CMD_RELEASE_FD_MASK, // Param: 1 to release fd mask when zooming or slow motion 664 E_VDEC_EX_V2_USER_CMD_NULL, // E_VDEC_EX_USER_CMD_SET_DECODE_MODE 665 E_VDEC_EX_V2_USER_CMD_SUPPORT_AVC_TO_MVC, // Param: 0(Do not support), 1(Support AVC to MVC) 666 E_VDEC_EX_V2_USER_CMD_3DLR_VIEW_EXCHANGE, // Param: 0(Disable), 1(View L/R exhange) 667 E_VDEC_EX_V2_USER_CMD_SET_VSIZE_ALIGN, // Param: 0(Disable), 1(Enable) 668 E_VDEC_EX_V2_USER_CMD_SHOW_DECODE_ORDER, // Param: 0(Disable), 1(Enable) 669 E_VDEC_EX_V2_USER_CMD_AVC_DISP_IGNORE_CROP, // Param: 0(Disable), 1(Enable) 670 E_VDEC_EX_V2_USER_CMD_SET_DISP_FINISH_MODE, 671 E_VDEC_EX_V2_USER_CMD_SET_AVSYNC_MODE, 672 E_VDEC_EX_V2_USER_CMD_SUSPEND_DYNAMIC_SCALE, // Param: 0(Disable, non-suspend DS), 1(Enable, suspend DS) 673 E_VDEC_EX_V2_USER_CMD_FORCE_AUTO_MUTE, 674 E_VDEC_EX_V2_USER_CMD_AVC_NEW_SLOW_MOTION, // Param: 0(Disable), 1(Enable) 675 E_VDEC_EX_V2_USER_CMD_PUSH_DISPQ_WITH_REF_NUM, // Param: 0(Disable), 1(Enable) 676 E_VDEC_EX_V2_USER_CMD_DS_RESV_N_BUFFER, // Param: 0(Disable), 1(Enable) 677 E_VDEC_EX_V2_USER_CMD_RM_ENABLE_PTS_TBL, // Param: 0(Disable), 1(Enable) 678 E_VDEC_EX_V2_USER_CMD_FLUSH_PTS_BUF, 679 E_VDEC_EX_V2_USER_CMD_SET_IDCT_MODE, // Param: 0(Original), 1(new IDCT) 680 E_VDEC_EX_V2_USER_CMD_DROP_ERR_FRAME, // Param: 0(Disable), 1(Enable) 681 E_VDEC_EX_V2_USER_CMD_SET_CC608_INFO_ENHANCE_MODE, 682 E_VDEC_EX_V2_USER_CMD_IGNORE_PIC_OVERRUN, // Param: 0(Disable), 1(Enable) 683 E_VDEC_EX_V2_USER_CMD_SET_SELF_SEQCHANGE, 684 E_VDEC_EX_V2_USER_CMD_AUTO_EXHAUST_ES_MODE, // Param: set the upper bound (arg[31:16]), and lower bound (arg[15:0])of ES level, Unit = 1KBytes, Auto drop display to consume ES data as soon as possible when ES level is higher than upper bound 685 E_VDEC_EX_V2_USER_CMD_CTL_SPEED_IN_DISP_ONLY, // Param: 0(Original: Dec and disp time), 1(In Disp only) 686 E_VDEC_EX_V2_USER_CMD_AVC_SUPPORT_REF_NUM_OVER_MAX_DPB_SIZE, // Param: 0(Disable), 1(Enable) 687 E_VDEC_EX_V2_USER_CMD_RETURN_INVALID_AFD, // Param: 0(Disable), 1(Enable) 688 E_VDEC_EX_V2_USER_CMD_FIELD_POLARITY_DISPLAY_ONE_FIELD,// Param : VDEC_EX_V2_Field_Polarity 689 E_VDEC_EX_V2_USER_CMD_AVC_FORCE_BROKEN_BY_US, // Param: 0(Disable), 1(Enable) 690 E_VDEC_EX_V2_USER_CMD_SHOW_FIRST_FRAME_DIRECT, // Param: 0(Disable), 1(Enable), Push first frame to display queue directly.. 691 E_VDEC_EX_V2_USER_CMD_AVC_RESIZE_DOS_DISP_PEND_BUF, // Param: size of AVC display pending buffer for display outside mode 692 E_VDEC_EX_V2_USER_CMD_SET_XC_LOW_DELAY_PARA, // Param: arg0 for diff_field_number... 693 E_VDEC_EX_V2_USER_CMD_SET_SECURE_MODE, // Param: use enum VDEC_EX_SecureMode 694 E_VDEC_EX_V2_USER_CMD_RVU_SETTING_MODE, // Param: 0(Disable), 1(drop B-frame and force IDR) 695 E_VDEC_EX_V2_USER_CMD_FRAMERATE_HANDLING, // Arg 0~60000, 0: Disable, 1000 ~ 60000: Used the arg to set frame rate when the sequence did not have frame rate info. and arg is not zero. (The frame unit is (arg/1000)fps, Exp: 30000 = 30.000 fps), others: Do not thing. 696 E_VDEC_EX_V2_USER_CMD_DUAL_NON_BLOCK_MODE, // Param: 0(Disable), 1(Enable) 697 E_VDEC_EX_V2_USER_CMD_IGNORE_PIC_STRUCT_DISPLAY, // Param: 0(Disable), 1(Enable) Ignore Pic_struct when display progressive frame. 698 E_VDEC_EX_V2_USER_CMD_INPUT_PTS_FREERUN_MODE, // Param: 0(Disable), 1(Enable) Video free run when the difference between input PTS and current STC is large than E_HVD_CMD_FREERUN_THRESHOLD + 1s; 699 E_VDEC_EX_V2_USER_CMD_ERR_CONCEAL_SLICE_1ST_MB, // Param: 0(disable), Error concealment from current/last MB position; 1(enale) Error concealment from current slice first MB.(Need enable E_HVD_CMD_ERR_CONCEAL) 700 E_VDEC_EX_V2_USER_CMD_SET_EXTERNAL_DS_BUFFER, // Param: External DS Buffer info. 701 E_VDEC_EX_V2_USER_CMD_SET_MIN_TSP_DATA_SIZE, // Param: Resize HVD_FW_AVC_ES_MIN_TSP_DATA_SIZE 702 E_VDEC_EX_V2_USER_CMD_SET_DMX_FRAMERATE, 703 E_VDEC_EX_V2_USER_CMD_SET_DMX_FRAMERATEBASE, 704 E_VDEC_EX_V2_USER_CMD_ENABLE_CC_608_EXTERNAL_BUFFER, // Param: u32_ccinfo 32bits-->([31:8]+[7:0] = addr+size), addr is kb unit, if u32_ccinfo ==0, it will turn off this feature 705 E_VDEC_EX_V2_USER_CMD_ENABLE_CC_708_EXTERNAL_BUFFER, // Param: u32_ccinfo 32bits-->([31:8]+[7:0] = addr+size), addr is kb unit, if u32_ccinfo ==0, it will turn off this feature 706 E_VDEC_EX_V2_USER_CMD_SET_TIME_INC_PREDICT_PARA, 707 E_VDEC_EX_V2_USER_CMD_ENABLE_DECODE_ENGINE_TIMEOUT, // Param: Enable/Disable decode timeout solution, timeout value unit:ms (VDEC_EX_Decode_Timeout_Param) 708 E_VDEC_EX_V2_USER_CMD_AUTO_FREE_ES, // Param: 0(Disable), 1(Enable) 709 E_VDEC_EX_V2_USER_CMD_FRAMEBUFFER_AUTO_MODE, //Param: 0(Disable),1(Enable), this cmd is used for MVD. 710 E_VDEC_EX_V2_USER_CMD_SET_SMOOTH_REWIND, //enable/disable or support smooth rewind 711 E_VDEC_EX_V2_USER_CMD_SET_ERROR_TOLERANCE, // Param: VDEC_EX_Err_Tolerance; bEnable: enable or disable; u8Tolerance: err_rate(0%~100%) 712 E_VDEC_EX_V2_USER_CMD_AUTO_DROP_DISPLAY_QUEUE, // Param: 0(Disable), N = 1~16: Drop display queue when display queue above than N frames. 713 E_VDEC_EX_V2_USER_CMD_USE_CPB_REMOVAL_DEALY, // Param: 0(Disable), 1(Enable) 714 E_VDEC_EX_V2_USER_CMD_SKIP_N_FRAME, // Param: 0:disable, N = 1~63. Skip N frame. 715 E_VDEC_EX_V2_USER_CMD_SET_PTS_US_MODE, //Param: 1(enable), 0(disable ) PTS output by micro second level, 716 E_VDEC_EX_V2_USER_CMD_AUTO_INSERT_DUMMY_DATA, //Param: 1(enable),0(disable), Enable/Disable utopia auto insert dummy pattern in SLQ/BBU mode. 717 E_VDEC_EX_V2_USER_CMD_DROP_ONE_PTS, 718 E_VDEC_EX_V2_USER_CMD_PVR_TIMESHIFT_SEAMLESS_MODE, 719 E_VDEC_EX_V2_USER_CMD_AUTO_REDUCE_ES_DATA, 720 E_VDEC_EX_V2_USER_CMD_RM_FORCE_MCU_MODE_ES, // Param: 0(Disable), 1(Enable) 721 E_VDEC_EX_V2_USER_CMD_FORCE_PROGRESSIVE_MODE, // Param: 1(enable),0(disable), Enable/Disable force progressive mode 722 E_VDEC_EX_V2_USER_CMD_SET_FRAMEBUFF2, // Param[0]=Addr and Param[1]=size for the second frame buffer 723 724 E_VDEC_EX_V2_USER_CMD_EXIT, 725 E_VDEC_EX_V2_USER_CMD_RST, 726 E_VDEC_EX_V2_USER_CMD_CHECK_DISPINFO_READY, 727 E_VDEC_EX_V2_USER_CMD_SET_FRC_MODE, 728 E_VDEC_EX_V2_USER_CMD_SET_DYNSCALING_PARAMS, 729 E_VDEC_EX_V2_USER_CMD_SET_DBG_LEVEL, 730 E_VDEC_EX_V2_USER_CMD_PLAY, 731 E_VDEC_EX_V2_USER_CMD_PAUSE, 732 E_VDEC_EX_V2_USER_CMD_RESUME, 733 E_VDEC_EX_V2_USER_CMD_STEP_DISP, 734 E_VDEC_EX_V2_USER_CMD_STEP_DECODE, 735 E_VDEC_EX_V2_USER_CMD_SET_TRICK_MODE, 736 E_VDEC_EX_V2_USER_CMD_PUSH_DECQ, 737 E_VDEC_EX_V2_USER_CMD_FLUSH, 738 E_VDEC_EX_V2_USER_CMD_ENABLE_LAST_FRAME_SHOW, 739 E_VDEC_EX_V2_USER_CMD_SET_SPEED, 740 E_VDEC_EX_V2_USER_CMD_SET_FREEZE_DISP, 741 E_VDEC_EX_V2_USER_CMD_SET_BLUE_SCREEN, 742 E_VDEC_EX_V2_USER_CMD_RESET_PTS, 743 E_VDEC_EX_V2_USER_CMD_AVSYNC_ON, 744 E_VDEC_EX_V2_USER_CMD_AVSYNC_FREERUN_THRESHOLD, 745 E_VDEC_EX_V2_USER_CMD_SET_EVENT_MULTICALLBACK, 746 E_VDEC_EX_V2_USER_CMD_UNSET_EVENT_MULTICALLBACK, 747 E_VDEC_EX_V2_USER_CMD_FIRE_DEC, 748 E_VDEC_EX_V2_USER_CMD_SEEK_TO_PTS, 749 E_VDEC_EX_V2_USER_CMD_SKIP_TO_PTS, 750 E_VDEC_EX_V2_USER_CMD_DISABLE_DEBLOCKING, 751 E_VDEC_EX_V2_USER_CMD_DISABLE_QUARTER_PIXEL, 752 E_VDEC_EX_V2_USER_CMD_SET_AUTO_RM_LST_ZERO_BYTE, 753 E_VDEC_EX_V2_USER_CMD_SET_BALANCE_BW, 754 E_VDEC_EX_V2_USER_CMD_GEN_PATTERN, 755 E_VDEC_EX_V2_USER_CMD_MHEG_DECODE_IFRAME, 756 E_VDEC_EX_V2_USER_CMD_MHEG_RST_IFRAME_DEC, 757 E_VDEC_EX_V2_USER_CMD_CC_START_PARSING, 758 E_VDEC_EX_V2_USER_CMD_CC_STOP_PARSING, 759 E_VDEC_EX_V2_USER_CMD_CC_UPDATE_READ_PTR, 760 E_VDEC_EX_V2_USER_CMD_SET_BLOCK_DISPLAY, 761 E_VDEC_EX_V2_USER_CMD_ENABLE_ES_BUFF_MALLOC, 762 E_VDEC_EX_V2_USER_CMD_DISPLAY_FRAME, 763 E_VDEC_EX_V2_USER_CMD_RELEASE_FRAME, 764 E_VDEC_EX_V2_USER_CMD_CAPTURE_FRAME, 765 E_VDEC_EX_V2_USER_CMD_CC_INIT, 766 E_VDEC_EX_V2_USER_CMD_CC_SET_CFG, 767 E_VDEC_EX_V2_USER_CMD_CC_SET_BUFF_START_ADDR, 768 E_VDEC_EX_V2_USER_CMD_CC_UPDATE_WRITE_ADDR, 769 E_VDEC_EX_V2_USER_CMD_CC_UPDATE_READ_ADDR, 770 E_VDEC_EX_V2_USER_CMD_CC_DISABLE_PARSING, 771 772 773 E_VDEC_EX_V2_USER_CMD_MVC_SET_CMD_BASE = 0x0800, 774 E_VDEC_EX_V2_USER_CMD_MVC_BBU2_PUSH_PACKET, // Param: Packet Info. 775 E_VDEC_EX_V2_USER_CMD_MVC_BBU2_FIRE_DECCMD, // Param: Non 776 777 E_VDEC_EX_V2_USER_CMD_UT_SET_CMD_BASE = 0x0900, 778 E_VDEC_EX_V2_USER_CMD_UT_SET_DBG_MODE, // Param: for enable the specify dbg mode for UT 779 E_VDEC_EX_V2_USER_CMD_UT_CLR_DBG_MODE, // Param: for disable the specify dbg mode for UT 780 781 //Group2:Get Control command================================ 782 E_VDEC_EX_V2_USER_CMD_GET_CONTROL_BASE = 0x1000, 783 E_VDEC_EX_V2_USER_CMD_GET_CHROMA_TYPE, 784 E_VDEC_EX_V2_USER_CMD_GET_REAL_FRAMERATE, // Get Real FrameRate reported by decoder 785 E_VDEC_EX_V2_USER_CMD_GET_COLOR_MATRIX, // Get color matrix coefficients reported by decoder 786 E_VDEC_EX_V2_USER_CMD_GET_MAIN_STREAM_ID, // Get activated main stream ID 787 E_VDEC_EX_V2_USER_CMD_GET_SUB_STREAM_ID, // Get activated sub stream ID 788 E_VDEC_EX_V2_USER_CMD_GET_DYNSCALE_ENABLED, 789 E_VDEC_EX_V2_USER_CMD_GET_FPA_SEI, //Get SEI info 790 E_VDEC_EX_V2_USER_CMD_GET_U64PTS, 791 E_VDEC_EX_V2_USER_CMD_GET_ORI_INTERLACE_MODE, 792 E_VDEC_EX_V2_USER_CMD_GET_MBS_ONLY_FLAG, 793 E_VDEC_EX_V2_USER_CMD_GET_CRC_VALUE, //Get frame Y/UV crc value 794 E_VDEC_EX_V2_USER_CMD_GET_BBU_Q_NUM, 795 E_VDEC_EX_V2_USER_CMD_GET_DISP_FRAME_NUM, 796 E_VDEC_EX_V2_USER_CMD_GET_FPA_SEI_EX, //Get SEI info(enhancement) 797 E_VDEC_EX_V2_USER_CMD_GET_ES_BUFFER_STATUS, //Get ES buffer over/under flow status 798 E_VDEC_EX_V2_USER_CMD_GET_CODEC_TYPE, // Get Codec type 799 E_VDEC_EX_V2_USER_CMD_GET_SHAREMEMORY_BASE, 800 E_VDEC_EX_V2_USER_CMD_GET_IS_LEAST_DISPQ_SIZE_FLAG, 801 E_VDEC_EX_V2_USER_CMD_GET_FIELD_PIC_FLAG, // Param: Get Field Pic Flag 802 E_VDEC_EX_V2_USER_CMD_GET_SUPPORT_2ND_MVOP_INTERFACE, // Param: TRUE : support, FALSE : not support 803 E_VDEC_EX_V2_USER_CMD_GET_FB_USAGE_MEM, // Get FrameBuufer Size needed by decoder 804 E_VDEC_EX_V2_USER_CMD_GET_XC_LOW_DELAY_INT_STATE, // Get xc_low_delay int state... 805 E_VDEC_EX_V2_USER_CMD_GET_VSYNC_BRIDGE_ADDR, 806 E_VDEC_EX_V2_USER_CMD_GET_FRAME_INFO_EX, 807 E_VDEC_EX_V2_USER_CMD_GET_FLUSH_PATTEN_ENTRY_NUM, 808 E_VDEC_EX_V2_USER_CMD_GET_DS_BUF_MIU_SEL, //For those chips which has 3 MIU, use this get control to get correct miu select of DS buffer 809 E_VDEC_EX_V2_USER_CMD_GET_FW_STATUS_FLAG, 810 E_VDEC_EX_V2_USER_CMD_GET_HW_MAX_PIXEL, 811 E_VDEC_EX_V2_USER_CMD_GET_FLOW_CONTROL_U64PTS_DIFF, // based on PTS table Rdptr and Wrptr, support TSP mode only 812 E_VDEC_EX_V2_USER_CMD_GET_NEXT_DISP_FRAME_INFO_EXT, //replace of E_VDEC_EX_USER_CMD_GET_FRAME_INFO_EX 813 E_VDEC_EX_V2_USER_CMD_GET_VSYNC_BRIDGE_EXT_ADDR, //get vsync bridge ext addr 814 815 E_VDEC_EX_V2_USER_CMD_GET_STATUS, 816 E_VDEC_EX_V2_USER_CMD_CHECK_DISPINFORDY, 817 E_VDEC_EX_V2_USER_CMD_IS_STEP_DISP_DONE, 818 E_VDEC_EX_V2_USER_CMD_IS_STEP_DECODE_DONE, 819 E_VDEC_EX_V2_USER_CMD_GET_DISP_INFO, 820 E_VDEC_EX_V2_USER_CMD_IS_AVSYNC_ON, 821 E_VDEC_EX_V2_USER_CMD_IS_WITH_VALID_STREAM, 822 E_VDEC_EX_V2_USER_CMD_IS_DISP_FINISH, 823 E_VDEC_EX_V2_USER_CMD_IS_IFRAME_FOUND, 824 E_VDEC_EX_V2_USER_CMD_IS_SEQ_CHG, 825 E_VDEC_EX_V2_USER_CMD_IS_REACH_SYNC, 826 E_VDEC_EX_V2_USER_CMD_IS_START_SYNC, 827 E_VDEC_EX_V2_USER_CMD_IS_FREERUN, 828 E_VDEC_EX_V2_USER_CMD_IS_WITH_LOW_DELAY, 829 E_VDEC_EX_V2_USER_CMD_IS_ALL_BUFFER_EMPTY, 830 E_VDEC_EX_V2_USER_CMD_GET_EXT_DISP_INFO, 831 E_VDEC_EX_V2_USER_CMD_GET_DEC_FRAME_INFO, 832 E_VDEC_EX_V2_USER_CMD_GET_DISP_FRAME_INFO, 833 E_VDEC_EX_V2_USER_CMD_GET_DEC_TIMECODE, 834 E_VDEC_EX_V2_USER_CMD_GET_DISP_TIMECODE, 835 E_VDEC_EX_V2_USER_CMD_GET_EVENT_INFO, 836 E_VDEC_EX_V2_USER_CMD_GET_ACTIVE_FORMAT, 837 E_VDEC_EX_V2_USER_CMD_GET_COLOUR_PRIMARIES, 838 E_VDEC_EX_V2_USER_CMD_GET_FW_VERSION, 839 E_VDEC_EX_V2_USER_CMD_GET_GOP_CNT, 840 E_VDEC_EX_V2_USER_CMD_GET_ES_WRITE_PTR, 841 E_VDEC_EX_V2_USER_CMD_GET_ES_READ_PTR, 842 E_VDEC_EX_V2_USER_CMD_GET_PTS, 843 E_VDEC_EX_V2_USER_CMD_GET_NEXT_PTS, 844 E_VDEC_EX_V2_USER_CMD_GET_VIDEO_PTS_STC_DELTA, 845 E_VDEC_EX_V2_USER_CMD_GET_ERR_CODE, 846 E_VDEC_EX_V2_USER_CMD_GET_ERR_CNT, 847 E_VDEC_EX_V2_USER_CMD_GET_BITRATE, 848 E_VDEC_EX_V2_USER_CMD_GET_FRAME_CNT, 849 E_VDEC_EX_V2_USER_CMD_GET_SKIP_CNT, 850 E_VDEC_EX_V2_USER_CMD_GET_DROP_CNT, 851 E_VDEC_EX_V2_USER_CMD_GET_DISP_CNT, 852 E_VDEC_EX_V2_USER_CMD_GET_DECQ_VACANCY, 853 E_VDEC_EX_V2_USER_CMD_IS_32_PULLDOWN, 854 E_VDEC_EX_V2_USER_CMD_IS_ALIVE, 855 E_VDEC_EX_V2_USER_CMD_IS_CC_AVAILABLE, 856 E_VDEC_EX_V2_USER_CMD_GET_CC_INFO, 857 E_VDEC_EX_V2_USER_CMD_GET_TRICK_MODE, 858 E_VDEC_EX_V2_USER_CMD_GET_ACTIVE_CODEC_TYPE, 859 E_VDEC_EX_V2_USER_CMD_GET_PATTERN_LEAST_LENGTH, 860 E_VDEC_EX_V2_USER_CMD_MHEG_IS_IFRAME_DECODING, 861 E_VDEC_EX_V2_USER_CMD_CC_GET_WRITE_PTR, 862 E_VDEC_EX_V2_USER_CMD_CC_GET_READ_PTR, 863 E_VDEC_EX_V2_USER_CMD_CC_GET_IS_OVERFLOW, 864 E_VDEC_EX_V2_USER_CMD_GET_HW_KEY, 865 E_VDEC_EX_V2_USER_CMD_GET_ES_BUFF_VACANCY, 866 E_VDEC_EX_V2_USER_CMD_GET_ES_BUFF, 867 E_VDEC_EX_V2_USER_CMD_GET_NEXT_DISP_FRAME, 868 E_VDEC_EX_V2_USER_CMD_CC_GET_INFO, 869 E_VDEC_EX_V2_USER_CMD_CC_GET_IS_RST_DONE, 870 E_VDEC_EX_V2_USER_CMD_CC_GET_IS_BUFF_OVERFLOW, 871 E_VDEC_EX_V2_USER_CMD_CC_GET_WRITE_ADDR, 872 E_VDEC_EX_V2_USER_CMD_CC_GET_READ_ADDR, 873 E_VDEC_EX_V2_USER_CMD_GETLIBVER, 874 E_VDEC_EX_V2_USER_CMD_GETINFO, 875 E_VDEC_EX_V2_USER_CMD_CHECKCAPS, 876 E_VDEC_EX_V2_USER_CMD_IS_FRAME_RDY, 877 E_VDEC_EX_V2_USER_CMD_GET_DCV_SEI, 878 E_VDEC_EX_V2_USER_CMD_GET_VUI_DISP_INFO, 879 880 881 E_VDEC_EX_V2_USER_CMD_MVC_GET_CMD_BASE = 0x1800, 882 E_VDEC_EX_V2_USER_CMD_GET_MVC_SUB_FRAME_DISP_INFO, // Param: VDEC_FrameInfo pointer. 883 E_VDEC_EX_V2_USER_CMD_GET_MVC_BBU2_DECQ_VACANCY, // Param: BBU2 Dec Q Vacancy. 884 E_VDEC_EX_V2_USER_CMD_GET_MVC_ES2_READ_PTR, // Param: ES2 read pointer. 885 E_VDEC_EX_V2_USER_CMD_GET_MVC_ES2_WRITE_PTR, // Param: ES2 Write pointer. 886 E_VDEC_EX_V2_USER_CMD_GET_ES_QUANTITY, // Param: Get ES buffer Level. 887 E_VDEC_EX_V2_USER_CMD_GET_ES2_QUANTITY, // Param: Get ES2 buffer Level. 888 889 //Group3:Preset Control command====================== 890 //Group3-1:Common system Preset Control command 891 E_VDEC_EX_V2_USER_CMD_SYSTEM_PRESET_CONTROL_BASE = 0x2000, 892 E_VDEC_EX_V2_USER_CMD_SYSTEM_PRESET_VPU_CLOCK, //Param: VDEC_EX_ClockSpeed 893 894 //Group3-2:HVD System Preset Control command 895 E_VDEC_EX_V2_USER_CMD_SYSTEM_PRESET_HVD_BASE = 0x2100, 896 E_VDEC_EX_V2_USER_CMD_SYSTEM_PRESET_HVD_CLOCK, //Param: VDEC_EX_ClockSpeed 897 898 //Group3-3:MVD System Preset Control command 899 E_VDEC_EX_V2_USER_CMD_SYSTEM_PRESET_MVD_BASE = 0x2200, 900 E_VDEC_EX_V2_USER_CMD_SYSTEM_PRESET_MVD_CLOCK, //Param: VDEC_EX_ClockSpeed 901 E_VDEC_EX_V2_USER_CMD_VPU_SECURITY_MODE, //Param: 0:disable,1:enable 902 E_VDEC_EX_V2_USER_CMD_PRESET_DECODE_MODE, 903 E_VDEC_EX_V2_USER_CMD_PRESET_ENABLETURBOMODE, 904 E_VDEC_EX_V2_USER_CMD_PRESETSINGLEDECODE, 905 E_VDEC_EX_V2_USER_CMD_PREGETSTATUS, 906 E_VDEC_EX_V2_USER_CMD_SETPOWERSTATE, 907 908 909 //Group3-4:Preset Control command============================= 910 E_VDEC_EX_V2_USER_CMD_PRESET_CONTROL_BASE = 0x2300, 911 E_VDEC_EX_V2_USER_CMD_HVD_ONE_PENDING_BUFFER_MODE, //Param: 0(Disable), 1(Enable), use only one pending buffer instead of two for HVD 912 E_VDEC_EX_V2_USER_CMD_MVD_HWBUFFER_REMAPPING_MODE, //Param: 0(Disable), 1(Enable),Allcate HW buffer to start of frame buffer 913 E_VDEC_EX_V2_USER_CMD_SET_SHAREMEMORY_BASE, 914 E_VDEC_EX_V2_USER_CMD_HVD_COL_BBU_MODE, //Param: HVD use colocated BBU mode, 0: disable, 1: enable /*johnny.ko*/ 915 E_VDEC_EX_V2_USER_CMD_HVD_IAPGN_BUF_SHARE_BW_MODE, //Param: HVD IAP GN Buffer address, 0xFFFFFFFF means disable 916 /***/E_VDEC_EX_V2_USER_CMD_DTV_DEBUG_MODE, 917 E_VDEC_EX_V2_USER_CMD_HVD_TS_IN_BBU_MODE, 918 E_VDEC_EX_V2_USER_CMD_AUTO_ARRANGE_FRAMEBUFFER_USAGE, //Param: 0:disable,1:enable, address:PA,size:unit is byte 919 E_VDEC_EX_V2_USER_CMD_THUMBNAIL_MODE, //Param: 0(Disable), 1(Enable), use small frame buffer to decdoe thumbnail 920 E_VDEC_EX_V2_USER_CMD_FORCE_8BIT_DEC_MODE, //Param: force 8bit decode mode, 0: disable, 1: enable 921 E_VDEC_EX_V2_USER_CMD_MFCODEC_MODE, 922 E_VDEC_EX_V2_USER_CMD_VDEC_FEATURE, //AP control VDEC features 923 E_VDEC_EX_V2_USER_CMD_DYNAMIC_CMA_MODE, //enable dynamic cma features 924 //Group4:Postset Control command====================== 925 E_VDEC_EX_V2_USER_CMD_SYSTEM_POSTSET_CONTROL_BASE = 0x3000, 926 E_VDEC_EX_V2_USER_CMD_SYSTEM_POSTSET_CLEAR_PROCESS_RELATED, 927 928 } VDEC_EX_V2_User_Cmd; 929 //------------------------------------------------------------------------------------------------- 930 // Structure for Upper layer 931 //------------------------------------------------------------------------------------------------- 932 typedef struct 933 { 934 MS_U32 u32Version; 935 MS_U32 u32Id; 936 } VDEC_EX_V2_StreamId; 937 938 typedef struct 939 { 940 VDEC_EX_V2_StreamId* StreamID; 941 VDEC_EX_V2_User_Cmd eUserCmd; 942 void* param[8]; // at most 8 param 943 void* pRet; 944 }VDEC_EX_V2_IO_Param; 945 946 typedef struct 947 { 948 VDEC_EX_V2_Stream eStream; 949 VDEC_EX_V2_CodecType eCodecType; 950 } VDEC_EX_V2_CodecInfo; 951 952 /// Configurations of f/w decode mode 953 typedef struct 954 { 955 VDEC_EX_V2_DEC_MODE eDecMod; 956 VDEC_EX_V2_CodecInfo pstCodecInfo[VDEC_EX_V2_MAX_DEC_NUM]; 957 MS_U8 u8CodecCnt; 958 MS_U8 u8ArgSize; 959 MS_U32 u32Arg; //ref VDEC_EX_DEC_MODE_ARG enum 960 } VDEC_EX_V2_DecModCfg; 961 962 typedef struct 963 { 964 MS_BOOL bEnable; // 0 : disable , 1:enable 965 MS_U8 u8DisplayTop; // 0: display top, 1: display bottom 966 }VDEC_EX_V2_Field_Polarity; 967 968 typedef struct 969 { 970 MS_U32 u32version; 971 MS_U32 u32size; 972 } VDEC_EX_V2_VerCtl; 973 974 /// Data structure of CC Configuration 975 typedef struct 976 { 977 VDEC_EX_V2_CCFormat eFormat; 978 VDEC_EX_V2_CCType eType; 979 MS_VIRT u32BufStAdd; 980 MS_U32 u32BufSize; 981 } VDEC_EX_V2_CCCfg; 982 983 /// information for display setting 984 typedef struct 985 { 986 ///bitstream horizontal size 987 MS_U16 u16HorSize; 988 ///bitstream vertical size 989 MS_U16 u16VerSize; 990 ///frame rate 991 MS_U32 u32FrameRate; 992 ///interlace flag 993 MS_U8 u8Interlace; 994 ///active frame code 995 MS_U8 u8AFD; 996 ///Sample aspect rate width 997 MS_U16 u16SarWidth; 998 ///Sample aspect rate height 999 MS_U16 u16SarHeight; 1000 ///right cropping 1001 MS_U16 u16CropRight; 1002 ///left cropping 1003 MS_U16 u16CropLeft; 1004 ///bottom cropping 1005 MS_U16 u16CropBottom; 1006 ///top cropping 1007 MS_U16 u16CropTop; 1008 ///pitch 1009 MS_U16 u16Pitch; 1010 ///interval of PTS 1011 MS_U16 u16PTSInterval; 1012 ///MPEG1 flag 1013 MS_U8 u8MPEG1; 1014 ///play mode (fixme) 1015 MS_U8 u8PlayMode; 1016 ///FRC mode 1017 MS_U8 u8FrcMode; 1018 ///aspect ratio code 1019 MS_U8 u8AspectRate; 1020 ///if FALSE, set VOP as mono mode (only for H264) 1021 MS_BOOL bWithChroma; 1022 /// if true, color space is xvYCC (Y from 16 to 235 and Cb , Cr from 16 to 240). 1023 /// if false, color space is BT.601/709 (Y from 0 to 255 and Cb , Cr from 0 to 255). 1024 /// only MPEG might be with BT.601/709 1025 MS_BOOL bColorInXVYCC; 1026 ///Dynamic scaling buffer address 1027 MS_VIRT u32DynScalingAddr; 1028 ///Dynamic scaling buffer size 1029 MS_U32 u32DynScalingSize; 1030 ///Dynamic scaling depth 1031 MS_U8 u8DynScalingDepth; 1032 ///Dynamic scaling DS buffer on miu1 or miu0 1033 MS_BOOL bEnableMIUSel; 1034 ///Display width 1035 MS_U32 u32AspectWidth; 1036 ///Display height 1037 MS_U32 u32AspectHeight; 1038 } VDEC_EX_V2_DispInfo; 1039 1040 /// system configuration 1041 typedef struct 1042 { 1043 ///FW binary start address 1044 MS_PHY u32FWBinaryAddr; 1045 ///FW binary size 1046 MS_U32 u32FWBinarySize; 1047 ///FW code buffer start address 1048 MS_PHY u32CodeBufAddr; 1049 ///FW code buffer size 1050 MS_U32 u32CodeBufSize; 1051 ///frame buffer start address 1052 MS_PHY u32FrameBufAddr; 1053 ///frame buffer size 1054 MS_U32 u32FrameBufSize; 1055 ///bitstream buffer start address 1056 MS_PHY u32BitstreamBufAddr; 1057 ///bitstream buffer size 1058 MS_U32 u32BitstreamBufSize; 1059 ///driver process buffer start address 1060 MS_PHY u32DrvProcBufAddr; 1061 ///driver process buffer size 1062 MS_U32 u32DrvProcBufSize; 1063 ///vlc table Binary address (RM only) 1064 MS_PHY u32VlcBinarySrcAddr; 1065 ///vld table Binary size 1066 MS_U32 u32VlcTabBinarySize; 1067 ///debug level setting 1068 VDEC_EX_V2_DbgLevel eDbgMsgLevel; 1069 ///debug level setting 1070 VDEC_EX_V2_FWSourceType eFWSourceType; 1071 } VDEC_EX_V2_SysCfg; 1072 1073 /// video information 1074 typedef struct 1075 { 1076 ///input source mode 1077 VDEC_EX_V2_SrcMode eSrcMode; 1078 /// timestamp type of command queue 1079 VDEC_EX_V2_TimeStampType eTimeStampType; 1080 ///MJPEG scale factor 1081 VDEC_EX_V2_MJpegScaleFactor eMJpegScaleFactor; 1082 /// should be TRUE when codec type is H264 and container is MKV and MP4(MOV) 1083 MS_BOOL bWithoutNalStCode; 1084 /// needness when CodecType is MJPEG and divx311 1085 //MS_U16 u16FrameRate; 1086 MS_U32 u32FrameRate; 1087 MS_U32 u32FrameRateBase; 1088 /// if divx311; use u16Width[0]; only need other elements when RV8 1089 MS_U16 u16Width[8]; 1090 /// if divx311; use u16Height[0]; only need other elements when RV8 1091 MS_U16 u16Height[8]; 1092 /// video number sizes (for RM) 1093 MS_U16 u16NumSizes; 1094 } VDEC_EX_V2_VideoInfo; 1095 1096 /// frame information 1097 typedef struct 1098 { 1099 /// frame buffer base + the start offset of current displayed luma data. Unit: byte. 1100 MS_PHY u32LumaAddr; 1101 /// frame buffer base + the start offset of current displayed chroma data. Unit: byte. 1102 MS_PHY u32ChromaAddr; 1103 /// Time stamp(DTS, PTS) of current displayed frame. Unit: ms (todo: 90khz) 1104 MS_U32 u32TimeStamp; 1105 /// low part of ID number 1106 MS_U32 u32ID_L; 1107 /// high part of ID number 1108 MS_U32 u32ID_H; 1109 /// pitch 1110 MS_U16 u16Pitch; 1111 /// width 1112 MS_U16 u16Width; 1113 /// hight 1114 MS_U16 u16Height; 1115 ///< Frame type: I, P, B frame 1116 VDEC_EX_V2_FrameType eFrameType; 1117 ///< Field type: Top, Bottom, Both 1118 VDEC_EX_V2_FieldType eFieldType; 1119 } VDEC_EX_V2_FrameInfo; 1120 1121 typedef struct 1122 { 1123 VDEC_EX_V2_FrameInfo sFrameInfo; 1124 1125 MS_PHY u32LumaAddr_2bit; 1126 MS_PHY u32ChromaAddr_2bit; 1127 MS_U8 u8LumaBitdepth; 1128 MS_U8 u8ChromaBitdepth; 1129 MS_U16 u16Pitch_2bit; 1130 1131 MS_U8 u8Reserved[64]; 1132 } VDEC_EX_V2_FrameInfoEX; 1133 1134 //Extension of frame info(VDEC_EX_FrameInfoEX) 1135 typedef struct 1136 { 1137 VDEC_EX_V2_VerCtl stVerCtl; /// version : 0, 1138 VDEC_EX_V2_FrameInfo sFrameInfo; 1139 MS_PHY u32LumaAddr_2bit; 1140 MS_PHY u32ChromaAddr_2bit; 1141 MS_PHY u32LumaAddrI; 1142 MS_PHY u32LumaAddrI_2bit; 1143 MS_PHY u32ChromaAddrI; 1144 MS_PHY u32ChromaAddrI_2bit; 1145 MS_U32 u32MFCodecInfo; 1146 MS_U32 u32LumaMFCbitlen; 1147 MS_U32 u32ChromaMFCbitlen; 1148 MS_U16 u16Pitch_2bit; 1149 MS_U8 u8LumaBitdepth; 1150 MS_U8 u8ChromaBitdepth; 1151 ////HVD_MasteringDisplayColourVolume// 1152 MS_U32 maxLuminance; 1153 MS_U32 minLuminance; 1154 MS_U16 primaries[3][2]; 1155 MS_U16 whitePoint[2]; 1156 MS_U8 Frm_Info_Ext_avail; ///bit[1]: SEI_Enabled, bit[0]: colur_description_present_flag 1157 ////colour_description//////////// 1158 MS_U8 colour_primaries; // u(8) 1159 MS_U8 transfer_characteristics; // u(8) 1160 MS_U8 matrix_coefficients; // u(8) 1161 } VDEC_EX_V2_FrameInfoExt; 1162 1163 typedef struct 1164 { 1165 MS_BOOL bUsed; 1166 MS_BOOL bColourVolumeSEIEnabled; 1167 MS_U32 u32MaxLuminance; 1168 MS_U32 u32MinLuminance; 1169 MS_U16 u16Primaries[3][2]; 1170 MS_U16 u16WhitePoint[2]; 1171 }VDEC_EX_V2_DisplayColourVolume_SEI; 1172 1173 typedef struct 1174 { 1175 VDEC_EX_V2_FrameInfoExt sFrameInfoExt; 1176 ////HVD_MasteringDisplayColourVolume// 1177 VDEC_EX_V2_DisplayColourVolume_SEI sDisplay_colour_volume; 1178 MS_U8 u8Frm_Info_Ext_avail; ///bit[1]: SEI_Enabled, bit[0]: colur_description_present_flag 1179 ////colour_description//////////// 1180 MS_U8 u8Colour_primaries; // u(8) 1181 MS_U8 u8Transfer_characteristics; // u(8) 1182 MS_U8 u8Matrix_coefficients; // u(8) 1183 } VDEC_EX_V2_FrameInfoExt_v2; 1184 1185 /// Extension display information 1186 typedef struct 1187 { 1188 /// vertical size from sequene_display_extension 1189 MS_U16 u16VSize; 1190 /// horizontal size from sequene_display_extension 1191 MS_U16 u16HSize; 1192 /// vertical offset from picture_display_extension 1193 MS_S16 s16VOffset; 1194 /// horizontal offset from picture_display_extension 1195 MS_S16 s16HOffset; 1196 } VDEC_EX_V2_ExtDispInfo; 1197 1198 /// display frame information 1199 typedef struct 1200 { 1201 ///< frame information 1202 VDEC_EX_V2_FrameInfo stFrmInfo; 1203 ///< firmware private data 1204 MS_U32 u32PriData; 1205 ///< index used by apiVDEC to manage VDEC_DispQ[][] 1206 MS_U32 u32Idx; 1207 } VDEC_EX_V2_DispFrame; 1208 1209 /// time code structure 1210 typedef struct 1211 { 1212 /// time_code_hours 1213 MS_U8 u8TimeCodeHr; 1214 /// time_code_minutes 1215 MS_U8 u8TimeCodeMin; 1216 /// time_code_seconds 1217 MS_U8 u8TimeCodeSec; 1218 /// time_code_pictures 1219 MS_U8 u8TimeCodePic; 1220 /// drop_frame_flag 1221 MS_U8 u8DropFrmFlag; 1222 /// reserved fields for 4-byte alignment 1223 MS_U8 u8Reserved[3]; 1224 } VDEC_EX_V2_TimeCode; 1225 1226 /// vdec frame buffer reduction 1227 typedef struct 1228 { 1229 VDEC_EX_V2_FBReductionType eLumaFBReduction; 1230 VDEC_EX_V2_FBReductionType eChromaFBReduction; 1231 MS_BOOL bEnableAutoMode; /// 0: Disable, 1: Enable 1232 } VDEC_EX_V2_FBReduction; 1233 1234 /// Initial parameter 1235 typedef struct 1236 { 1237 /// init param version : 0 1238 MS_U32 u32Version; 1239 /// codec type 1240 VDEC_EX_V2_CodecType eCodecType; 1241 /// system configuration 1242 VDEC_EX_V2_SysCfg SysConfig; 1243 /// video information from container 1244 VDEC_EX_V2_VideoInfo VideoInfo; 1245 /// dynamic scaling control bit 1246 MS_BOOL EnableDynaScale; 1247 /// switch for display decode error frame or not 1248 MS_BOOL bDisableDropErrFrame; 1249 /// switch for error concealment 1250 MS_BOOL bDisableErrConceal; 1251 /// enable repeat last field when repeat happened at interlace stream 1252 MS_BOOL bRepeatLastField; 1253 /// threshold to judge error frame 1254 MS_U8 u8ErrThreshold; 1255 /// dynamic scaling virtual box Width 1256 MS_U32 u32DSVirtualBoxWidth; 1257 /// dynamic scaling virtual box Height 1258 MS_U32 u32DSVirtualBoxHeight; 1259 /// vdec frame buffer reduction setting 1260 VDEC_EX_V2_FBReduction stFBReduction; 1261 } VDEC_EX_V2_InitParam; 1262 1263 /// Decode Command 1264 typedef struct 1265 { 1266 /// ID (high 4-bytes) 1267 MS_U32 u32ID_H; 1268 /// ID (low 4-bytes) 1269 MS_U32 u32ID_L; 1270 /// start address of payload 1271 MS_VIRT u32StAddr; 1272 /// size of payload 1273 MS_U32 u32Size; 1274 /// timestamp of payload 1275 MS_U32 u32Timestamp; 1276 } VDEC_EX_V2_DecCmd; 1277 1278 /// Display Command 1279 typedef struct 1280 { 1281 /// ID (high 4-bytes) 1282 MS_U32 u32ID_H; 1283 /// ID (low 4-bytes) 1284 MS_U32 u32ID_L; 1285 /// action of command 1286 VDEC_EX_V2_DispCmdAction eAction; 1287 } VDEC_EX_V2_DispCmd; 1288 1289 typedef struct 1290 { 1291 MS_U32 u32Version; 1292 /// top, bottom or frame 1293 VDEC_EX_V2_PicStructure u8PicStructure; 1294 MS_U8 u8TopFieldFirst; 1295 MS_U16 u16TempRef; 1296 MS_U32 u32Pts; 1297 /// address of cc data 1298 MS_U32 u32UserDataBuf; 1299 /// size of cc data 1300 MS_U32 u32UserDataSize; 1301 ///< Frame type: I, P, B frame 1302 VDEC_EX_V2_FrameType eFrameType; 1303 } VDEC_EX_V2_CC_Info; 1304 1305 ///CC input parameters for mstar proprietary CC library 1306 typedef struct 1307 { 1308 MS_U32 u32Ver; ///version of this structure 1309 MS_U32 u32Val; 1310 } VDEC_EX_V2_CC_InputPara; 1311 1312 typedef struct 1313 { 1314 MS_U32 u32OutputFrameRate; ///< output frame rate, unit:vsync count 1315 MS_U8 u8Interlace; ///< output scan:0:progress, 1:interlace 1316 } VDEC_EX_V2_FRC_OutputParam; 1317 1318 1319 typedef void (*VDEC_EX_V2_EventCb)(MS_U32 eFlag, void *param); 1320 1321 typedef struct 1322 { 1323 MS_U8 u8Frm_packing_arr_cnl_flag; 1324 MS_U8 u8Frm_packing_arr_type; 1325 MS_U8 u8content_interpretation_type; 1326 MS_U8 u1Quincunx_sampling_flag; 1327 1328 MS_U8 u1Spatial_flipping_flag; 1329 MS_U8 u1Frame0_flipping_flag; 1330 MS_U8 u1Field_views_flag; 1331 MS_U8 u1Current_frame_is_frame0_flag; 1332 1333 MS_U8 u1Frame0_self_contained_flag; 1334 MS_U8 u1Frame1_self_contained_flag; 1335 MS_U8 u4Frame0_grid_position_x; 1336 MS_U8 u4Frame0_grid_position_y; 1337 1338 MS_U8 u4Frame1_grid_position_x; 1339 MS_U8 u4Frame1_grid_position_y; 1340 MS_U8 u8Reserved01; 1341 MS_U8 u8Reserved02; 1342 }VDEC_EX_V2_Frame_packing_SEI; 1343 1344 typedef struct 1345 { 1346 VDEC_EX_V2_VerCtl stVerCtl; /// version : 0, 1347 /// size : sizeof(VDEC_EX_Frame_packing_SEI_EX) 1348 MS_BOOL bIsCropInfo; 1349 MS_BOOL bValid; 1350 MS_BOOL bUsed; 1351 MS_U8 u8Frm_packing_arr_cnl_flag; 1352 MS_U8 u8Frm_packing_arr_type; 1353 MS_U8 u8content_interpretation_type; 1354 MS_U8 u1Quincunx_sampling_flag; 1355 MS_U8 u1Spatial_flipping_flag; 1356 MS_U8 u1Frame0_flipping_flag; 1357 MS_U8 u1Field_views_flag; 1358 MS_U8 u1Current_frame_is_frame0_flag; 1359 MS_U8 u1Frame0_self_contained_flag; 1360 MS_U8 u1Frame1_self_contained_flag; 1361 MS_U8 u4Frame0_grid_position_x; 1362 MS_U8 u4Frame0_grid_position_y; 1363 MS_U8 u4Frame1_grid_position_x; 1364 MS_U8 u4Frame1_grid_position_y; 1365 MS_U32 u32DataBuff; 1366 MS_U32 u32DataSize; 1367 MS_U32 left; 1368 MS_U32 right; 1369 MS_U32 top; 1370 MS_U32 bottom; 1371 } VDEC_EX_V2_Frame_packing_SEI_EX; 1372 1373 typedef struct 1374 { 1375 MS_BOOL bAspect_ratio_info_present_flag; // u(1) 1376 MS_U8 u8Aspect_ratio_idc; // u(8) 1377 MS_U16 u16Sar_width; // u(16) 1378 MS_U16 u16Sar_height; // u(16) 1379 MS_BOOL bOverscan_info_present_flag; // u(1) 1380 MS_BOOL bOverscan_appropriate_flag; // u(1) 1381 MS_BOOL bVideo_signal_type_present_flag; // u(1) 1382 MS_U8 u8Video_format; // u(3) 1383 MS_BOOL bVideo_full_range_flag; // u(1) 1384 MS_BOOL bColour_description_present_flag; // u(1) 1385 MS_U8 u8Colour_primaries; // u(8) 1386 MS_U8 u8Transfer_characteristics; // u(8) 1387 MS_U8 u8Matrix_coefficients; // u(8) 1388 MS_BOOL bChroma_location_info_present_flag; // u(1) 1389 MS_U8 u8Chroma_sample_loc_type_top_field; // ue(v) 0~5 1390 MS_U8 u8Chroma_sample_loc_type_bottom_field; // ue(v) 0~5 1391 MS_BOOL bTiming_info_present_flag; // u(1) 1392 MS_BOOL bFixed_frame_rate_flag; // u(1) 1393 MS_U32 u32Num_units_in_tick; // u(32) 1394 MS_U32 u32Time_scale; // u(32) 1395 } VDEC_EX_V2_AVC_VUI_DISP_INFO; 1396 1397 //CRC value 1398 typedef struct 1399 { 1400 MS_U32 u32HorSize; 1401 MS_U32 u32VerSize; 1402 MS_U32 u32Strip; 1403 MS_VIRT u32LumaStartAddr; 1404 MS_VIRT u32ChromaStartAddr; 1405 }VDEC_EX_V2_CrcIn; 1406 1407 typedef struct 1408 { 1409 MS_U32 u32LumaCRC; 1410 MS_U32 u32ChromaCRC; 1411 }VDEC_EX_V2_CrcOut; 1412 1413 typedef struct 1414 { 1415 VDEC_EX_V2_CrcIn stCrcIn; 1416 VDEC_EX_V2_CrcOut stCrcOut; 1417 }VDEC_EX_V2_CrcValue; 1418 1419 //------------------------------------------------------------------------------------------------- 1420 // Function pointer for Upper layer 1421 //------------------------------------------------------------------------------------------------- 1422 1423 //------------------------------------------------------------------------------------------------- 1424 // API for Upper layer 1425 //------------------------------------------------------------------------------------------------- 1426 1427 void VDEC_EX_V2_RegisterToUtopia(FUtopiaOpen ModuleType); 1428 MS_U32 VDEC_EX_V2_Open(void** ppInstance, const void* const pAttribute); 1429 MS_U32 VDEC_EX_V2_Close(void* pInstance); 1430 MS_U32 VDEC_EX_V2_IOctl(void* pInstance, MS_U32 u32Cmd, void* pArgs); 1431 1432 #ifdef __cplusplus 1433 } 1434 #endif 1435 1436 #endif 1437 #undef _VDEC_EX_V2_H_ 1438 #endif //_VDEC_EX_V2_H_ 1439