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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// @file apiPNL.h 98 /// @brief Panel Interface 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 /*! \defgroup PNL_MODULE Panel Module 103 104 PNL is used for: 105 106 - 1.Set panel parameters base on different panel type,include VOP, MOD setting 107 - 2.change panel types . 108 - Ex:VBY1 switch from 2,4,8 lanes. 109 110 <b> Operation Code Flow: </b> \n 111 check flow chart directly. 112 \image html apiPNL.png 113 114 *! \defgroup PNL_INTERFACE_INIT Panel Init Control Interface 115 * \ingroup PNL_MODULE 116 117 *! \defgroup PNL_INTERFACE_FEATURE Panel Feature Operations Interface 118 * \ingroup PNL_MODULE 119 120 *! \defgroup PNL_INTERFACE_INFO Panel Infomation Pool Interface 121 * \ingroup PNL_MODULE 122 123 *! \defgroup PNL_INTERFACE_ToBeModified Panel APIs-to-be-modified Interface 124 * \ingroup PNL_MODULE 125 126 *! \defgroup PNL_INTERFACE_ToBeRemove Panel APIs-to-be-removed Interface 127 * \ingroup PNL_MODULE 128 */ 129 130 131 #ifndef _API_XC_PANEL_H_ 132 #define _API_XC_PANEL_H_ 133 134 #include "MsDevice.h" 135 #include "MsVersion.h" 136 137 #ifdef __cplusplus 138 extern "C" { 139 #endif 140 141 #ifdef _API_XC_PANEL_C_ 142 #define INTERFACE 143 #else 144 #define INTERFACE extern 145 #endif 146 147 //------------------------------------------------------------------------------------------------- 148 // Macro and Define 149 //------------------------------------------------------------------------------------------------- 150 151 //------------------------------------------------------------------------------------------------- 152 // This macro defined in mscommon.h originally, here just for avoid SN compile error 153 //------------------------------------------------------------------------------------------------- 154 #ifndef SYMBOL_WEAK 155 #define SYMBOL_WEAK __attribute__((weak)) 156 #endif 157 158 #ifndef _MS_VERSION_H_ 159 #define MSIF_TAG {'M','S','I','F'} // MSIF 160 #define MSIF_CLASS {'0','0'} // DRV/API (DDI) 161 #define MSIF_CUS 0x0000 // MStar Common library 162 #define MSIF_MOD 0x0000 // MStar Common library 163 #define MSIF_CHIP 0x000B 164 #define MSIF_CPU '0' 165 #define MSIF_OS '2' 166 #endif 167 168 // library information 169 #define MSIF_PNL_LIB_CODE {'P','N','L','_'} 170 #define MSIF_PNL_LIBVER {'0','3'} 171 #define MSIF_PNL_BUILDNUM {'5','2'} 172 #define MSIF_PNL_CHANGELIST {'0','0','6','1','4','4','7','7'} 173 174 #define PNL_API_VERSION /* Character String for DRV/API version */ \ 175 MSIF_TAG, /* 'MSIF' */ \ 176 MSIF_CLASS, /* '00' */ \ 177 MSIF_CUS, /* 0x0000 */ \ 178 MSIF_MOD, /* 0x0000 */ \ 179 MSIF_CHIP, \ 180 MSIF_CPU, \ 181 MSIF_PNL_LIB_CODE , /* IP__ */ \ 182 MSIF_PNL_LIBVER , /* 0.0 ~ Z.Z */ \ 183 MSIF_PNL_BUILDNUM , /* 00 ~ 99 */ \ 184 MSIF_PNL_CHANGELIST, /* CL# */ \ 185 MSIF_OS 186 187 /// ApiStatusEX version of current XC lib 188 #define API_PNLSTATUS_EX_VERSION 1 189 190 //---------------------------- 191 // Debug Switch 192 //---------------------------- 193 #define PNL_DBGLEVEL_OFF (0x0000) ///< turn off debug message, this is default setting 194 #define PNL_DBGLEVEL_INIT (0x0001) ///< Initial function 195 #define PNL_DBGLEVEL_PANEL_EN (0x0002) ///< panel enable function 196 #define PNL_DBGLEVEL_SSC (0x0004) ///< panel SSC setting 197 #define PNL_DBGLEVEL_GAMMA (0x0008) ///< gamma table setting 198 #define PNL_DBGLEVEL_CALIBRATION (0x0010) ///< mod calibration 199 200 //------------------------------------------------------------------------------------------------- 201 // Type and Structure 202 //------------------------------------------------------------------------------------------------- 203 /// Define return value of MApi_PNL 204 typedef enum 205 { 206 E_APIPNL_FAIL = 0, 207 E_APIPNL_OK = 1, 208 E_APIPNL_GET_BASEADDR_FAIL, ///< get base address failed when initialize panel driver 209 E_APIPNL_OBTAIN_MUTEX_FAIL, ///< obtain mutex timeout when calling this function 210 } APIPNL_Result; 211 212 /// Define aspect ratio 213 typedef enum 214 { 215 E_PNL_ASPECT_RATIO_4_3 = 0, ///< set aspect ratio to 4 : 3 216 E_PNL_ASPECT_RATIO_WIDE, ///< set aspect ratio to 16 : 9 217 E_PNL_ASPECT_RATIO_OTHER, ///< resvered for other aspect ratio other than 4:3/ 16:9 218 }E_PNL_ASPECT_RATIO; 219 220 /// Define the panel gamma precision type 221 typedef enum 222 { 223 E_APIPNL_GAMMA_10BIT = 0, ///< Gamma Type of 10bit 224 E_APIPNL_GAMMA_12BIT, ///< Gamma Type of 12bit 225 E_APIPNL_GAMMA_ALL ///< The library can support all mapping mode 226 } APIPNL_GAMMA_TYPE; 227 228 /// Define Gamma type 229 typedef enum 230 { 231 E_APIPNL_GAMMA_8BIT_MAPPING = 0, ///< mapping 1024 to 256 gamma entries 232 E_APIPNL_GAMMA_10BIT_MAPPING, ///< mapping 1024 to 1024 gamma entries 233 E_APIPNL_GAMMA_ALL_MAPPING ///< the library can map to any entries 234 } APIPNL_GAMMA_MAPPEING_MODE; ///< samping mode for GAMMA correction 235 236 /// Define The dimming control flag. when use with setter/getter, it will set/get MIN/MAX/Current value 237 typedef enum 238 { 239 E_APIPNL_DIMMING_MIN = 0, ///< Indicate to Get/Set Min Dimming value. 240 E_APIPNL_DIMMING_CURRENT , ///< Indicate to Get/Set Current Dimming value. 241 E_APIPNL_DIMMING_MAX , ///< Indicate to Get/Set Max Dimming value. 242 } APIPNL_DIMMING_CTRL; 243 244 /// Define PANEL Signaling Type 245 typedef enum 246 { 247 LINK_TTL, ///< TTL type 248 LINK_LVDS, ///< LVDS type 249 LINK_RSDS, ///< RSDS type 250 LINK_MINILVDS, ///< TCON 251 LINK_ANALOG_MINILVDS, ///< Analog TCON 252 LINK_DIGITAL_MINILVDS, ///< Digital TCON 253 LINK_MFC, ///< Ursa (TTL output to Ursa) 254 LINK_DAC_I, ///< DAC output 255 LINK_DAC_P, ///< DAC output 256 LINK_PDPLVDS, ///< For PDP(Vsync use Manually MODE) 257 LINK_EXT, /// EXT LPLL TYPE 258 }APIPNL_LINK_TYPE; 259 260 /// Define PANEL Signaling Type 261 typedef enum 262 { 263 // M10 New Panel Type 264 LINK_EPI34_8P = LINK_EXT, /// 10 265 LINK_EPI28_8P, /// 11 266 LINK_EPI34_6P, /// 12 267 LINK_EPI28_6P, /// 13 268 269 ///LINK_MINILVDS_6P_2L, /// replace this with LINK_MINILVDS 270 LINK_MINILVDS_5P_2L, /// 14 271 LINK_MINILVDS_4P_2L, /// 15 272 LINK_MINILVDS_3P_2L, /// 16 273 LINK_MINILVDS_6P_1L, /// 17 274 LINK_MINILVDS_5P_1L, /// 18 275 LINK_MINILVDS_4P_1L, /// 19 276 LINK_MINILVDS_3P_1L, /// 20 277 278 LINK_HS_LVDS, /// 21 279 LINK_HF_LVDS, /// 22 280 281 LINK_TTL_TCON, /// 23 282 LINK_MINILVDS_2CH_3P_8BIT, // 2 channel, 3 pair, 8 bits ///24 283 LINK_MINILVDS_2CH_4P_8BIT, // 2 channel, 4 pair, 8 bits ///25 284 LINK_MINILVDS_2CH_5P_8BIT, // 2 channel, 5 pair, 8 bits ///26 285 LINK_MINILVDS_2CH_6P_8BIT, // 2 channel, 6 pair, 8 bits ///27 286 287 LINK_MINILVDS_1CH_3P_8BIT, // 1 channel, 3 pair, 8 bits ///28 288 LINK_MINILVDS_1CH_4P_8BIT, // 1 channel, 4 pair, 8 bits ///29 289 LINK_MINILVDS_1CH_5P_8BIT, // 1 channel, 5 pair, 8 bits ///30 290 LINK_MINILVDS_1CH_6P_8BIT, // 1 channel, 6 pair, 8 bits ///31 291 292 LINK_MINILVDS_2CH_3P_6BIT, // 2 channel, 3 pari, 6 bits ///32 293 LINK_MINILVDS_2CH_4P_6BIT, // 2 channel, 4 pari, 6 bits ///33 294 LINK_MINILVDS_2CH_5P_6BIT, // 2 channel, 5 pari, 6 bits ///34 295 LINK_MINILVDS_2CH_6P_6BIT, // 2 channel, 6 pari, 6 bits ///35 296 297 LINK_MINILVDS_1CH_3P_6BIT, // 1 channel, 3 pair, 6 bits ///36 298 LINK_MINILVDS_1CH_4P_6BIT, // 1 channel, 4 pair, 6 bits ///37 299 LINK_MINILVDS_1CH_5P_6BIT, // 1 channel, 5 pair, 6 bits ///38 300 LINK_MINILVDS_1CH_6P_6BIT, // 1 channel, 6 pair, 6 bits ///39 301 LINK_HDMI_BYPASS_MODE, // HDMI Bypass Mode///40 302 303 LINK_EPI34_2P, /// 41 304 LINK_EPI34_4P, /// 42 305 LINK_EPI28_2P, /// 43 306 LINK_EPI28_4P, /// 44 307 308 LINK_VBY1_10BIT_4LANE, ///45 309 LINK_VBY1_10BIT_2LANE, ///46 310 LINK_VBY1_10BIT_1LANE, ///47 311 LINK_VBY1_8BIT_4LANE, ///48 312 LINK_VBY1_8BIT_2LANE, ///49 313 LINK_VBY1_8BIT_1LANE, ///50 314 315 LINK_VBY1_10BIT_8LANE, ///51 316 LINK_VBY1_8BIT_8LANE, ///52 317 318 LINK_EPI28_12P, ///53 319 320 LINK_HS_LVDS_2CH_BYPASS_MODE, //54 321 LINK_VBY1_8BIT_4LANE_BYPASS_MODE, //55 322 LINK_VBY1_10BIT_4LANE_BYPASS_MODE, //56 323 324 }APIPNL_LINK_EXT_TYPE; 325 326 /// Define power on and off timing order. 327 typedef enum 328 { 329 E_APIPNL_POWER_TIMING_1 , ///< Timing order 1 330 E_APIPNL_POWER_TIMING_2 , ///< Timing order 2 331 E_APIPNL_POWER_TIMING_NA = 0xFFFF, ///< Reserved Timing order 332 } APIPNL_POWER_TIMING_SEQ; 333 334 /// Define TI bit mode 335 typedef enum 336 { 337 TI_10BIT_MODE = 0, 338 TI_8BIT_MODE = 2, 339 TI_6BIT_MODE = 3, 340 } APIPNL_TIBITMODE; 341 342 /// Define which panel output timing change mode is used to change VFreq for same panel 343 typedef enum 344 { 345 E_PNL_CHG_DCLK = 0, ///<change output DClk to change Vfreq. 346 E_PNL_CHG_HTOTAL = 1, ///<change H total to change Vfreq. 347 E_PNL_CHG_VTOTAL = 2, ///<change V total to change Vfreq. 348 } APIPNL_OUT_TIMING_MODE; 349 350 /// Define panel output format bit mode 351 typedef enum 352 { 353 OUTPUT_10BIT_MODE = 0,//default is 10bit, becasue 8bit panel can use 10bit config and 8bit config. 354 OUTPUT_6BIT_MODE = 1, //but 10bit panel(like PDP panel) can only use 10bit config. 355 OUTPUT_8BIT_MODE = 2, //and some PDA panel is 6bit. 356 } APIPNL_OUTPUTFORMAT_BITMODE; 357 358 /// Panel Api information 359 typedef struct __attribute__((packed)) 360 { 361 APIPNL_GAMMA_TYPE eSupportGammaType; ///< Gamma type supported by apiPNL 362 } PNL_ApiInfo; 363 364 /// Panel status 365 typedef struct __attribute__((packed)) 366 { 367 MS_BOOL bPanel_Initialized; ///< panel initialized or not 368 MS_BOOL bPanel_Enabled; ///< panel enabled or not, if enabled, you can see OSD/Video 369 } PNL_ApiStatus; 370 371 /// Panel status 372 typedef struct 373 { 374 MS_U32 u32ApiStatusEx_Version;///<Version of current structure. Please always set to "API_PNLSTATUS_EX_VERSION" as input 375 MS_U16 u16ApiStatusEX_Length; ///<Length of this structure, u16PanelInfoEX_Length=sizeof(XC_PANEL_INFO_EX) 376 377 MS_BOOL bPNLInitialize; ///< panel initialized or not 378 MS_BOOL bPNLEnable; ///< panel enabled or not, if enabled, you can see OSD/Video 379 MS_U16 u16VTotal; ///< Output vertical total 380 MS_U16 u16DEVStart; ///< Output DE vertical start 381 MS_U16 u16DEVEnd; ///< Output DE Vertical end 382 MS_U16 u16VSyncStart; ///< Output VSync start 383 MS_U16 u16VSyncEnd; ///< Output VSync end 384 MS_U16 u16HTotal; ///< Output horizontal total 385 MS_U16 u16DEHStart; ///< Output DE horizontal start 386 MS_U16 u16DEHEnd; ///< Output DE horizontal end 387 MS_U16 u16HSyncWidth; ///< Output HSync width 388 MS_BOOL bIsPanelManualVysncMode; ///< enable manuel V sync control 389 MS_BOOL bInterlaceOutput; ///< enable Scaler Interlace output 390 MS_BOOL bYUVOutput; ///< enable Scaler YUV output 391 } PNL_ApiExtStatus; 392 393 /// Panel output control, must be called before g_IPanel.Enable(), otherwise will output after called g_IPanel.Enable() 394 typedef enum 395 { 396 E_APIPNL_OUTPUT_NO_OUTPUT = 0, ///< even called g_IPanel.Enable(TRUE), still no physical output 397 E_APIPNL_OUTPUT_CLK_ONLY, ///< after called g_IPanel.Enable(TRUE), will output clock only 398 E_APIPNL_OUTPUT_DATA_ONLY, ///< after called g_IPanel.Enable(TRUE), will output data only 399 E_APIPNL_OUTPUT_CLK_DATA, ///< after called g_IPanel.Enable(TRUE), will output clock and data 400 } APIPNL_OUTPUT_MODE; 401 402 /// Define Panel MISC control index 403 /// please enum use BIT0 = 0x01, BIT1 = 0x02, BIT2 = 0x04, BIT3 = 0x08, BIT4 = 0x10, 404 typedef enum 405 { 406 E_APIPNL_MISC_CTRL_OFF = 0x0000, 407 E_APIPNL_MISC_MFC_ENABLE = 0x0001, 408 E_APIPNL_MISC_SKIP_CALIBRATION = 0x0002, 409 E_APIPNL_MISC_GET_OUTPUT_CONFIG = 0x0004, 410 E_APIPNL_MISC_SKIP_ICONVALUE = 0x0008, 411 412 E_APIPNL_MISC_MFC_MCP = 0x0010, // bit 4 413 E_APIPNL_MISC_MFC_ABChannel = 0x0020, // bit5 414 E_APIPNL_MISC_MFC_ACChannel = 0x0040, // bit 6 415 E_APIPNL_MISC_MFC_ENABLE_60HZ = 0x0080, // bit 7, for 60Hz Panel 416 E_APIPNL_MISC_MFC_ENABLE_240HZ = 0x0100, // bit 8, for 240Hz Panel 417 E_APIPNL_MISC_4K2K_ENABLE_60HZ = 0x0200, // bit 9, for 4k2K 60Hz Panel 418 E_APIPNL_MISC_SKIP_T3D_CONTROL = 0x0400, // bit 10, for T3D control 419 E_APIPNL_MISC_PIXELSHIFT_ENABLE = 0x0800,// bit 11, enable pixel shift 420 E_APIPNL_MISC_ENABLE_MANUAL_VSYNC_CTRL = 0x8000, // enable manual V sync control 421 } APIPNL_MISC; 422 423 typedef enum 424 { 425 E_APIPNL_TCON_TAB_TYPE_GENERAL, 426 E_APIPNL_TCON_TAB_TYPE_GPIO, 427 E_APIPNL_TCON_TAB_TYPE_SCALER, 428 E_APIPNL_TCON_TAB_TYPE_MOD, 429 E_APIPNL_TCON_TAB_TYPE_GAMMA, 430 E_APIPNL_TCON_TAB_TYPE_POWER_SEQUENCE_ON, 431 E_APIPNL_TCON_TAB_TYPE_POWER_SEQUENCE_OFF, 432 }APIPNL_TCON_TAB_TYPE; 433 434 typedef enum 435 { 436 APIPNL_OUTPUT_CHANNEL_ORDER_DEFAULT, 437 APIPNL_OUTPUT_CHANNEL_ORDER_USER, 438 }APIPNL_OUTPUT_CHANNEL_ORDER; 439 440 /** 441 * Represent a panel interface. 442 * 443 * Provide panel attributes, and some panel basic functions 444 */ 445 typedef struct 446 { 447 // 448 // Data 449 // 450 const char* ( * const Name ) ( void ); // /< Panel name 451 MS_U16 ( * const HStart ) ( void ); // /< DE H start 452 MS_U16 ( * const VStart ) ( void ); // /< DE V start 453 MS_U16 ( * const Width ) ( void ); // /< DE H width 454 MS_U16 ( * const Height ) ( void ); // /< DE V height 455 MS_U16 ( * const HTotal ) ( void ); // /< Htotal 456 MS_U16 ( * const VTotal ) ( void ); // /< Vtotal 457 MS_U8 ( * const HSynWidth ) ( void ); // /< H sync width 458 MS_U8 ( * const HSynBackPorch ) ( void ); // /< H sync back porch 459 MS_U8 ( * const VSynBackPorch ) ( void ); // /< V sync back porch 460 MS_U16 ( * const DefaultVFreq ) ( void ); // /< deault V Freq 461 MS_U8 ( * const LPLL_Mode ) ( void ); // /< 0: single, 1: dual mode 462 MS_U8 ( * const LPLL_Type ) ( void ); // /< 0: LVDS, 1: RSDS 463 E_PNL_ASPECT_RATIO ( * const AspectRatio ) ( void ); // /< please refer to E_PNL_ASPECT_RATIO 464 MS_U32 ( * const MinSET ) ( void ); // / < MinSET 465 MS_U32 ( * const MaxSET ) ( void ); // / < MaxSET 466 467 // 468 // Manipulation 469 // 470 /// @brief Set Span-Spectrum-Control 471 /// @param u16Fmodulation IN:SSC_SPAN_PERIOD 472 /// @param u16Rdeviation IN:SSC_STEP_PERCENT 473 /// @param bEnable IN:Enable / Disable 474 /// 475 void ( * const SetSSC ) ( MS_U16 u16Fmodulation, MS_U16 u16Rdeviation, MS_BOOL bEnable ) ; 476 void ( * const SetOSDSSC ) ( MS_U16 u16Fmodulation, MS_U16 u16Rdeviation, MS_BOOL bEnable ) ; 477 478 /// @brief Enable panel's output, but "not include the function to turn VCC on". 479 /// @param bEnable IN:Enable / Disable 480 MS_BOOL ( * const Enable ) ( MS_BOOL bEnable ) ; 481 482 /// @brief Set Gamma correction table. 483 /// @param eGammaType Resolution of gamma table 484 /// @param pu8GammaTab gamma table 485 /// @param u16NumOfLevel T2: 256, T3: can be 256 / 1024 levels 486 MS_BOOL ( * const SetGammaTbl ) ( APIPNL_GAMMA_TYPE eGammaType, 487 MS_U8* pu8GammaTab[3], 488 APIPNL_GAMMA_MAPPEING_MODE Gamma_Map_Mode ) ; 489 490 /// @brief Get Gamma correction table. 491 /// @return A Gamma table used currently. 492 MS_U8** ( * const GammaTab ) ( void ) ; 493 494 /// @brief printout panel data, width, height, htt, vtt etc. 495 void ( * const Dump ) ( void ) ; 496 497 /// @brief Get Min/Max/Current Dimming Value according to the given flag. 498 /// @param max_min_setting Flag of Min / Max / Current Dimming Value.s 499 MS_U8 ( * const DimCtrl ) ( APIPNL_DIMMING_CTRL max_min_setting ) ; 500 501 /// @brief Query Power On Timing with given power on timing order.\n 502 /// @param power_on_sequence_timing order 503 MS_U16 ( * const OnTiming ) ( APIPNL_POWER_TIMING_SEQ power_on_sequence_timing ) ; 504 505 /// @brief Query Power Off Timing with given power on timing order.\n 506 /// @param power_off_sequence_timing order 507 MS_U16 ( * const OffTiming ) ( APIPNL_POWER_TIMING_SEQ power_off_sequence_timing ) ; 508 509 // 510 // Custimized methods, can be provided by clinets. 511 // 512 void ( *TurnBackLightOn ) ( MS_BOOL bEnable ) ; 513 APIPNL_OUT_TIMING_MODE 514 ( * const OutTimingMode )( void ); ///<output timing mode 515 516 ///@brief Set Gamma value 517 ///@param u8Channel R/G/B channel, 0->R, 1->G, 2->B 518 ///@param u16Offset The address of Gamma value 519 ///@param u16GammaValue Gamma value 520 MS_BOOL (* const SetGammaValue)(MS_U8 u8Channel, MS_U16 u16Offset, MS_U16 u16GammaValue); 521 522 /// @brief Get Gamma correction table. 523 /// @param eGammaType Resolution of gamma table 524 /// @param pu8GammaTab gamma table 525 /// @param Gamma_Map_Mode 8Bit mapping or 10Bit mapping 526 MS_BOOL ( * const GetGammaTbl ) ( APIPNL_GAMMA_TYPE eGammaType, 527 MS_U8* pu8GammaTab[3], 528 APIPNL_GAMMA_MAPPEING_MODE Gamma_Map_Mode ) ; 529 }XC_PNL_OBJ; 530 531 /// A panel struct type used to specify the panel attributes, and settings from Board layout 532 typedef struct __attribute__((packed)) 533 { 534 const char *m_pPanelName; ///< PanelName 535 #if !defined (__aarch64__) 536 MS_U32 u32AlignmentDummy0; 537 #endif 538 // 539 // Panel output 540 // 541 MS_U8 m_bPanelDither :1; ///< PANEL_DITHER, keep the setting 542 APIPNL_LINK_TYPE m_ePanelLinkType :4; ///< PANEL_LINK 543 544 /////////////////////////////////////////////// 545 // Board related setting 546 /////////////////////////////////////////////// 547 MS_U8 m_bPanelDualPort :1; ///< VOP_21[8], MOD_4A[1], PANEL_DUAL_PORT, refer to m_bPanelDoubleClk 548 MS_U8 m_bPanelSwapPort :1; ///< MOD_4A[0], PANEL_SWAP_PORT, refer to "LVDS output app note" A/B channel swap 549 MS_U8 m_bPanelSwapOdd_ML :1; ///< PANEL_SWAP_ODD_ML 550 MS_U8 m_bPanelSwapEven_ML :1; ///< PANEL_SWAP_EVEN_ML 551 MS_U8 m_bPanelSwapOdd_RB :1; ///< PANEL_SWAP_ODD_RB 552 MS_U8 m_bPanelSwapEven_RB :1; ///< PANEL_SWAP_EVEN_RB 553 554 MS_U8 m_bPanelSwapLVDS_POL :1; ///< MOD_40[5], PANEL_SWAP_LVDS_POL, for differential P/N swap 555 MS_U8 m_bPanelSwapLVDS_CH :1; ///< MOD_40[6], PANEL_SWAP_LVDS_CH, for pair swap 556 MS_U8 m_bPanelPDP10BIT :1; ///< MOD_40[3], PANEL_PDP_10BIT ,for pair swap 557 MS_U8 m_bPanelLVDS_TI_MODE :1; ///< MOD_40[2], PANEL_LVDS_TI_MODE, refer to "LVDS output app note" 558 559 /////////////////////////////////////////////// 560 // For TTL Only 561 /////////////////////////////////////////////// 562 MS_U8 m_ucPanelDCLKDelay; ///< PANEL_DCLK_DELAY 563 MS_U8 m_bPanelInvDCLK :1; ///< MOD_4A[4], PANEL_INV_DCLK 564 MS_U8 m_bPanelInvDE :1; ///< MOD_4A[2], PANEL_INV_DE 565 MS_U8 m_bPanelInvHSync :1; ///< MOD_4A[12], PANEL_INV_HSYNC 566 MS_U8 m_bPanelInvVSync :1; ///< MOD_4A[3], PANEL_INV_VSYNC 567 568 /////////////////////////////////////////////// 569 // Output driving current setting 570 /////////////////////////////////////////////// 571 // driving current setting (0x00=4mA, 0x01=6mA, 0x02=8mA, 0x03=12mA) 572 MS_U8 m_ucPanelDCKLCurrent; ///< define PANEL_DCLK_CURRENT 573 MS_U8 m_ucPanelDECurrent; ///< define PANEL_DE_CURRENT 574 MS_U8 m_ucPanelODDDataCurrent; ///< define PANEL_ODD_DATA_CURRENT 575 MS_U8 m_ucPanelEvenDataCurrent; ///< define PANEL_EVEN_DATA_CURRENT 576 577 /////////////////////////////////////////////// 578 // panel on/off timing 579 /////////////////////////////////////////////// 580 MS_U16 m_wPanelOnTiming1; ///< time between panel & data while turn on power 581 MS_U16 m_wPanelOnTiming2; ///< time between data & back light while turn on power 582 MS_U16 m_wPanelOffTiming1; ///< time between back light & data while turn off power 583 MS_U16 m_wPanelOffTiming2; ///< time between data & panel while turn off power 584 585 /////////////////////////////////////////////// 586 // panel timing spec. 587 /////////////////////////////////////////////// 588 // sync related 589 MS_U8 m_ucPanelHSyncWidth; ///< VOP_01[7:0], PANEL_HSYNC_WIDTH 590 MS_U8 m_ucPanelHSyncBackPorch; ///< PANEL_HSYNC_BACK_PORCH, no register setting, provide value for query only 591 592 ///< not support Manuel VSync Start/End now 593 ///< VOP_02[10:0] VSync start = Vtt - VBackPorch - VSyncWidth 594 ///< VOP_03[10:0] VSync end = Vtt - VBackPorch 595 MS_U8 m_ucPanelVSyncWidth; ///< define PANEL_VSYNC_WIDTH 596 MS_U8 m_ucPanelVBackPorch; ///< define PANEL_VSYNC_BACK_PORCH 597 598 // DE related 599 MS_U16 m_wPanelHStart; ///< VOP_04[11:0], PANEL_HSTART, DE H Start (PANEL_HSYNC_WIDTH + PANEL_HSYNC_BACK_PORCH) 600 MS_U16 m_wPanelVStart; ///< VOP_06[11:0], PANEL_VSTART, DE V Start 601 MS_U16 m_wPanelWidth; ///< PANEL_WIDTH, DE width (VOP_05[11:0] = HEnd = HStart + Width - 1) 602 MS_U16 m_wPanelHeight; ///< PANEL_HEIGHT, DE height (VOP_07[11:0], = Vend = VStart + Height - 1) 603 604 // DClk related 605 MS_U16 m_wPanelMaxHTotal; ///< PANEL_MAX_HTOTAL. Reserved for future using. 606 MS_U16 m_wPanelHTotal; ///< VOP_0C[11:0], PANEL_HTOTAL 607 MS_U16 m_wPanelMinHTotal; ///< PANEL_MIN_HTOTAL. Reserved for future using. 608 609 MS_U16 m_wPanelMaxVTotal; ///< PANEL_MAX_VTOTAL. Reserved for future using. 610 MS_U16 m_wPanelVTotal; ///< VOP_0D[11:0], PANEL_VTOTAL 611 MS_U16 m_wPanelMinVTotal; ///< PANEL_MIN_VTOTAL. Reserved for future using. 612 613 MS_U8 m_dwPanelMaxDCLK; ///< PANEL_MAX_DCLK. Reserved for future using. 614 MS_U8 m_dwPanelDCLK; ///< LPLL_0F[23:0], PANEL_DCLK ,{0x3100_10[7:0], 0x3100_0F[15:0]} 615 MS_U8 m_dwPanelMinDCLK; ///< PANEL_MIN_DCLK. Reserved for future using. 616 617 ///< spread spectrum 618 MS_U16 m_wSpreadSpectrumStep; ///< move to board define, no use now. 619 MS_U16 m_wSpreadSpectrumSpan; ///< move to board define, no use now. 620 621 MS_U8 m_ucDimmingCtl; ///< Initial Dimming Value 622 MS_U8 m_ucMaxPWMVal; ///< Max Dimming Value 623 MS_U8 m_ucMinPWMVal; ///< Min Dimming Value 624 625 MS_U8 m_bPanelDeinterMode :1; ///< define PANEL_DEINTER_MODE, no use now 626 E_PNL_ASPECT_RATIO m_ucPanelAspectRatio; ///< Panel Aspect Ratio, provide information to upper layer application for aspect ratio setting. 627 /* 628 * 629 * Board related params 630 * 631 * If a board ( like BD_MST064C_D01A_S ) swap LVDS TX polarity 632 * : This polarity swap value = 633 * (LVDS_PN_SWAP_H<<8) | LVDS_PN_SWAP_L from board define, 634 * Otherwise 635 * : The value shall set to 0. 636 */ 637 MS_U16 m_u16LVDSTxSwapValue; 638 APIPNL_TIBITMODE m_ucTiBitMode; ///< MOD_4B[1:0], refer to "LVDS output app note" 639 APIPNL_OUTPUTFORMAT_BITMODE m_ucOutputFormatBitMode; 640 641 MS_U8 m_bPanelSwapOdd_RG :1; ///< define PANEL_SWAP_ODD_RG 642 MS_U8 m_bPanelSwapEven_RG :1; ///< define PANEL_SWAP_EVEN_RG 643 MS_U8 m_bPanelSwapOdd_GB :1; ///< define PANEL_SWAP_ODD_GB 644 MS_U8 m_bPanelSwapEven_GB :1; ///< define PANEL_SWAP_EVEN_GB 645 646 /** 647 * Others 648 */ 649 MS_U8 m_bPanelDoubleClk :1; ///< LPLL_03[7], define Double Clock ,LVDS dual mode 650 MS_U32 m_dwPanelMaxSET; ///< define PANEL_MAX_SET 651 MS_U32 m_dwPanelMinSET; ///< define PANEL_MIN_SET 652 APIPNL_OUT_TIMING_MODE m_ucOutTimingMode; ///<Define which panel output timing change mode is used to change VFreq for same panel 653 MS_U8 m_bPanelNoiseDith :1; ///< PAFRC mixed with noise dither disable 654 } PanelType; 655 656 //Display information 657 typedef struct 658 { 659 MS_U32 VDTOT; //Output vertical total 660 MS_U32 DEVST; //Output DE vertical start 661 MS_U32 DEVEND;//Output DE Vertical end 662 MS_U32 HDTOT;// Output horizontal total 663 MS_U32 DEHST; //Output DE horizontal start 664 MS_U32 DEHEND;// Output DE horizontal end 665 MS_BOOL bInterlaceMode; 666 MS_BOOL bYUVOutput; 667 } MS_PNL_DST_DispInfo; 668 669 //HW LVDS Reserved Bit to L/R flag Info 670 typedef struct 671 { 672 MS_U32 u32pair; // pair 0: BIT0, pair 1: BIT1, pair 2: BIT2, pair 3: BIT3, pair 4: BIT4, etc ... 673 MS_U16 u16channel; // channel A: BIT0, channel B: BIT1, 674 MS_BOOL bEnable; 675 } MS_PNL_HW_LVDSResInfo; 676 677 /// Define the initial OverDrive for XC 678 typedef struct 679 { 680 MS_U8 u8ODTbl[1056]; 681 MS_U32 u32PNL_version; ///<Version of current structure. 682 // OD frame buffer related 683 MS_PHYADDR u32OD_MSB_Addr; ///<OverDrive MSB frame buffer start address, absolute without any alignment 684 MS_U32 u32OD_MSB_Size; ///<OverDrive MSB frame buffer size, the unit is BYTES 685 MS_PHYADDR u32OD_LSB_Addr; ///<OverDrive LSB frame buffer start address, absolute without any alignment 686 MS_U32 u32OD_LSB_Size; ///<OverDrive MSB frame buffer size, the unit is BYTES 687 } MS_PNL_OD_INITDATA; 688 689 typedef struct 690 { 691 MS_U16 m_u16ExpectSwingLevel; 692 MS_U8 m_u8ModCaliPairSel; 693 MS_U8 m_u8ModCaliTarget; 694 MS_S8 m_s8ModCaliOffset; 695 MS_BOOL m_bPVDD_2V5; 696 }MS_PNL_ModCaliInfo; 697 698 //------------------------------------------------------------------------------------------------- 699 //MApi_PNL_Setting enum of cmd 700 //------------------------------------------------------------------------------------------------- 701 typedef enum 702 { 703 E_PNL_MOD_PECURRENT_SETTING, 704 E_PNL_CONTROL_OUT_SWING, 705 }E_PNL_SETTING; 706 //------------------------------------------------------------------------------------------------- 707 //MApi_PNL_Setting struct of cmd 708 //------------------------------------------------------------------------------------------------- 709 typedef struct 710 { 711 MS_U16 u16Current_Level; 712 MS_U16 u16Channel_Select; 713 }ST_PNL_MOD_PECURRENT_SETTING; 714 715 typedef struct 716 { 717 MS_U16 u16Swing_Level; 718 }ST_PNL_CONTROL_OUT_SWING; 719 720 //------------------------------------------------------------------------------------------------- 721 722 //------------------------------------------------------------------------------------------------- 723 // Function and Variable 724 //------------------------------------------------------------------------------------------------- 725 726 /******************************************************************************/ 727 /* Variable */ 728 /* ****************************************************************************/ 729 /** 730 * 731 * The global interface for panel manipulation. 732 * 733 * @attention <b>Call "MApi_PNL_Init()" first before using this obj</b> 734 */ 735 extern XC_PNL_OBJ g_IPanel; 736 INTERFACE void* pu32PNLInst; 737 typedef enum 738 { 739 E_PNL_NO_OUTPUT, 740 E_PNL_CLK_ONLY, 741 E_PNL_CLK_DATA, 742 E_PNL_MAX, 743 } E_PNL_PREINIT_OPTIONS; 744 //------------------------------------------------------------------------------ 745 /// Description : Show the PNL driver version 746 /// @ingroup PNL_INTERFACE_INFO 747 /// @param ppVersion \b OUT: output PNL driver version 748 /// @return @ref APIPNL_Result 749 /// @return E_APIPNL_OK : succeed 750 /// @return E_APIPNL_FAIL : fail before timeout or illegal parameters 751 //------------------------------------------------------------------------------ 752 // APIPNL_Result MApi_PNL_GetLibVer(const MSIF_Version **ppVersion); 753 754 //------------------------------------------------------------------------------ 755 /// Description : Show the PNL info 756 /// @ingroup PNL_INTERFACE_INFO 757 /// @return @ref APIPNL_Result 758 /// @return E_APIPNL_OK : succeed 759 /// @return E_APIPNL_FAIL : fail before timeout or illegal parameters 760 //------------------------------------------------------------------------------ 761 // const PNL_ApiInfo * MApi_PNL_GetInfo(void); 762 763 //------------------------------------------------------------------------------ 764 /// Description : Show the PNL Status 765 /// @ingroup PNL_INTERFACE_ToBeModified 766 /// @param pPnlStatus \b IN: point of panel status 767 /// @return @ref MS_BOOL 768 //------------------------------------------------------------------------------ 769 // MS_BOOL MApi_PNL_GetStatus(PNL_ApiStatus *pPnlStatus); 770 771 //------------------------------------------------------------------------------ 772 /// Description : Show the PNL Status EX 773 /// @ingroup PNL_INTERFACE_ToBeModified 774 /// @param pPnlExtStatus \b IN: point of panel status 775 /// @return @ref MS_BOOL 776 //------------------------------------------------------------------------------ 777 MS_BOOL MApi_PNL_GetStatusEx(PNL_ApiExtStatus *pPnlExtStatus); 778 779 //------------------------------------------------------------------------------ 780 /// Description : Set the PNL debug level 781 /// @ingroup PNL_INTERFACE_INFO 782 /// @param u16DbgSwitch \b IN: debug level switch 783 /// @return @ref MS_BOOL 784 //------------------------------------------------------------------------------ 785 MS_BOOL MApi_PNL_SetDbgLevel(MS_U16 u16DbgSwitch); 786 787 //------------------------------------------------------------------------------ 788 /// Description : Init the PNL IOMAP base 789 /// @ingroup PNL_INTERFACE_INIT 790 /// @return @ref MS_BOOL 791 //------------------------------------------------------------------------------ 792 MS_BOOL MApi_PNL_IOMapBaseInit(void); 793 //------------------------------------------------------------------------------ 794 /// Description : Pre Init the PNL 795 /// @ingroup PNL_INTERFACE_INIT 796 /// @param eInitParam \b IN: Init Parameter 797 /// @return @ref MS_BOOL 798 //------------------------------------------------------------------------------ 799 MS_BOOL MApi_PNL_PreInit(E_PNL_PREINIT_OPTIONS eInitParam); 800 801 //------------------------------------------------------------------------------ 802 /// Description : 803 /// This is a wrapper for \link MApi_PNL_Init_Ex \endlink. 804 /// For more information, please check MApi_PNL_Init_Ex( ). 805 /// @ingroup PNL_INTERFACE_INIT 806 //------------------------------------------------------------------------------ 807 #ifndef _API_XC_PANEL_C_ 808 #define MApi_PNL_Init(x) MApi_PNL_Init_Ex(x, (MSIF_Version){{ PNL_API_VERSION },}); 809 #endif 810 //------------------------------------------------------------------------------ 811 /// \b Description : \n 812 /// In order to make panel inited and working properly according to panel spec, such as Htotal, Vtotal..etc \n 813 /// We have to pass these specific panel specs to Utopia panel module by this API. 814 /// @ingroup PNL_INTERFACE_INIT 815 /// @param[in] pSelPanelType A panel struct type used to specify the panel attributes, and settings from PCB board layout 816 /// @param[in] LIBVER lib version 817 /// @return @ref MS_BOOL returns @ref TRUE for success, @ref FALSE for failure. 818 /// @par Example Code 819 /// \code 820 /// // MApi_PNL_Init_Ex example : how to pass initial panel data to panel driver. 821 /// #include <apiPNL.h> 822 /// 823 /// void main() 824 /// { 825 /// MS_BOOL bSuccess = FALSE; 826 /// 827 /// // This setting is purely virtual 828 /// // it should be adopted from panel vendors 829 /// PanelType panelSetting = { 830 /// .m_pPanelName = "MStar_Panel, 831 /// .m_bPanelDither = 1, 832 /// .m_ePanelLinkType = LINK_LVDS, 833 /// ... 834 /// ... 835 /// }; 836 /// 837 /// bSuccess = MApi_PNL_Init_Ex( &panelSetting, 838 /// (MSIF_Version){{ PNL_API_VERSION },} 839 /// ); 840 /// } 841 /// \endcode 842 //------------------------------------------------------------------------------ 843 MS_BOOL MApi_PNL_Init_Ex(PanelType *pSelPanelType, MSIF_Version LIBVER); 844 845 //------------------------------------------------------------------------------ 846 /// Description : Setup the PNL output type 847 /// @ingroup PNL_INTERFACE_FEATURE 848 /// @param eOutputMode \b IN: setup output mode 849 //------------------------------------------------------------------------------ 850 void MApi_PNL_SetOutput(APIPNL_OUTPUT_MODE eOutputMode); 851 852 //------------------------------------------------------------------------------ 853 /// Description : Change the PNL type 854 /// @ingroup PNL_INTERFACE_FEATURE 855 /// @param pSelPanelType \b IN: change panel type 856 /// @return @ref MS_BOOL 857 //------------------------------------------------------------------------------ 858 MS_BOOL MApi_PNL_ChangePanelType(PanelType *pSelPanelType); 859 860 //------------------------------------------------------------------------------ 861 /// Description : Dump TCON Table 862 /// @ingroup PNL_INTERFACE_INIT 863 /// @param pTCONTable \b IN: Table 864 /// @param u8Tcontype \b IN: use APIPNL_TCON_TAB_TYPE ad input 865 /// @return @ref MS_BOOL 866 //------------------------------------------------------------------------------ 867 MS_BOOL MApi_PNL_TCONMAP_DumpTable(MS_U8 *pTCONTable, MS_U8 u8Tcontype); 868 869 //------------------------------------------------------------------------------ 870 /// Description : Control the TCON power sequence 871 /// @ingroup PNL_INTERFACE_INIT 872 /// @param pTCONTable \b IN: Table 873 /// @param bEnable \b IN: Enable Power sequence 874 /// @return @ref MS_BOOL 875 //------------------------------------------------------------------------------ 876 // MS_BOOL MApi_PNL_TCONMAP_Power_Sequence(MS_U8 *pTCONTable, MS_BOOL bEnable); 877 //------------------------------------------------------------------------------ 878 /// Description : Reset the TCON counter 879 /// @ingroup PNL_INTERFACE_INIT 880 /// @param bEnable \b IN: Enable Power sequence 881 /// @return @ref MS_BOOL 882 //------------------------------------------------------------------------------ 883 void MApi_PNL_TCON_Count_Reset ( MS_BOOL bEnable ); 884 //------------------------------------------------------------------------------ 885 /// Description : Init the TCON 886 /// @ingroup PNL_INTERFACE_INIT 887 //------------------------------------------------------------------------------ 888 889 void MApi_PNL_TCON_Init( void ); 890 //------------------------------------------------------------------------------ 891 /// Description : Show the PNL Destnation info 892 /// @ingroup PNL_INTERFACE_INFO 893 /// @param pDstInfo \b IN: get destanation onfo 894 /// @param u32SizeofDstInfo \b IN: size of stucture 895 /// @return @ref MS_BOOL 896 //------------------------------------------------------------------------------ 897 MS_BOOL MApi_PNL_GetDstInfo(MS_PNL_DST_DispInfo *pDstInfo, MS_U32 u32SizeofDstInfo); 898 899 //------------------------------------------------------------------------------ 900 /// Description : Setup the PNL output swing 901 /// @ingroup PNL_INTERFACE_FEATURE 902 /// @param u16Swing_Level \b IN: setup swing value 903 /// @return @ref MS_BOOL 904 //------------------------------------------------------------------------------ 905 MS_BOOL MApi_PNL_Control_Out_Swing(MS_U16 u16Swing_Level); 906 //------------------------------------------------------------------------------ 907 /// Description : Setup the PNL output DCLK 908 /// @ingroup PNL_INTERFACE_ToBeModified 909 /// @param u16PanelDCLK \b IN: setup DCLK 910 /// @param bSetDCLKEnable \b IN: enable this setting 911 /// @return @ref MS_BOOL 912 //------------------------------------------------------------------------------ 913 MS_BOOL MApi_PNL_ForceSetPanelDCLK(MS_U16 u16PanelDCLK ,MS_BOOL bSetDCLKEnable ); 914 //------------------------------------------------------------------------------ 915 /// Description : Setup the PNL Horizontal start 916 /// @ingroup PNL_INTERFACE_INIT 917 /// @param u16PanelHStart \b IN: setup H start 918 /// @param bSetHStartEnable \b IN: enable this setting 919 /// @return @ref MS_BOOL 920 //------------------------------------------------------------------------------ 921 MS_BOOL MApi_PNL_ForceSetPanelHStart(MS_U16 u16PanelHStart ,MS_BOOL bSetHStartEnable); 922 //------------------------------------------------------------------------------ 923 /// Description : Setup the PNL Output pattern 924 /// @ingroup PNL_INTERFACE_FEATURE 925 /// @param bEnable \b IN: Enable output pattern 926 /// @param u16Red \b IN: Red color 927 /// @param u16Green \b IN: Green color 928 /// @param u16Blue \b IN: Blue color 929 //------------------------------------------------------------------------------ 930 void MApi_PNL_SetOutputPattern(MS_BOOL bEnable, MS_U16 u16Red , MS_U16 u16Green, MS_U16 u16Blue); 931 //------------------------------------------------------------------------------ 932 /// Description : Init the MOD calibration parameter 933 /// @ingroup PNL_INTERFACE_INIT 934 /// @param pstModCaliInfo \b IN: setup mod calibration parameter 935 /// @return @ref MS_BOOL 936 //------------------------------------------------------------------------------ 937 // MS_BOOL MApi_Mod_Calibration_Setting(MS_PNL_ModCaliInfo *pstModCaliInfo); 938 939 //------------------------------------------------------------------------------ 940 /// Description : Start the MOD calibration 941 /// @ingroup PNL_INTERFACE_FEATURE 942 /// @return @ref MS_BOOL 943 //------------------------------------------------------------------------------ 944 // MS_BOOL MApi_Mod_Do_Calibration(void); 945 946 //------------------------------------------------------------------------------ 947 /// Description : Type: This type means package. Different package maybe have different type id. 948 /// Check board define or system configure for type id. 949 /// @ingroup PNL_INTERFACE_INIT 950 /// @param Type \b IN: setup LVDS output type for different board layout 951 //------------------------------------------------------------------------------ 952 void MApi_BD_LVDS_Output_Type(MS_U16 Type); 953 954 //------------------------------------------------------------------------------ 955 /// Description : Setup the LPLL type EX 956 /// @ingroup PNL_INTERFACE_ToBeModified 957 /// @param eLPLL_TypeExt \b IN: setup LPLL Ext type 958 //------------------------------------------------------------------------------ 959 void MApi_PNL_SetLPLLTypeExt(APIPNL_LINK_EXT_TYPE eLPLL_TypeExt); 960 961 //------------------------------------------------------------------------------ 962 /// Description : Init the PNL MISC config 963 /// @ingroup PNL_INTERFACE_INIT 964 /// @param ePNL_MISC \b IN: setup MISC control 965 //------------------------------------------------------------------------------ 966 void MApi_PNL_Init_MISC(APIPNL_MISC ePNL_MISC); 967 968 //------------------------------------------------------------------------------ 969 /// Description : Show the PNL MISC config 970 /// @ingroup PNL_INTERFACE_INIT 971 /// @return @ref MS_U32 972 //------------------------------------------------------------------------------ 973 MS_U32 MApi_PNL_GetMiscStatus(void); 974 975 //------------------------------------------------------------------------------ 976 /// Description : Setup the PNL output config by user 977 /// @ingroup PNL_INTERFACE_INIT 978 /// @param u32OutputCFG0_7 \b IN: setup output config channel 00~07 979 /// @param u32OutputCFG8_15 \b IN: setup output config channel 08~15 980 /// @param u32OutputCFG16_21 \b IN: setup output config channel 16~23 981 //------------------------------------------------------------------------------ 982 void MApi_PNL_MOD_OutputConfig_User(MS_U32 u32OutputCFG0_7, MS_U32 u32OutputCFG8_15, MS_U32 u32OutputCFG16_21); 983 984 //------------------------------------------------------------------------------ 985 /// Description : Set channel output order 986 /// @ingroup PNL_INTERFACE_FEATURE 987 /// @param u8OutputOrderType \b IN: use enum of APIPNL_OUTPUT_CHANNEL_ORDER 988 /// @param u16OutputOrder0_3 \b IN: output order of channel 0 to 3 989 /// @param u16OutputOrder4_7 \b IN: output order of channel 4 to 7 990 /// @param u16OutputOrder8_11 \b IN: output order of channel 8 to 11 991 /// @param u16OutputOrder12_13 \b IN: output order of channel 12 to 13 992 //------------------------------------------------------------------------------ 993 void MApi_PNL_MOD_OutputChannelOrder(MS_U8 u8OutputOrderType, 994 MS_U16 u16OutputOrder0_3, 995 MS_U16 u16OutputOrder4_7, 996 MS_U16 u16OutputOrder8_11, 997 MS_U16 u16OutputOrder12_13); 998 999 //------------------------------------------------------------------------------ 1000 /// Description : Setup the PNL 3D LR falg 1001 /// @ingroup PNL_INTERFACE_INIT 1002 /// @param lvdsresinfo \b IN: setup LVDS reserved bit to be LR flag pin 1003 //------------------------------------------------------------------------------ 1004 void MApi_PNL_HWLVDSReservedtoLRFlag(MS_PNL_HW_LVDSResInfo lvdsresinfo); 1005 1006 //------------------------------------------------------------------------------ 1007 /// Description : Setup the PNL PVDD level 1008 /// @ingroup PNL_INTERFACE_INIT 1009 /// @param bIs2p5 \b IN: setup PVDD voltage is 2.5V or 3.3V 1010 //------------------------------------------------------------------------------ 1011 void MApi_MOD_PVDD_Power_Setting(MS_BOOL bIs2p5); 1012 1013 1014 //------------------------------------------------------------------------------ 1015 /// Description : Enable the PNL Video path SSC 1016 /// @ingroup PNL_INTERFACE_FEATURE 1017 /// @param bEnable \b IN: Enable SSC 1018 /// @return @ref APIPNL_Result 1019 //------------------------------------------------------------------------------ 1020 APIPNL_Result MApi_PNL_SetSSC_En(MS_BOOL bEnable); 1021 1022 //------------------------------------------------------------------------------ 1023 /// Description : Set panel SSC Fmodulation 1024 /// @ingroup PNL_INTERFACE_FEATURE 1025 /// @param u16Fmodulation \b IN:Fmodulation, Unit:0.1Khz 1026 /// @return @ref APIPNL_Result 1027 //------------------------------------------------------------------------------ 1028 APIPNL_Result MApi_PNL_SetSSC_Fmodulation(MS_U16 u16Fmodulation); 1029 //------------------------------------------------------------------------------ 1030 /// Description : Set panel SSC Rdeviation 1031 /// @ingroup PNL_INTERFACE_FEATURE 1032 /// @param u16Rdeviation \b IN: u16Rdeviation, Unit:1%%(1/10000) 1033 /// @return @ref APIPNL_Result 1034 //------------------------------------------------------------------------------ 1035 APIPNL_Result MApi_PNL_SetSSC_Rdeviation(MS_U16 u16Rdeviation); 1036 1037 //------------------------------------------------------------------------------ 1038 /// Description : Enable the PNL OSD path SSC 1039 /// @ingroup PNL_INTERFACE_FEATURE 1040 /// @param bEnable \b IN: Enable OSD SSC 1041 /// @return @ref APIPNL_Result 1042 //------------------------------------------------------------------------------ 1043 // APIPNL_Result MApi_PNL_SetOSDSSC_En(MS_BOOL bEnable); 1044 1045 //------------------------------------------------------------------------------ 1046 /// Description : Set panel OSD SSC Fmodulation 1047 /// @ingroup PNL_INTERFACE_FEATURE 1048 /// @param u16Fmodulation \b IN:Fmodulation, Unit:0.1Khz 1049 /// @return @ref APIPNL_Result 1050 //------------------------------------------------------------------------------ 1051 // APIPNL_Result MApi_PNL_SetOSDSSC_Fmodulation(MS_U16 u16Fmodulation); 1052 1053 //------------------------------------------------------------------------------ 1054 /// Description : Set panel OSD SSC Rdeviation 1055 /// @ingroup PNL_INTERFACE_FEATURE 1056 /// @param u16Rdeviation \b IN: u16Rdeviation, Unit:1%%(1/10000) 1057 /// @return TRUE --OK FALSE 1058 //------------------------------------------------------------------------------ 1059 // APIPNL_Result MApi_PNL_SetOSDSSC_Rdeviation(MS_U16 u16Rdeviation); 1060 1061 //------------------------------------------------------------------------------------------------- 1062 /// Description : skip the timing change 1063 /// @ingroup PNL_INTERFACE_INIT 1064 /// @param bSetModeOn \b IN: TRUE: when set mode on t; FALSE: when set mode off 1065 /// @return E_APIPNL_OK or E_APIPNL_FAIL 1066 //------------------------------------------------------------------------------------------------- 1067 1068 APIPNL_Result MApi_PNL_SkipTimingChange(MS_BOOL bFlag); 1069 1070 //------------------------------------------------------------------------------------------------- 1071 /// Description : Set Pre Set Mode On 1072 /// @ingroup PNL_INTERFACE_INIT 1073 /// @param bSetModeOn \b IN: TRUE: when set mode on t; FALSE: when set mode off 1074 /// @return E_APIPNL_OK or E_APIPNL_FAIL 1075 //------------------------------------------------------------------------------------------------- 1076 APIPNL_Result MApi_PNL_PreSetModeOn(MS_BOOL bSetModeOn); 1077 1078 //------------------------------------------------------------------------------------------------- 1079 /// Description : Initialize OverDrive 1080 /// @ingroup PNL_INTERFACE_INIT 1081 /// @param pPNL_ODInitData \b IN: the Initialized Data 1082 /// @param u32ODInitDataLen \b IN: the length of the initialized data 1083 /// @return E_APIPNL_OK or E_APIPNL_FAIL 1084 //------------------------------------------------------------------------------------------------- 1085 APIPNL_Result MApi_PNL_OverDriver_Init(MS_PNL_OD_INITDATA *pPNL_ODInitData, MS_U32 u32ODInitDataLen); 1086 1087 //------------------------------------------------------------------------------------------------- 1088 /// Description : OverDrive Enable 1089 /// @ingroup PNL_INTERFACE_FEATURE 1090 /// @param bEnable \b IN: TRUE: Enable OverDrive; FALSE: Disable OverDrive 1091 /// @return E_APIPNL_OK or E_APIPNL_FAIL 1092 //------------------------------------------------------------------------------------------------- 1093 APIPNL_Result MApi_PNL_OverDriver_Enable(MS_BOOL bEnable); 1094 1095 1096 //------------------------------------------------------------------------------------------------- 1097 /// Description : Get TCON capability 1098 /// @ingroup PNL_INTERFACE_INFO 1099 /// @return MS_BOOL 1100 //------------------------------------------------------------------------------------------------- 1101 // MS_BOOL MApi_PNL_Get_TCON_Capability(void); 1102 1103 1104 //------------------------------------------------------------------------------------------------- 1105 /// Description : Set FRC MOD pair swap 1106 /// @ingroup PNL_INTERFACE_FEATURE 1107 /// @param u32Polarity \b IN: u32Polarity, (d:c:b:a)=([15:14],[13:12],[11:10],[9:8]) => (10,00,11,01), => (2,0,3,1) 1108 //------------------------------------------------------------------------------------------------- 1109 // void MApi_PNL_SetPairSwap(MS_U32 u32Polarity); 1110 1111 //------------------------------------------------------------------------------------------------- 1112 /// Description : Set Ext LPLL type 1113 /// @ingroup PNL_INTERFACE_ToBeModified 1114 /// @param u16Ext_lpll_type \b IN: ldHz = Htt*Vtt*Vfreq 1115 //------------------------------------------------------------------------------------------------- 1116 // void MApi_PNL_SetExt_LPLL_Type(MS_U16 u16Ext_lpll_type); 1117 1118 //------------------------------------------------------------------------------------------------- 1119 /// Description : Cal Ext LPLL Set by DCLK 1120 /// @ingroup PNL_INTERFACE_FEATURE 1121 /// @param ldHz \b IN: ldHz = Htt*Vtt*Vfreq 1122 //------------------------------------------------------------------------------------------------- 1123 // void MApi_PNL_CalExtLPLLSETbyDClk(MS_U32 ldHz); 1124 1125 //------------------------------------------------------------------------------------------------- 1126 /// Description : Enable Internal Termination for Urania, disable it for others case 1127 /// @ingroup PNL_INTERFACE_FEATURE 1128 /// @param bEnable \b IN: Enable or Disable 1129 /// @return TRUE or FALSE 1130 //------------------------------------------------------------------------------------------------- 1131 // MS_BOOL MApi_PNL_EnableInternalTermination(MS_BOOL bEnable); 1132 1133 1134 //------------------------------------------------------------------------------------------------- 1135 /// Description : Set power state 1136 /// @ingroup PNL_INTERFACE_FEATURE 1137 /// @param ePowerState \b IN: power state 1138 /// @return MS_U32 1139 //------------------------------------------------------------------------------------------------- 1140 MS_U32 MApi_PNL_SetPowerState(EN_POWER_MODE ePowerState); 1141 1142 1143 ////////////////////////////////////////////// 1144 // Below functions are obosolted ! Please do not use them if you do not use them yet. 1145 ////////////////////////////////////////////// 1146 1147 //------------------------------------------------------------------------------------------------- 1148 /// Description : Set power state 1149 /// @ingroup PNL_INTERFACE_ToBeRemove 1150 /// @param ePowerState \b IN: power state 1151 /// @return MS_U32 1152 //------------------------------------------------------------------------------------------------- 1153 // MS_BOOL MApi_PNL_SetDiffSwingLevel(MS_U8 u8Swing_Level); 1154 1155 //------------------------------------------------------------------------------------------------- 1156 /// Do handshake for special output device, ex. VB1 1157 /// @ingroup PNL_INTERFACE_FEATURE 1158 /// @return TRUE or FALSE 1159 //------------------------------------------------------------------------------------------------- 1160 MS_BOOL MApi_PNL_OutputDeviceHandshake(void); 1161 1162 //------------------------------------------------------------------------------------------------- 1163 /// Do OC handshake for special output device, ex. VB1 1164 /// @ingroup PNL_INTERFACE_FEATURE 1165 /// @return TRUE or FALSE 1166 //------------------------------------------------------------------------------------------------- 1167 // MS_BOOL MApi_PNL_OutputDeviceOCHandshake(void); 1168 1169 //------------------------------------------------------------------------------------------------- 1170 /// set necessary setting for outputing interlace timing to rear 1171 /// @ingroup PNL_INTERFACE_FEATURE 1172 /// @return APIPNL_Result 1173 //------------------------------------------------------------------------------------------------- 1174 APIPNL_Result MApi_PNL_SetOutputInterlaceTiming(MS_BOOL bEnable); 1175 1176 // void MApi_PNL_GetPanelData(PanelType* pstPNLData); 1177 // void MApi_PNL_DumpPanelData(void); 1178 void MApi_PNL_SetSSC(MS_U16 u16Fmodulation, MS_U16 u16Rdeviation, MS_BOOL bEnable); 1179 // MS_U16 MApi_PNL_GetPanelOnTiming(APIPNL_POWER_TIMING_SEQ seq); 1180 // MS_U16 MApi_PNL_GetPanelOffTiming(APIPNL_POWER_TIMING_SEQ seq); 1181 // MS_U8 MApi_PNL_GetPanelDimCtrl(APIPNL_DIMMING_CTRL dim_type); 1182 // MS_U8** MApi_PNL_GetAllGammaTbl(void); 1183 MS_BOOL MApi_PNL_EnablePanel(MS_BOOL bPanelOn); 1184 // MS_BOOL MApi_PNL_SetGammaTbl(APIPNL_GAMMA_TYPE eGammaType, MS_U8* pu8GammaTab[3], APIPNL_GAMMA_MAPPEING_MODE Gamma_Map_Mode); 1185 // MS_BOOL MApi_PNL_GetGammaTbl(APIPNL_GAMMA_TYPE eGammaType, MS_U8* pu8GammaTab[3], APIPNL_GAMMA_MAPPEING_MODE Gamma_Map_Mode); 1186 // MS_BOOL MApi_PNL_SetGammaValue(MS_U8 u8Channel, MS_U16 u16Offset, MS_U16 u16GammaValue); 1187 // MS_BOOL MApi_PNL_Check_VBY1_Handshake_Status(void); 1188 // void MApi_PNL_SetVideoHWTraining(MS_BOOL bEnable); 1189 // void MApi_PNL_SetOSDHWTraining(MS_BOOL bEnable); 1190 // MS_BOOL MApi_PNL_GetVideoHWTraining_Status(void); 1191 // MS_BOOL MApi_PNL_GetOSDHWTraining_Status(void); 1192 MS_BOOL SYMBOL_WEAK MApi_PNL_GetOutputInterlaceTiming(void); 1193 APIPNL_Result MApi_PNL_Setting(MS_U32 u32Cmd,void *pCmdArgs,MS_U32 u32CmdArgsSize); 1194 1195 #undef INTERFACE 1196 1197 #ifdef __cplusplus 1198 } 1199 #endif 1200 1201 #endif 1202