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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: apiDMX_v2.h 98 // Description: Demux (dmx) api header file 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _DMX_H_ 103 #define _DMX_H_ 104 105 #include "MsDevice.h" 106 107 #ifdef __cplusplus 108 extern "C" 109 { 110 #endif 111 112 113 typedef enum { 114 // General API //*** Args of API *** 115 116 MApi_CMD_DMX_Init = 0, // (DMX_TSPParam*) #0 117 MApi_CMD_DMX_Exit = 1, // pointer to (U32_Result) 118 MApi_CMD_DMX_ForceExit = 2, // pointer to (U32_Result) 119 MApi_CMD_DMX_Suspend = 3, // pointer to (U32_Result) 120 MApi_CMD_DMX_Resume = 4, // pointer to (U32_Result) 121 MApi_CMD_DMX_ChkFwAlive = 5, // pointer to (U32_Result) 122 MApi_CMD_DMX_Reset = 6, // pointer to (U32_Result) 123 MApi_CMD_DMX_SetFwMiuDataAddr = 7, // pointer to (U32_PhyAddr_L, U32_PhyAddr_H, U32_Size, U32_Result) 124 MApi_CMD_DMX_WProtectEnable = 8, // pointer to (PDMX_WP_PARAM) 125 MApi_CMD_DMX_OrzWProtectEnable = 9, // pointer to (U32_bEnable, U32_StartAddr_L, U32_StartAddr_H, U32_EndAddr_L, U32_EndAddr_H, U32_Result) 126 127 MApi_CMD_DMX_ReadDropCount = 10, // pointer to (DMX_POWSTATE_PARAM) #10 128 MApi_CMD_DMX_SetPowerState = 11, 129 MApi_CMD_DMX_SetOwner = 12, // pointer to (U32_Start_Flt_Id, U32_End_Flt_Id, U32_IsOwner, U32_Result) 130 MApi_CMD_DMX_GetCap = 13, // pointer to (DMX_CAP_PARAM) 131 132 MApi_CMD_DMX_SetBurstLen = 14, // pointer to (DMX_BURSTTYPE) 133 134 //Flow Control 135 MApi_CMD_DMX_Flow = 15, // pointer to (DMX_FLOW_PARAM) 136 MApi_CMD_DMX_Flow_ParlInvert = 16, // pointer to (U32_DMX_FLOW, U32_bInvert, U32_Result) 137 MApi_CMD_DMX_Flow_ENABLE = 17, // pointer to (U32_DMX_FLOW, U32_bEnable, U32_Result) 138 139 //STC API 140 MApi_CMD_DMX_GetPcr = 18, // pointer to (U32_Eng_Id, U32_PCR_H, U32_PCR_L, U32_Result) 141 MApi_CMD_DMX_Stc_Get = 19, // pointer to (U32_Eng_Id, U32_STC_H, U32_STC_L, U32_Result) 142 MApi_CMD_DMX_Stc_Set = 20, // pointer to (U32_Eng_Id, U32_STC_H, U32_STC_L, U32_Result) #20 143 MApi_CMD_DMX_Stc_UpdateCtrl = 21, // pointer to (U32_Eng_Id, U32_eStcUpdateCtrlMode, U32_Result) 144 MApi_CMD_DMX_Stc_SetOffset = 22, // pointer to (U32_Eng_Id, U32_STCOffset, U32_bAdd, U32_Result) 145 MApi_CMD_DMX_Stc_ClkAdjust = 23, // pointer to (U32_Eng_Id, U32_Mutipletor64, U32_Result) 146 147 //Filter API 148 MApi_CMD_DMX_Open = 24, // pointer to (DMX_FLT_TYPE_PARAM) 149 MApi_CMD_DMX_Close = 25, // pointer to (U32_DmxId, U32_Result) 150 MApi_CMD_DMX_Start = 26, // pointer to (U32_DmxId, U32_Result) 151 MApi_CMD_DMX_Stop = 27, // pointer to (U32_DmxId, U32_Result) 152 MApi_CMD_DMX_Info = 28, // pointer to (DMX_FLT_INFO_PARAM) 153 MApi_CMD_DMX_Pid = 29, // pointer to (U32_DmxId, U32_Pid, U32_bSet, U32_Result) 154 MApi_CMD_DMX_IsStart = 30, // pointer to (U32_DmxId, U32_bEnable, U32_Result) #30 155 MApi_CMD_DMX_CopyData = 31, // pointer to (DMX_FLT_COPY_PARAM) 156 MApi_CMD_DMX_Proc = 32, // pointer to (DMX_FLT_EVENT_PARAM) 157 MApi_CMD_DMX_ChangeFltSrc = 33, // pointer to (DMX_FLT_TYPE_PARAM) 158 MApi_CMD_DMX_GetOwner = 34, // pointer to (U32_DmxId, U32_bOwner, U32_Result) 159 160 MApi_CMD_DMX_GetPESScmbSts = 35, // pointer to (U32_DmxId, U32_ScmbSts, U32_Result) 161 MApi_CMD_DMX_GetTsScmbSts = 36, // pointer to (U32_DmxId, U32_ScmbSts, U32_Result) 162 163 // Section API 164 MApi_CMD_DMX_Sec_Reset = 37, // pointer to (U32_DmxId, U32_Result, U32_Result) 165 MApi_CMD_DMX_Sec_ReadAddr = 38, // pointer to (U32_DmxId, U32_PhyReadAddr_L, U32_PhyReadAddr_H, U32_bSet, U32_Result) 166 MApi_CMD_DMX_Sec_GetWriteAddr = 39, // pointer to (U32_DmxId, U32_PhyWriteAddr_L, U32_PhyWriteAddr_H, U32_Result) 167 MApi_CMD_DMX_Sec_GetStartAddr = 40, // pointer to (U32_DmxId, U32_PhyWriteAddr_L, U32_PhyWriteAddr_H, U32_Result) #40 168 MApi_CMD_DMX_Sec_GetEndAddr = 41, // pointer to (U32_DmxId, U32_PhyEndAddr_L, U32_PhyWriteAddr_H, U32_Result) 169 MApi_CMD_DMX_Sec_SetPattern = 42, // pointer to (DMX_FLT_SEC_PAT_PARAM) 170 171 //TTX API 172 MApi_CMD_DMX_GetTTXWrite = 43, // pointer to (U32_DmxId, U32_PhyWriteAddr, U32_Result) 173 MApi_CMD_DMX_GetAccess = 44, // pointer to (U32_Try, U32_Result) 174 MApi_CMD_DMX_ReleaseAccess = 45, 175 176 // AVFIFO control 177 MApi_CMD_DMX_AVFIFO_Reset = 46, // pointer to (DMX_AVFIFO_PARAM), u32Data is for setting bFlush 178 MApi_CMD_DMX_AVFIFO_Status = 47, // pointer to (DMX_AVFIFO_PARAM), u32Data is for getting FifoLevel 179 MApi_CMD_DMX_RemoveDupAVFifoPkt = 48, // pointer to (DMX_AVFIFO_DROP_PARAM) 180 MApi_CMD_DMX_AUBD_Enable = 49, // pointer to (U32_bEnable, U32_Result) 181 182 //PVR Playback API 183 MApi_CMD_DMX_FI_PlayStamp = 50, // pointer to (U32_EngId, U32_Stamp, U32_bSet, U32_Result) #50 184 MApi_CMD_DMX_FI_TimestampMode = 51, // pointer to (U32_EngId, U32_bEnable, U32_Result) 185 MApi_CMD_DMX_FI_SetPlaybackStampClk = 52, // pointer to (DMX_TIMESTAMP_CLK_PARAM) 186 187 // PVR Engine API 188 MApi_CMD_DMX_Pvr_Open = 53, // pointer to (DMX_PVR_INFO_PARAM) 189 MApi_CMD_DMX_Pvr_Close = 54, // pointer to (U32_EngId, U32_Result) 190 MApi_CMD_DMX_Pvr_PidOpen = 55, // pointer to (DMX_PVR_FLTTYPE_PARAM) 191 MApi_CMD_DMX_Pvr_PidClose = 56, // pointer to (U32_EngId, U32_DmxId, U32_bDecryptRec, U32_Result) 192 MApi_CMD_DMX_Pvr_Start = 57, // pointer to (U32_EngId, MS_U32_bRecAll, U32_bDecryptRec, U32_Result) 193 MApi_CMD_DMX_Pvr_Stop = 58, // pointer to (U32_EngId, U32_bDecryptRec, U32_Result) 194 MApi_CMD_DMX_Pvr_GetWriteAddr = 59, // pointer to (U32_EngId, U32_PhyWriteAddr_L, U32_PhyWriteAddr_H, U32_Result) 195 MApi_CMD_DMX_Pvr_SetPktMode = 60, // pointer to (U32_EngId, U32_bSet, U32_Result) #60 196 MApi_CMD_DMX_Pvr_SetRecordStamp = 61, // pointer to (U32_EngId, U32_Stamp, U32_Result) 197 MApi_CMD_DMX_Pvr_GetRecordStamp = 62, // pointer to (U32_EngId, U32_Stamp, U32_Result) 198 MApi_CMD_DMX_Pvr_SetMobfKey = 63, // pointer to (U32_EngId, U32_Key0, U32_Key1, U32_bEnable, U32_Result) 199 MApi_CMD_DMX_Pvr_SetRecordStampClk = 64, // pointer to (DMX_TIMESTAMP_CLK_PARAM) 200 201 // File-in Engine API 202 MApi_CMD_DMX_FI_Start = 65, // pointer to (DMX_FILE_START_PARAM) 203 MApi_CMD_DMX_FI_Stop = 66, // pointer to (U32_EngId, U32_Result) 204 MApi_CMD_DMX_FI_Info = 67, // poiinter to (DMX_FILE_INFO_PARAM) 205 MApi_CMD_DMX_FI_Pause = 68, // pointer to (U32_EngId, U32_Result) 206 MApi_CMD_DMX_FI_Resume = 69, // pointer to (U32_EngId, U32_Result) 207 MApi_CMD_DMX_FI_IsIdle = 70, // pointer to (U32_EngId, U32_bIdle, U32_Result) #70 208 MApi_CMD_DMX_FI_IsBusy = 71, // pointer to (U32_EngId, U32_bBusy, U32_Result) 209 MApi_CMD_DMX_FI_IsPause = 72, // pointer to (U32_EngId, U32_bPause, U32_Result) 210 MApi_CMD_DMX_FI_CmdQReset = 73, // pointer to (U32_EngId, U32_Result) 211 MApi_CMD_DMX_FI_CmdQGetEmptyNum = 74, // pointer to (U32_EngId, U32_EmptyNum, U32_Result) 212 MApi_CMD_DMX_FI_BypassFileTimestamp = 75, // pointer to (U32_EngId, U32_bByPass, U32_Result) 213 MApi_CMD_DMX_FI_CmdQGetFifoLevel = 76, // pointer to (U32_EngId, U32_WLevel, U32_Result) 214 MApi_CMD_DMX_FI_GetFileTimeStamp = 77, // pointer to (U32_EngId, U32_TimeStamp, U32_Result) 215 MApi_CMD_DMX_FI_GetReadAddr = 78, // pointer to (U32_EngId, U32_PhyReadAddr_L, U32_PhyReadAddr_H, U32_Result) 216 MApi_CMD_DMX_FI_SetMobfKey = 79, // pointer to (U32_EngId, U32_Key, U32_bEnable, U32_Result) 217 218 //MMFI API 219 MApi_CMD_DMX_MMFI_IsIdle = 80, // pointer to (U32_MMFIPath, U32_bIdle, U32_Result) #80 220 MApi_CMD_DMX_MMFI_IsBusy = 81, // pointer to (U32_MMFIPath, U32_bBusy, U32_Result) 221 MApi_CMD_DMX_MMFI_CmdQReset = 82, // pointer to (U32_DMX_MMFI_PATH, U32_Result) 222 MApi_CMD_DMX_MMFI_GetEmptyNum = 83, // pointer to (U32_MMFIPath, U32_EmptyNum, U32_Result) 223 MApi_CMD_DMX_MMFI_Start = 84, // pointer to (DMX_FILE_START_PARAM) 224 MApi_CMD_DMX_MMFI_GetFileTimeStamp = 85, // pointer to (U32_EngId, U32_TimeStamp, U32_Result) 225 226 MApi_CMD_DMX_MMFI_PidOpen = 86, // pointer to (DMX_MMFI_FLT_PARAM) 227 MApi_CMD_DMX_MMFI_PidClose = 87, // pointer to (U32_EngId, U32_DmxId, U32_Result) 228 MApi_CMD_DMX_MMFI_GetFifoLevel = 88, // pointer to (U32_EngId, U32_WLevel, U32_Result) 229 MApi_CMD_DMX_MMFI_PlayStamp_Set = 89, // pointer to (U32_EngId, U32_Stamp, U32_Result) 230 MApi_CMD_DMX_MMFI_PlayStamp_Get = 90, // pointer to (U32_EngId, U32_Stamp, U32_Result) #90 231 MApi_CMD_DMX_MMFI_SetTimeStampClk = 91, // pointer to (U32_MMFIPath, U32_DMX_TimeStamp_Clk, U32_Result) 232 MApi_CMD_DMX_MMFI_RemoveDupAVPkt = 92, // pointer to (DMX_AVFIFO_DROP_PARAM) 233 MApi_CMD_DMX_MMFI_SetMOBFKey = 93, // pointer to (U32_EngId, U32_Key, U32_bEnable, U32_Result) 234 235 //Debug API 236 MApi_CMD_DMX_SetDbgLevel = 94, // pointer to (U32_DMX_DBGMSG_LEVEL, U32_Result) 237 MApi_CMD_DMX_GetFwVer = 95, // pointer to (U32_FwVer) 238 239 MApi_CMD_DMX_CmdRun = 96, // pointer to (DMX_CMDRUN_PARAM) 240 241 //Utopia 1.0 compatible API 242 MApi_CMD_DMX_SetFw = 97, // pointer to (U32_FWAddr_L, U32_FWAddr_H, U32_FWSize, U32_Result) 243 MApi_CMD_DMX_SetHK = 98, // pointer to (U32_bHK, U32_Result) 244 MApi_CMD_DMX_Init_1_0 = 99, // U32_Result 245 MApi_CMD_DMX_TSPInit_1_0 = 100, // (DMX_TSPParam*) #100 246 MApi_CMD_DMX_ReleseHWSemp = 101, // U32_Result 247 MApi_CMD_DMX_GetLibVer = 102, // const MSIF_Version ** 248 MApi_CMD_DMX_STC64ModeEnable = 103, // pointer to (U32_bEnablem, U32_Result) 249 250 //Merge stream API 251 MApi_CMD_DMX_SetPktMode = 104, //// pointer to (DMX_PKT_MODE_PARAM) 252 MApi_CMD_DMX_SetMergeStrSync = 105, /// pointer to (U32_SrcID, U32_SyncByte, U32_Result) 253 254 MApi_CMD_DMX_PVR_Flow = 106, /// pointer to (U32_PVR_ENG, DMX_PVRFLOW_PARAM) 255 256 //TSO API 257 MApi_CMD_DMX_TSO_FileInfo = 107, /// poiinter to (DMX_FILE_INFO_PARAM) 258 MApi_CMD_DMX_TSO_FileIsIdle = 108, /// pointer to (U32_EngId, U32_bIdle, U32_Result) 259 MApi_CMD_DMX_TSO_FileGetCmdQEmptyNum = 109, /// pointer to (U32_EngId, U32EmptyNum, U32_Result) 260 MApi_CMD_DMX_TSO_FileStart = 110, /// pointer to (U32_EngId, U32Address, U32Size, U32_Result) #110 261 MApi_CMD_DMX_TSO_FileStop = 111, /// pointer to (U32_EngId, U32_Result) 262 MApi_CMD_DMX_TSO_FilePlayStamp = 112, /// pointer to (U32_EngId, U32Stamp, U32_bEnable, U32_Result) 263 MApi_CMD_DMX_TSO_FileGetTimeStamp = 113, /// pointer to (U32_EngId, U32Stamp, U32_Result) 264 MApi_CMD_DMX_TSO_FileBypassStamp = 114, /// pointer to (U32_EngId, U32_bBypass, U32_Result) 265 MApi_CMD_DMX_TSO_FileTimeStampEnable = 115, /// pointer to (U32_EngId, U32_bEnable, U32_Result) 266 267 // DBG INFO API 268 MApi_CMD_DMX_DBG_GET_DISCONCNT = 116, /// poiinter to (DMX_PKT_DISCONCNT_PARAM) 269 MApi_CMD_DMX_DBG_GET_DROPPKTCNT = 117, /// poiinter to (DMX_PKT_DROPCNT_PARAM) 270 MApi_CMD_DMX_DBG_GET_LOCKPKTCNT = 118, /// poiinter to (DMX_PKT_LOCKCNT_PARAM) 271 MApi_CMD_DMX_DBG_GET_AVPKTCNT = 119, /// poiinter to (DMX_PKT_AVCNT_PARAM) 272 273 MApi_CMD_DMX_GET_SECTEI_PKTCNT = 120, /// poiinter to (DMX_PKT_SECTEI_PARAM) #120 274 MApi_CMD_DMX_RESET_SECTEI_PKTCNT = 121, /// poiinter to (DMX_FILTER_TYPE) 275 MApi_CMD_DMX_GET_SECDISCON_PKTCNT = 122, /// poiinter to (U32_DMXID, U32_PKTCNT, U32_Result) 276 MApi_CMD_DMX_RESET_SECDISCON_PKTCNT = 123, /// poiinter to (U32_DMXID, U32_Result) 277 278 // BOX Series only 279 MApi_CMD_DMX_Pvr_CBSize = 124, /// poiinter to (U32_ENGID, U32_CBSIZE, U32_bSet, U32_Result) 280 MApi_CMD_DMX_Pvr_SetCaMode = 125, /// poiinter to (U32_ENGID, U32_CAMODE, U32_bSPSENABLE, U32_Result) 281 MApi_CMD_DMX_Pvr_IsStart = 126, /// poiinter to (U32_ENGID, U32_bIsStart, U32_Result) 282 283 //New 284 MApi_CMD_DMX_TSO_OutClk = 127, /// pointer to (DMX_TSO_OUTCLK_PARAM) 285 MApi_CMD_DMX_STCEng_Sel = 128, /// pointer to (U32_eFltSrc, U32_u32StcEng, U32_Result) 286 MApi_CMD_DMX_TSO_LocStrId = 129, /// pointer to (DMX_TSO_LOCSTRID_PARAM) 287 MApi_CMD_DMX_TSO_CmdQReset = 130, /// pointer to (U32_Eng, U32_Result) #130 288 MApi_CMD_DMX_GetFltScmbSts = 131, /// pointer to (U32_FltSrc, U32_FltGroupId, U32_PidFltId, U32_ScmbSts, U32_Result) 289 290 //FQ 291 MApi_CMD_DMX_FQ_SetFltRushPass = 132, 292 MApi_CMD_DMX_FQ_Init = 133, 293 MApi_CMD_DMX_FQ_Exit = 134, 294 MApi_CMD_DMX_FQ_RushEnable = 135, 295 MApi_CMD_DMX_FQ_SkipRushData = 136, 296 297 //TSO2 298 MApi_CMD_DMX_TSO_SvqBufSet = 150, /// pointer to (U32_Eng, U32_Addr_L, U32_Addr_H, U32Size, U32_Result) #150 299 MApi_CMD_DMX_TSO_InputCfg = 151, /// pointer to (DMX_TSO_Input_Cfg) 300 MApi_CMD_DMX_TSO_OutputCfg = 152, /// pointer to (DMX_TSO_OutputCfg) 301 MApi_CMD_DMX_TSO_OutputEn = 153, /// pointer to (U32_ENG, U32_Enable, U32_Result) 302 MApi_CMD_DMX_TSO_PidOpen = 154, /// pointer to (U32_ENG, U32_eTSOInSrc, U32_Pid, U32_FilterID, U32_Result) 303 MApi_CMD_DMX_TSO_PidClose = 155, /// pointer to (U32_ENG, U32_FilterID, U32_Result) 304 MApi_CMD_DMX_TSO_FI_GetReadAddr = 156, /// pointer to (U32_EngId, U32_PhyReadAddr, U32_Result) 305 306 //Merge Stream 307 MApi_CMD_DMX_MStr_SyncBy = 170, /// pointer to (DMX_MSTR_SYNCBY_PARAM) #170 308 309 //2K only 310 MApi_CMD_DMX_WaitTspCbEvt = 190, /// pointer to (DMX_TSP_IOSIGNAL) #190 311 312 //Misc 313 MApi_CMD_DMX_GetIntCnt = 200, /// pointer to (U32_CNT, U32_Result) #200 314 MApi_CMD_DMX_DropEn = 201, /// pointer to (U32_ENABLE, U32_Result) 315 MApi_CMD_DMX_TeiRmErrPkt = 202, /// pointer to (U32_DMX_TEI_RmPktType, U32_BOOL_bEnable, U32_Result) 316 MApi_CMD_DMX_SetFwDbgParam = 203, /// pointer to (U32_ADDR_L, U32_ADDR_H, U32_SIZE, U32_DBGWORD, U32_Result) 317 MApi_CMD_DMX_PVR_MOBFEn = 204, /// pointer to (U32_ENABLE, U32_KEY0, U32_KEY1, U32_Result) 318 MApi_CMD_DMX_Get_DbgPortInfo = 205, /// pointer to (U32_ENABLE, U32_KEY0, U32_KEY1, U32_Result) 319 MApi_CMD_DMX_Open_MultiFlt = 206, /// pointer to (U32_DmxFltType, U32_DMXID, U32_u8TargetDmxId, U32_Result) 320 MApi_CMD_DMX_Pvr_Pause = 207, /// pointer to (U32_EngId, U32_bPAUSE, U32_Result) 321 MApi_CMD_DMX_Pvr_Pid = 208, /// pointer to (U32_EngId, U32_u8DmxId, U32_Pid, U32_bSet, U32_Result) 322 MApi_CMD_DMX_OutPadCfg = 209, /// pointer to (DMX_OutputPad_Cfg) 323 MApi_CMD_DMX_GetCapEx = 210, // pointer to (DMX_CAP_EX_PARAM) #210 324 MApi_CMD_DMX_TsOutPhase = 211, /// pointer to (U32_U16VAL, U32_bEnable, U32_Reserved, , U32_Result) 325 MApi_CMD_DMX_FlowDscmbEng = 212, /// pointer to (DMX_FLOW_DSCMBENG_PARAM) 326 MApi_CMD_DMX_DropScmbPkt = 213, /// pointer to (DMX_DROP_SCMB_PARAM) 327 328 //MMFI part2 329 MApi_CMD_DMX_MMFI_Info = 220, /// pointer to (DMX_FILE_INFO_PARAM) #220 330 MApi_CMD_DMX_MMFI_BypassStamp = 221, /// pointer to (U32_DbgSel, U32_DbgInfo, U32_Result) 331 MApi_CMD_DMX_MMFI_Timestamp_En = 222, /// pointer to (U32_ePath, U32_bEnable, U32_Result) 332 333 //Filein PVR 334 MApi_CMD_DMX_File_PVR_PidOpen = 230, /// pointer to (U32_EngId, U32_Pid, U32_DMXId, U32_ShareKeyType, U32_Result) #230 335 MApi_CMD_DMX_File_PVR_PidClose = 231, /// pointer to (U32_EngId, U32_DMXId, U32_Result) 336 MApi_CMD_DMX_File_PVR_Start = 232, /// pointer to (U32_EngId, U32_bPvrAll, U32_Result) 337 MApi_CMD_DMX_File_PVR_Stop = 233, /// pointer to (U32_EngId, U32_Result) 338 339 340 /*****************New command******************/ 341 // File-in Engine API 342 MApi_CMD_DMX_FI_Eng_Info = 267, // poiinter to (DMX_FILE_INFO_PARAM) 343 /***********************************************/ 344 345 } eDmxIoctlOpt; 346 347 //------------------------------------------------------------------------------------------------- 348 // Macros 349 //------------------------------------------------------------------------------------------------- 350 351 352 //------------------------------------------------------------------------------------------------- 353 // Type and Structure Declaration 354 //------------------------------------------------------------------------------------------------- 355 356 /// DMX Output destination 357 typedef enum 358 { 359 DMX_FLOW_OUT_LIVE0 = 0, 360 DMX_FLOW_OUT_LIVE1 = 1, 361 DMX_FLOW_OUT_LIVE2 = 2, 362 DMX_FLOW_OUT_LIVE3 = 3, 363 364 DMX_FLOW_OUT_FILE0 = 4, 365 DMX_FLOW_OUT_FILE1 = 5, 366 DMX_FLOW_OUT_FILE2 = 6, 367 DMX_FLOW_OUT_FILE3 = 7, 368 369 DMX_FLOW_OUT_PVR0 = 8, 370 DMX_FLOW_OUT_PVR1 = 9, 371 DMX_FLOW_OUT_PVR2 = 10, 372 DMX_FLOW_OUT_PVR3 = 11, 373 DMX_FLOW_OUT_PVR4 = 12, 374 DMX_FLOW_OUT_PVR5 = 13, 375 DMX_FLOW_OUT_PVRCB = 14, 376 377 DMX_FLOW_OUT_MMFIAU = 15, 378 DMX_FLOW_OUT_MMFI0 = DMX_FLOW_OUT_MMFIAU, 379 DMX_FLOW_OUT_MMFIV3D = 16, 380 DMX_FLOW_OUT_MMFI1 = DMX_FLOW_OUT_MMFIV3D, 381 382 } DMX_FLOW_OUTPUT; 383 384 385 typedef struct _DMX_CAP_PARAM 386 { 387 MS_U32 u32Res; 388 DMX_QUERY_TYPE Quetype; 389 void* pdata; 390 391 }DMX_CAP_PARAM, *PDMX_CAP_PARAM; 392 393 typedef struct _DMX_CAP_EX_PARAM 394 { 395 MS_U32 u32Res; 396 MS_S32 InputStrLen; 397 MS_S32 OutputSize; 398 char* StrQuetype; 399 void* pdata; 400 }DMX_CAP_EX_PARAM, *PDMX_CAP_EX_PARAM; 401 402 typedef struct _DMX_FLOW_PARAM 403 { 404 MS_U32 u32Res; 405 MS_U32 u32CAEngSel; // 0xFFFFFFFF:None CA 406 DMX_FLOW DmxFlow; 407 DMX_FLOW_INPUT DmxFlowInput; 408 MS_BOOL bClkInv; 409 MS_BOOL bExtSync; 410 MS_BOOL bParallel; 411 MS_BOOL bSet; 412 413 }DMX_FLOW_PARAM, *PDMX_FLOW_PARAM; 414 415 typedef struct _DMX_PVRFLOW_PARAM 416 { 417 MS_U32 u32Res; 418 DMX_PVR_ENG eEng; 419 DMX_TSIF eSrcTSIf; 420 MS_BOOL bSet; 421 MS_BOOL bDscmbRec; 422 423 }DMX_PVRFLOWPARAM, *PDMX_PVRFLOW_PARAM; 424 425 typedef struct _DMX_FLT_TYPE_PARAM 426 { 427 MS_U32 u32Res; 428 DMX_FILTER_TYPE DmxFltType; 429 MS_U32 u32DmxId; 430 431 }DMX_FLT_TYPE_PARAM, *PDMX_FLT_TYPE_PARAM; 432 433 typedef struct _DMX_FLT_INFO_PARAM 434 { 435 MS_U32 u32Res; 436 MS_U32 u32DmxId; 437 DMX_Flt_info* pDmxFltInfo; 438 DMX_FILTER_TYPE* pDmxFltType; 439 MS_BOOL bSet; 440 441 }DMX_FLT_INFO_PARAM, *PDMX_FLT_INFO_PARAM; 442 443 typedef struct _DMX_FLT_COPYDATA_PARAM 444 { 445 MS_U32 u32Res; 446 MS_U32 u32DmxId; 447 MS_U32 u32BufSize; 448 MS_U32 u32ActualSize; 449 MS_U32 u32RmnSize; 450 DMX_CheckCb pfCheckCB; 451 MS_U8* pu8Buf; 452 453 }DMX_FLT_COPY_PARAM, *PDMX_FLT_COPY_PARAM; 454 455 typedef struct _DMX_FLT_EVENT_PARAM 456 { 457 MS_U32 u32Res; 458 MS_U32 u32DmxId; 459 DMX_EVENT* pEvent; 460 461 }DMX_FLT_EVENT_PARAM, *PDMX_FLT_EVENT_PARAM; 462 463 typedef struct _DMX_FLT_SEC_PAT_PARAM 464 { 465 MS_U32 u32Res; 466 MS_U32 u32DmxId; 467 MS_U32 u32MatchSize; 468 MS_U8* pu8Pattern; 469 MS_U8* pu8Mask; 470 MS_U8* pu8NotMask; 471 }DMX_FLT_SEC_PAT_PARAM, *PDMX_FLT_SEC_PAT_PARAM; 472 473 typedef struct _DMX_AVFIFO_PARAM 474 { 475 DMX_FILTER_TYPE DmxFltType; 476 MS_U32 u32Data; 477 MS_U32 u32Res; 478 }DMX_AVFIFO_PARAM, *PDMX_AVFIFO_PARAM; 479 480 typedef struct _DMX_AVFIFO_DROP_PARAM 481 { 482 MS_U32 u32Res; 483 DMX_FILTER_TYPE DmxFltType; 484 MS_BOOL bAllFifo; 485 MS_BOOL bEnable; 486 487 }DMX_AVFIFO_DROP_PARAM, *PDMX_AVFIFO_DROP_PARAM; 488 489 490 typedef struct _DMX_TIMESTAM_CLK_PARAM 491 { 492 MS_U32 u32Res; 493 MS_U32 u32EngId; 494 DMX_TimeStamp_Clk eClk; 495 496 }DMX_TIMESTAMP_CLK_PARAM, *PDMX_TIMESTAMP_CLK_PARAM; 497 498 typedef struct _DMX_PVR_INFO_PARAM 499 { 500 MS_U32 u32Res; 501 MS_U32 u32EngId; 502 DMX_Pvr_info* pPvrInfo; 503 504 }DMX_PVR_INFO_PARAM, *PDMX_PVR_INFO_PARAM; 505 506 typedef struct _DMX_PVR_FLTTYPE_PARAM 507 { 508 MS_U32 u32Res; 509 MS_U32 u32EngId; 510 MS_U32 u32DmxId; 511 MS_U32 u32Pid; 512 DMX_FILTER_TYPE FltSrc; 513 MS_U32 u32CAEngSel; // 0xFFFFFFFF:No Dscmb 514 MS_U32 u32SelShareFlt; //0: Not use share dscmb filter 515 516 }DMX_PVR_FLTTYPE_PARAM, *PDMX_PVR_FLTTYPE_PARAM; 517 518 typedef struct _DMX_FILE_START_PARAM 519 { 520 MS_U32 u32Res; 521 MS_U32 u32EngId; 522 DMX_FILEIN_DST Dst; 523 MS_PHY pBuf; 524 MS_U32 u32BufSize; 525 526 }DMX_FILE_START_PARAM, *PDMX_FILE_START_PARAM; 527 528 typedef struct _DMX_FILE_INFO_PARAM 529 { 530 MS_U32 u32Res; 531 MS_U32 u32EngId; 532 DMX_Filein_info* pFileinInfo; 533 534 }DMX_FILE_INFO_PARAM, *PDMX_FILE_INFO_PARAM; 535 536 typedef struct _DMX_MMFI_FLT_PARAM 537 { 538 MS_U32 u32Res; 539 MS_U32 u32DmxId; 540 MS_U32 u32Pid; 541 DMX_MMFI_FLTTYPE flttype; 542 DMX_MMFI_PATH MMFIPath; 543 }DMX_MMFI_FLT_PARAM, *PDMX_MMFI_FLT_PARAM; 544 545 typedef struct _DMX_CMDRUN_PARAM 546 { 547 MS_U32 u32Res; 548 MS_U32 u32Cmd; 549 MS_U32 u32Config; 550 MS_U32 u32DataNum; 551 void* pData; 552 }DMX_CMDRUN_PARAM, *PDMX_CMDRUN_PARAM; 553 554 typedef struct _DMX_POWSTATE_PARAM 555 { 556 MS_U32 u32Res; 557 EN_POWER_MODE u16PowerState; 558 MS_PHY u32FWAddr; 559 MS_U32 u32FWSize; 560 }DMX_POWSTATE_PARAM, *PDMX_POWSTATE_PARAM; 561 562 typedef struct _DMX_MMFI_START_PARAM 563 { 564 MS_U32 u32Res; 565 MS_U32 u32EngId; 566 DMX_MMFI_DST Dst; 567 MS_PHY pBuf; 568 MS_U32 u32BufSize; 569 570 }DMX_MMFI_START_PARAM, *PDMX_MMFI_START_PARAM; 571 572 typedef struct _DMX_PKT_MODE_PARAM 573 { 574 MS_U32 u32Res; 575 DMX_FLOW eFlow; 576 DMX_PacketMode ePktMode; 577 }DMX_PKT_MODE_PARAM, *PDMX_PKT_MODE_PARAM; 578 579 typedef struct _DMX_PKT_DISCONCNT_PARAM 580 { 581 MS_U32 u32Res; 582 DMX_DisContiCnt_info* pInfo; 583 MS_U32 u32Cnt; 584 }DMX_PKT_DISCONCNT_PARAM, *PDMX_PKT_DISCONCNT_PARAM; 585 586 typedef struct _DMX_PKT_DROPCNT_PARAM 587 { 588 MS_U32 u32Res; 589 DMX_DropPktCnt_info* pInfo; 590 MS_U32 u32Cnt; 591 }DMX_PKT_DROPCNT_PARAM, *PDMX_PKT_DROPCNT_PARAM; 592 593 typedef struct _DMX_PKT_LOCKCNT_PARAM 594 { 595 MS_U32 u32Res; 596 DMX_LockPktCnt_info* pInfo; 597 MS_U32 u32Cnt; 598 }DMX_PKT_LOCKCNT_PARAM, *PDMX_PKT_LOCKCNT_PARAM; 599 600 typedef struct _DMX_PKT_AVCNT_PARAM 601 { 602 MS_U32 u32Res; 603 DMX_AVPktCnt_info* pInfo; 604 MS_U32 u32Cnt; 605 }DMX_PKT_AVCNT_PARAM, *PDMX_PKT_AVCNT_PARAM; 606 607 typedef struct _DMX_PKT_SECTEI_PARAM 608 { 609 MS_U32 u32Res; 610 DMX_FILTER_TYPE eType; 611 MS_U32 u32Cnt; 612 }DMX_PKT_SECTEI_PARAM, *PDMX_PKT_SECTEI_PARAM; 613 614 typedef struct _DMX_WP_PARAM 615 { 616 MS_BOOL bEnable; 617 MS_PHY* pu32StartAddr; 618 MS_PHY* pu32EndAddr; 619 }DMX_WP_PARAM, *PDMX_WP_PARAM; 620 621 typedef struct _DMX_TSO_OUTCLK_PARAM 622 { 623 MS_U32 u32Res; 624 MS_U32 u32Eng; 625 DMX_TSO_OutClk eTsoOutClk; 626 DMX_TSO_OutClkSrc eTsoOutClkSrc; 627 MS_U16 u16DivNum; 628 MS_BOOL bClkInv; 629 MS_BOOL bSet; 630 }DMX_TSO_OUTCLK_PARAM, *PDMX_TSO_OUTCLK_PARAM; 631 632 typedef struct _DMX_TSO_LOCSTRID_PARAM 633 { 634 MS_U32 u32Res; 635 MS_U8 u8Eng; 636 DMX_TSIF eIf; 637 MS_U8* pu8StrId; 638 MS_BOOL bSet; 639 }DMX_TSO_LOCSTRID_PARAM, *PDMX_TSO_LOCSTRID_PARAM; 640 641 typedef struct _DMX_FQ_INIT_PARAM 642 { 643 MS_U32 u32Res; 644 MS_U32 u32Eng; 645 DMX_FQ_Info* pInfo; 646 }DMX_FQ_INIT_PARAM, *PDMX_FQ_INIT_PARAM; 647 648 typedef struct _DMX_FQ_SKIP_RUSH_DATA_PARAM 649 { 650 MS_U32 u32Res; 651 MS_U32 u32Eng; 652 DMX_FQ_SkipPath eSkipPath; 653 }DMX_FQ_SKIP_RUSH_DATA_PARAM, *PDMX_FQ_SKIP_RUSH_DATA_PARAM; 654 655 typedef struct _DMX_MSTR_SYNCBY_PARAM 656 { 657 MS_U32 u32Res; 658 DMX_TSIF eIf; 659 MS_U8 u8StrId; 660 MS_U8* pu8SyncByte; 661 MS_BOOL bSet; 662 }DMX_MSTR_SYNCBY_PARAM, *PDMX_MSTR_SYNCBY_PARAM; 663 664 typedef struct _DMX_OutputPad_Cfg 665 { 666 MS_U32 u32Res; 667 DMX_FLOW_OUTPUT_PAD eOutPad; 668 DMX_FLOW_INPUT eInSrcPad; 669 MS_BOOL bInParallel; 670 MS_U32 u32ResvNum; 671 MS_U32* pu32Resv; 672 }DMX_OutputPad_Cfg, *PDMX_OutputPad_Cfg; 673 674 typedef struct _DMX_FLOW_DSCMBENG_PARAM 675 { 676 MS_U32 u32Res; 677 MS_U32 u32DscmbEng; 678 DMX_TSIF eTsif; 679 MS_BOOL bSet; 680 }DMX_FLOW_DSCMBENG_PARAM, *PDMX_FLOW_DSCMBENG_PARAM; 681 682 typedef struct _DMX_DROP_SCMB_PKT_PARAM 683 { 684 MS_U32 u32Res; 685 DMX_FILTER_TYPE eType; 686 MS_BOOL bEnable; 687 }DMX_DROP_SCMB_PKT_PARAM,*PDMX_DROP_SCMB_PKT_PARAM; 688 689 690 #ifdef __cplusplus 691 } 692 #endif 693 694 695 #endif //_DMX_H_ 696 697 698