xref: /utopia/UTPA2-700.0.x/projects/project/kano_android/drvDTC.h (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)
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93 ////////////////////////////////////////////////////////////////////////////////
94 #ifndef _DRV_DTC_H_
95 #define _DRV_DTC_H_
96 
97 #define UTOPIA 0
98 #define UTOPIA2L 1
99 
100 #ifdef UTOPIA_TYPE
101     #if (UTOPIA_TYPE == UTOPIA2L)
102         #if defined (__aarch64__)
103         #define DTC_MS_U32_d "d"
104         #define DTC_MS_U32_i "i"
105         #define DTC_MS_U32_x "x"
106         #define DTC_MS_U32_X "X"
107         #define DTC_MS_U32_u "u"
108 
109         #define DTC_MS_U64_d "ld"
110         #define DTC_MS_U64_i "li"
111         #define DTC_MS_U64_x "lx"
112         #define DTC_MS_U64_X "lX"
113         #define DTC_MS_U64_u "lu"
114 
115         #define DTC_MS_S32_d "d"
116         #define DTC_MS_S32_i "i"
117         #define DTC_MS_S32_x "x"
118         #define DTC_MS_S32_X "X"
119         #define DTC_MS_S32_u "u"
120 
121         #define DTC_MS_S64_d "ld"
122         #define DTC_MS_S64_i "li"
123         #define DTC_MS_S64_x "lx"
124         #define DTC_MS_S64_X "lX"
125         #define DTC_MS_S64_u "lu"
126 
127         #define DTC_MS_PHY_d DTC_MS_U64_d
128         #define DTC_MS_PHY_i DTC_MS_U64_i
129         #define DTC_MS_PHY_x DTC_MS_U64_x
130         #define DTC_MS_PHY_X DTC_MS_U64_X
131         #define DTC_MS_PHY_u DTC_MS_U64_u
132 
133         #define DTC_MS_VIRT_d "zd"
134         #define DTC_MS_VIRT_i "zi"
135         #define DTC_MS_VIRT_x "zx"
136         #define DTC_MS_VIRT_X "zX"
137         #define DTC_MS_VIRT_u "zu"
138 
139         #define DTC_MS_PHYADDR_d "zd"
140         #define DTC_MS_PHYADDR_i "zi"
141         #define DTC_MS_PHYADDR_x "zx"
142         #define DTC_MS_PHYADDR_X "zX"
143         #define DTC_MS_PHYADDR_u "zu"
144         #else
145         #define DTC_MS_U32_d "d"
146         #define DTC_MS_U32_i "i"
147         #define DTC_MS_U32_x "x"
148         #define DTC_MS_U32_X "X"
149         #define DTC_MS_U32_u "u"
150 
151         #define DTC_MS_U64_d "lld"
152         #define DTC_MS_U64_i "lli"
153         #define DTC_MS_U64_x "llx"
154         #define DTC_MS_U64_X "llX"
155         #define DTC_MS_U64_u "llu"
156 
157         #define DTC_MS_S32_d "d"
158         #define DTC_MS_S32_i "i"
159         #define DTC_MS_S32_x "x"
160         #define DTC_MS_S32_X "X"
161         #define DTC_MS_S32_u "u"
162 
163         #define DTC_MS_S64_d "lld"
164         #define DTC_MS_S64_i "lli"
165         #define DTC_MS_S64_x "llx"
166         #define DTC_MS_S64_X "llX"
167         #define DTC_MS_S64_u "llu"
168 
169         #define DTC_MS_PHY_d DTC_MS_U64_d
170         #define DTC_MS_PHY_i DTC_MS_U64_i
171         #define DTC_MS_PHY_x DTC_MS_U64_x
172         #define DTC_MS_PHY_X DTC_MS_U64_X
173         #define DTC_MS_PHY_u DTC_MS_U64_u
174 
175         #define DTC_MS_VIRT_d "zd"
176         #define DTC_MS_VIRT_i "zi"
177         #define DTC_MS_VIRT_x "zx"
178         #define DTC_MS_VIRT_X "zX"
179         #define DTC_MS_VIRT_u "zu"
180 
181         #define DTC_MS_PHYADDR_d "zd"
182         #define DTC_MS_PHYADDR_i "zi"
183         #define DTC_MS_PHYADDR_x "zx"
184         #define DTC_MS_PHYADDR_X "zX"
185         #define DTC_MS_PHYADDR_u "zu"
186         #endif
187     #else
188         #define DTC_MS_U32_d "ld"
189         #define DTC_MS_U32_i "li"
190         #define DTC_MS_U32_x "lx"
191         #define DTC_MS_U32_X "lX"
192         #define DTC_MS_U32_u "lu"
193 
194         #define DTC_MS_U64_d "lld"
195         #define DTC_MS_U64_i "lli"
196         #define DTC_MS_U64_x "llx"
197         #define DTC_MS_U64_X "llX"
198         #define DTC_MS_U64_u "llu"
199 
200         #define DTC_MS_S32_d "ld"
201         #define DTC_MS_S32_i "li"
202         #define DTC_MS_S32_x "lx"
203         #define DTC_MS_S32_X "lX"
204         #define DTC_MS_S32_u "lu"
205 
206         #define DTC_MS_S64_d "lld"
207         #define DTC_MS_S64_i "lli"
208         #define DTC_MS_S64_x "llx"
209         #define DTC_MS_S64_X "llX"
210         #define DTC_MS_S64_u "llu"
211 
212         #define DTC_MS_PHY_d DTC_MS_U32_d
213         #define DTC_MS_PHY_i DTC_MS_U32_i
214         #define DTC_MS_PHY_x DTC_MS_U32_x
215         #define DTC_MS_PHY_X DTC_MS_U32_X
216         #define DTC_MS_PHY_u DTC_MS_U32_u
217 
218         #define DTC_MS_VIRT_d DTC_MS_U32_d
219         #define DTC_MS_VIRT_i DTC_MS_U32_i
220         #define DTC_MS_VIRT_x DTC_MS_U32_x
221         #define DTC_MS_VIRT_X DTC_MS_U32_X
222         #define DTC_MS_VIRT_u DTC_MS_U32_u
223 
224         #define DTC_MS_PHYADDR_d DTC_MS_PHY_d
225         #define DTC_MS_PHYADDR_i DTC_MS_PHY_i
226         #define DTC_MS_PHYADDR_x DTC_MS_PHY_x
227         #define DTC_MS_PHYADDR_X DTC_MS_PHY_X
228         #define DTC_MS_PHYADDR_u DTC_MS_PHY_u
229     #endif
230 #else
231 #define DTC_MS_U32_d "ld"
232 #define DTC_MS_U32_i "li"
233 #define DTC_MS_U32_x "lx"
234 #define DTC_MS_U32_X "lX"
235 #define DTC_MS_U32_u "lu"
236 
237 #define DTC_MS_U64_d "lld"
238 #define DTC_MS_U64_i "lli"
239 #define DTC_MS_U64_x "llx"
240 #define DTC_MS_U64_X "llX"
241 #define DTC_MS_U64_u "llu"
242 
243 #define DTC_MS_S32_d "ld"
244 #define DTC_MS_S32_i "li"
245 #define DTC_MS_S32_x "lx"
246 #define DTC_MS_S32_X "lX"
247 #define DTC_MS_S32_u "lu"
248 
249 #define DTC_MS_S64_d "lld"
250 #define DTC_MS_S64_i "lli"
251 #define DTC_MS_S64_x "llx"
252 #define DTC_MS_S64_X "llX"
253 #define DTC_MS_S64_u "llu"
254 
255 #define DTC_MS_PHYADDR_d "ld"
256 #define DTC_MS_PHYADDR_i "li"
257 #define DTC_MS_PHYADDR_x "lx"
258 #define DTC_MS_PHYADDR_X "lX"
259 #define DTC_MS_PHYADDR_u "lu"
260 #endif
261 
262 #endif
263