1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. 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These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 //////////////////////////////////////////////////////////////////////////////// 79 // 80 // Copyright (c) 2006-2007 MStar Semiconductor, Inc. 81 // All rights reserved. 82 // 83 // Unless otherwise stipulated in writing, any and all information contained 84 // herein regardless in any format shall remain the sole proprietary of 85 // MStar Semiconductor Inc. and be kept in strict confidence 86 // (¡§MStar Confidential Information¡¨) by the recipient. 87 // Any unauthorized act including without limitation unauthorized disclosure, 88 // copying, use, reproduction, sale, distribution, modification, disassembling, 89 // reverse engineering and compiling of the contents of MStar Confidential 90 // Information is unlawful and strictly prohibited. MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 ////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// @file drvSEAL.h 98 /// @brief SEAL Driver Interface 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 /*! \defgroup G_SEAL SEAL interface 103 \ingroup G_PERIPHERAL 104 105 \brief 106 107 This drvSEAL.h provided function to protect security range, to prevent anyone 108 who want to access this range. 109 110 <b>Features</b> 111 - SEAL initialize 112 - SEAL secure range set 113 - SEAL secure Master set 114 - SEAL secure Slave set 115 116 <b> Operation Code Flow: </b> \n 117 -# SEAL initialize 118 -# Set secure range 119 -# set secure master 120 -# set secure slave 121 -# set Buffer lock 122 123 \defgroup G_SEAL_INIT Initialization Task relative 124 \ingroup G_SEAL 125 \defgroup G_SEAL_COMMON Common Task relative 126 \ingroup G_SEAL 127 \defgroup G_SEAL_CONTROL Control relative 128 \ingroup G_SEAL 129 \defgroup G_SEAL_INT Interrupt relative 130 \ingroup G_SEAL 131 \defgroup G_SEAL_ToBeModified GPIO api to be modified 132 \ingroup G_SEAL 133 \defgroup G_SEAL_ToBeRemove GPIO api to be removed 134 \ingroup G_SEAL 135 */ 136 137 #ifndef _DRV_SEAL_H_ 138 #define _DRV_SEAL_H_ 139 140 #ifdef __cplusplus 141 extern "C" 142 { 143 #endif 144 145 #include "MsCommon.h" 146 #include "utopia.h" 147 #include "UFO.h" 148 149 //------------------------------------------------------------------------------------------------- 150 // Defines 151 //------------------------------------------------------------------------------------------------- 152 #define BIT0 0x0001UL 153 #define BIT1 0x0002UL 154 #define BIT2 0x0004UL 155 #define BIT3 0x0008UL 156 #define BIT4 0x0010UL 157 #define BIT5 0x0020UL 158 #define BIT6 0x0040UL 159 #define BIT7 0x0080UL 160 #define BIT8 0x0100UL 161 #define BIT9 0x0200UL 162 #define BIT10 0x0400UL 163 #define BIT11 0x0800UL 164 #define BIT12 0x1000UL 165 #define BIT13 0x2000UL 166 #define BIT14 0x4000UL 167 #define BIT15 0x8000UL 168 169 //------------------------------------------------------------------------------------------------- 170 // Macros 171 //------------------------------------------------------------------------------------------------- 172 #define SEAL_DRV_VERSION /* Character String for DRV/API version */ \ 173 MSIF_TAG, /* 'MSIF' */ \ 174 MSIF_CLASS, /* '00' */ \ 175 MSIF_CUS, /* 0x0000 */ \ 176 MSIF_MOD, /* 0x0000 */ \ 177 MSIF_CHIP, \ 178 MSIF_CPU, \ 179 {'S','E','A','L'}, /* IP__ */ \ 180 {'0','0'}, /* 0.0 ~ Z.Z */ \ 181 {'0','0'}, /* 00 ~ 99 */ \ 182 {'0','0','2','6','4','8','8','5'}, /* CL# */ \ 183 MSIF_OS 184 185 186 //------------------------------------------------------------------------------------------------- 187 // Type and Structure Declaration 188 //------------------------------------------------------------------------------------------------- 189 typedef enum 190 { 191 E_SEAL_MIU_DEV0, 192 E_SEAL_MIU_DEV1, 193 E_SEAL_MIU_DEV2, 194 E_SEAL_MIU_DEV3, 195 E_SEAL_MIU_NUM, 196 }eSeal_MiuDev; 197 198 typedef enum 199 { 200 #if defined(UFO_PUBLIC_HEADER_500) 201 E_SEAL_SECURE_WRITE = BIT0, 202 E_SEAL_SECURE_READ = BIT1, 203 E_SEAL_NONSECURE_WRITE = BIT2, 204 E_SEAL_NONSECURE_READ = BIT3, 205 #else 206 E_SEAL_SECURE_READ = BIT0, 207 E_SEAL_SECURE_WRITE = BIT1, 208 E_SEAL_NONSECURE_READ = BIT2, 209 E_SEAL_NONSECURE_WRITE = BIT3, 210 #endif 211 }eSeal_SecureAttribute; 212 213 typedef enum 214 { 215 E_SEAL_SECURE_RANGE_ID0, 216 E_SEAL_SECURE_RANGE_ID1, 217 E_SEAL_SECURE_RANGE_ID2, 218 E_SEAL_SECURE_RANGE_ID3, 219 E_SEAL_SECURE_RANGE_ID4, 220 E_SEAL_SECURE_RANGE_ID5, 221 E_SEAL_SECURE_RANGE_ID6, 222 E_SEAL_SECURE_RANGE_ID7, 223 #if defined(UFO_PUBLIC_HEADER_300)||defined(UFO_PUBLIC_HEADER_700) 224 E_SEAL_SECURE_RANGE_ID8, 225 E_SEAL_SECURE_RANGE_ID9, 226 E_SEAL_SECURE_RANGE_ID10, 227 E_SEAL_SECURE_RANGE_ID11, 228 E_SEAL_SECURE_RANGE_ID12, 229 E_SEAL_SECURE_RANGE_ID13, 230 E_SEAL_SECURE_RANGE_ID14, 231 E_SEAL_SECURE_RANGE_ID15, 232 #endif 233 E_SEAL_SECURE_RANGE_NUM, 234 }eSeal_SecureRangeId; 235 236 typedef enum 237 { 238 #if defined(UFO_PUBLIC_HEADER_212)||defined(UFO_PUBLIC_HEADER_300)||defined(UFO_PUBLIC_HEADER_700) 239 E_SEAL_PROCESSOR_DUMMY = -1, 240 E_SEAL_DBBUS = 0, 241 E_SEAL_MCU51, 242 E_SEAL_CPU2, 243 E_SEAL_VD_R2, 244 E_SEAL_SECURE_R2, 245 E_SEAL_SC, 246 E_SEAL_CMDQ, 247 E_SEAL_HEMCU, 248 E_SEAL_SECURE_51, 249 #if defined(UFO_PUBLIC_HEADER_212)||defined(UFO_PUBLIC_HEADER_700) 250 E_SEAL_SC_BE, 251 #endif 252 #else 253 E_SEAL_DBBUS, 254 E_SEAL_MCU51, 255 E_SEAL_CPU2, 256 E_SEAL_VD_R2, 257 E_SEAL_SECURE_R2, 258 E_SEAL_SC, 259 E_SEAL_CMDQ, 260 E_SEAL_HEMCU, 261 #endif 262 E_SEAL_PROCESSOR_NUM, 263 }eSeal_ProcessorId ; 264 265 typedef enum 266 { 267 E_SEAL_NONE =0, 268 E_SEAL_DUMMY =1, 269 E_SEAL_RIU_DBG_PROT_NONPM =2, 270 E_SEAL_MSPI0_PROT_NONPM =3, 271 E_SEAL_MSPI1_PROT_NONPM =4, 272 E_SEAL_VD_MHEG5_PROT_NONPM =5, 273 E_SEAL_MAU1_PROT_NONPM =6, 274 E_SEAL_HIREG_PROT_NONPM =7, 275 E_SEAL_POR_STATUS_PROT_NONPM =8, 276 E_SEAL_INTR_CPUINT_PROT_NONPM =9, 277 E_SEAL_MIU2_PROT_NONPM =10, 278 E_SEAL_USB0_PROT_NONPM =11, 279 E_SEAL_USB1_PROT_NONPM =12, 280 E_SEAL_BDMA_CH0_PROT_NONPM =13, 281 E_SEAL_BDMA_CH1_PROT_NONPM =14, 282 E_SEAL_UART0_PROT_NONPM =15, 283 E_SEAL_CLKGEN0_PROT_NONPM =16, 284 E_SEAL_DSCRMB_PROT_NONPM =17, 285 E_SEAL_UHC1_PROT_NONPM =18, 286 E_SEAL_MHEG5_PROT_NONPM =19, 287 E_SEAL_MVD_PROT_NONPM =20, 288 E_SEAL_MIU_PROT_NONPM =21, 289 E_SEAL_MVOPSUB_PROT_NONPM =22, 290 E_SEAL_MVOP_PROT_NONPM =23, 291 E_SEAL_TSP0_PROT_NONPM =24, 292 E_SEAL_TSP1_PROT_NONPM =25, 293 E_SEAL_JPD_PROT_NONPM =26, 294 E_SEAL_SEMAPH_PROT_NONPM =27, 295 E_SEAL_MAU0_PROT_NONPM =28, 296 E_SEAL_ECBRIDGE_PROT_NONPM =29, 297 E_SEAL_INTR_CTRL_PROT_NONPM =30, 298 E_SEAL_HDMI2_PROT_NONPM =31, 299 E_SEAL_HVD_PROT_NONPM =32, 300 E_SEAL_TSP2_PROT_NONPM =33, 301 E_SEAL_MIPS_PROT_NONPM =34, 302 E_SEAL_CHIP_PROT_NONPM =35, 303 E_SEAL_GOP_PROT_NONPM =36, 304 E_SEAL_EMAC0_PROT_NONPM =37, 305 E_SEAL_EMAC1_PROT_NONPM =38, 306 E_SEAL_EMAC2_PROT_NONPM =39, 307 E_SEAL_EMAC3_PROT_NONPM =40, 308 E_SEAL_UHC0_PROT_NONPM =41, 309 E_SEAL_ADC_ATOP_PROT_NONPM =42, 310 E_SEAL_ADC_DTOP_PROT_NONPM =43, 311 E_SEAL_HDMI_PROT_NONPM =44, 312 E_SEAL_GE0_PROT_NONPM =45, 313 E_SEAL_SMART_PROT_NONPM =46, 314 E_SEAL_CI_PROT_NONPM =47, 315 E_SEAL_CHIPGPIO_PROT_NONPM =48, 316 E_SEAL_VP6_PROT_NONPM =49, 317 E_SEAL_LDM_DMA0_PROT_NONPM =50, 318 E_SEAL_LDM_DMA1_PROT_NONPM =51, 319 E_SEAL_SC0_PROT_NONPM =52, 320 E_SEAL_SC1_PROT_NONPM =53, 321 E_SEAL_SC2_PROT_NONPM =54, 322 E_SEAL_SC3_PROT_NONPM =55, 323 E_SEAL_SC4_PROT_NONPM =56, 324 E_SEAL_CLKGEN1_PROT_NONPM =57, 325 E_SEAL_MAILBOX_PROT_NONPM =58, 326 E_SEAL_MIIC_PROT_NONPM =59, 327 E_SEAL_PCM_PROT_NONPM =60, 328 E_SEAL_VDMCU51_IF_PROT_NONPM =61, 329 E_SEAL_DMDMCU51_IF_PROT_NONPM =62, 330 E_SEAL_URDMA_PROT_NONPM =63, 331 E_SEAL_AFEC_PROT_NONPM =64, 332 E_SEAL_COMB_PROT_NONPM =65, 333 E_SEAL_VBI_PROT_NONPM =66, 334 E_SEAL_SCM_PROT_NONPM =67, 335 E_SEAL_UTMI2_PROT_NONPM =68, 336 E_SEAL_PATGEN_PROT_NONPM =69, 337 E_SEAL_UTMI1_PROT_NONPM =70, 338 E_SEAL_UTMI_PROT_NONPM =71, 339 E_SEAL_VE_0_PROT_NONPM =72, 340 E_SEAL_REG_PIU_NONPM_PROT_NONPM =73, 341 E_SEAL_VE_1_PROT_NONPM =74, 342 E_SEAL_VE_2_PROT_NONPM =75, 343 E_SEAL_MPIF_PROT_NONPM =76, 344 E_SEAL_GPD_PROT_NONPM =77, 345 E_SEAL_UART1_PROT_NONPM =78, 346 E_SEAL_UART2_PROT_NONPM =79, 347 E_SEAL_FUART_PROT_NONPM =80, 348 E_SEAL_GE1_PROT_NONPM =81, 349 E_SEAL_G3D_PROT_NONPM =82, 350 E_SEAL_DVI_ATOP_PROT_NONPM =83, 351 E_SEAL_DVI_DTOP_PROT_NONPM =84, 352 E_SEAL_DVIEQ_PROT_NONPM =85, 353 E_SEAL_HDCP_PROT_NONPM =86, 354 E_SEAL_NR_HSD_PROT_NONPM =87, 355 E_SEAL_ANA_MISC_PROT_NONPM =88, 356 E_SEAL_MIU_ATOP_PROT_NONPM =89, 357 E_SEAL_NR_PROT_NONPM =90, 358 E_SEAL_DI_PROT_NONPM =91, 359 E_SEAL_MFE0_PROT_NONPM =92, 360 E_SEAL_MFE1_PROT_NONPM =93, 361 E_SEAL_ADC_DTOPB_PROT_NONPM =94, 362 E_SEAL_NFIE0_PROT_NONPM =95, 363 E_SEAL_NFIE1_PROT_NONPM =96, 364 E_SEAL_NFIE2_PROT_NONPM =97, 365 E_SEAL_ON0_PROT_NONPM =98, 366 E_SEAL_ON1_PROT_NONPM =99, 367 E_SEAL_MIIC0_PROT_NONPM =100, 368 E_SEAL_MIIC1_PROT_NONPM =101, 369 E_SEAL_MIIC2_PROT_NONPM =102, 370 E_SEAL_MIIC3_PROT_NONPM =103, 371 E_SEAL_CLKGEN_DMD_PROT_NONPM =104, 372 E_SEAL_DEMOD_0_PROT_NONPM =105, 373 E_SEAL_DEMOD_1_PROT_NONPM =106, 374 E_SEAL_DEMOD_2_PROT_NONPM =107, 375 E_SEAL_DEMOD_3_PROT_NONPM =108, 376 E_SEAL_DEMOD_4_PROT_NONPM =109, 377 E_SEAL_DEMOD_5_PROT_NONPM =110, 378 E_SEAL_DEMOD_6_PROT_NONPM =111, 379 E_SEAL_DEMOD_7_PROT_NONPM =112, 380 E_SEAL_DMD_ANA_MISC_PROT_NONPM =113, 381 E_SEAL_AUR20_PROT_NONPM =114, 382 E_SEAL_VIVALDI0_PROT_NONPM =115, 383 E_SEAL_VIVALDI1_PROT_NONPM =116, 384 E_SEAL_VIVALDI2_PROT_NONPM =117, 385 E_SEAL_VIVALDI3_PROT_NONPM =118, 386 E_SEAL_VIVALDI4_PROT_NONPM =119, 387 E_SEAL_VIVALDI5_PROT_NONPM =120, 388 E_SEAL_AUR21_PROT_NONPM =121, 389 E_SEAL_AUR22_PROT_NONPM =122, 390 E_SEAL_DVI_ATOP_1_PROT_NONPM =123, 391 E_SEAL_DVI_DTOP_1_PROT_NONPM =124, 392 E_SEAL_DVIEQ_1_PROT_NONPM =125, 393 E_SEAL_HDCP_1_PROT_NONPM =126, 394 E_SEAL_DVI_ATOP_2_PROT_NONPM =127, 395 E_SEAL_DVI_DTOP_2_PROT_NONPM =128, 396 E_SEAL_DVIEQ_2_PROT_NONPM =129, 397 E_SEAL_HDCP_2_PROT_NONPM =130, 398 E_SEAL_DVI_PS_PROT_NONPM =131, 399 E_SEAL_DVI_DTOP_3_PROT_NONPM =132, 400 E_SEAL_DVIEQ_3_PROT_NONPM =133, 401 E_SEAL_HDCP_3_PROT_NONPM =134, 402 E_SEAL_USB2_PROT_NONPM =135, 403 E_SEAL_UHC2_PROT_NONPM =136, 404 E_SEAL_DRM_SECURE_PROT_NONPM =137, 405 E_SEAL_DSCRMB2_PROT_NONPM =138, 406 E_SEAL_DSCRMB3_PROT_NONPM =139, 407 E_SEAL_GPD0_PROT_NONPM =140, 408 E_SEAL_GPD1_PROT_NONPM =141, 409 E_SEAL_GOP4G_0_PROT_NONPM =142, 410 E_SEAL_GOP4G_1_PROT_NONPM =143, 411 E_SEAL_GOP4G_ST_PROT_NONPM =144, 412 E_SEAL_GOP2G_0_PROT_NONPM =145, 413 E_SEAL_GOP2G_1_PROT_NONPM =146, 414 E_SEAL_GOP2G_ST_PROT_NONPM =147, 415 E_SEAL_GOP1G_0_PROT_NONPM =148, 416 E_SEAL_GOP1G_1_PROT_NONPM =149, 417 E_SEAL_GOP1G_ST_PROT_NONPM =150, 418 E_SEAL_GOP1GX_0_PROT_NONPM =151, 419 E_SEAL_GOP1GX_1_PROT_NONPM =152, 420 E_SEAL_GOP1GX_ST_PROT_NONPM =153, 421 E_SEAL_GOPD_PROT_NONPM =154, 422 E_SEAL_SPARE0_PROT_NONPM =155, 423 E_SEAL_SPARE1_PROT_NONPM =156, 424 E_SEAL_CA9PAT_PROT_NONPM =157, 425 E_SEAL_USB30PHY_DTOP_PROT_NONPM =158, 426 E_SEAL_USB30PHY_ATOP_PROT_NONPM =159, 427 E_SEAL_UTMI3_PROT_NONPM =160, 428 E_SEAL_USB3INDCTL_PROT_NONPM =161, 429 E_SEAL_USB3TOP_PROT_NONPM =162, 430 E_SEAL_ALBANY0_PROT_NONPM =163, 431 E_SEAL_ALBANY1_PROT_NONPM =164, 432 E_SEAL_SEC_R2_PROT_NONPM =165, 433 E_SEAL_SEC_MAU0_PROT_NONPM =166, 434 E_SEAL_MOBF_PROT_NONPM =167, 435 E_SEAL_DC_SCL_PROT_NONPM =168, 436 E_SEAL_JPD1_PROT_NONPM =169, 437 E_SEAL_JPD2_PROT_NONPM =170, 438 E_SEAL_JPD3_PROT_NONPM =171, 439 E_SEAL_CMDQ_PROT_NONPM =172, 440 E_SEAL_MSC_PROT_NONPM =173, 441 E_SEAL_GPUAPB_PROT_NONPM =174, 442 E_SEAL_X32_USB3XHCI_PROT_NONPM =175, 443 E_SEAL_USBBC0_PROT_NONPM =176, 444 E_SEAL_USBBC1_PROT_NONPM =177, 445 E_SEAL_USBBC2_PROT_NONPM =178, 446 E_SEAL_USB3_BC0_PROT_NONPM =179, 447 E_SEAL_MHL_TMDS_PROT_NONPM =180, 448 E_SEAL_HDCPKEY_PROT_NONPM =181, 449 E_SEAL_ACP_PROT_NONPM =182, 450 E_SEAL_SPARE2_PROT_NONPM =183, 451 E_SEAL_SPARE3_PROT_NONPM =184, 452 E_SEAL_TSP_DUMMY_PROT_NONPM =185, 453 E_SEAL_CODEC_DUMMY_PROT_NONPM =186, 454 E_SEAL_MHEG5_DUMMY_PROT_NONPM =187, 455 E_SEAL_DSCRMB4_PROT_NONPM =188, 456 E_SEAL_MENULOAD_PROT_PM =189, 457 E_SEAL_GDMA_PROT_PM =190, 458 E_SEAL_DDC_PROT_PM =191, 459 E_SEAL_ISP_PROT_PM =192, 460 E_SEAL_FSP_PROT_PM =193, 461 E_SEAL_QSPI_PROT_PM =194, 462 E_SEAL_PM_SLEEP_PROT_PM =195, 463 E_SEAL_PM_GPIO_PROT_PM =196, 464 E_SEAL_MCU_PROT_PM =197, 465 E_SEAL_PM_CEC_PROT_PM =198, 466 E_SEAL_PM_RTC_PROT_PM =199, 467 E_SEAL_PM_RTC2_PROT_PM =200, 468 E_SEAL_PM_SAR_PROT_PM =201, 469 E_SEAL_PM_AV_LINK_PROT_PM =202, 470 E_SEAL_PM_TOP_PROT_PM =203, 471 E_SEAL_MHL_CBUS_PROT_PM =204, 472 E_SEAL_EFUSE_PROT_PM =205, 473 E_SEAL_IRQ_PROT_PM =206, 474 E_SEAL_CACHE_PROT_PM =207, 475 E_SEAL_XDMIU_PROT_PM =208, 476 E_SEAL_PM_MISC_PROT_PM =209, 477 E_SEAL_PM_MHL_CBUS_PROT_PM =210, 478 E_SEAL_WDT_PROT_PM =211, 479 E_SEAL_TIMER0_PROT_PM =212, 480 E_SEAL_TIMER1_PROT_PM =213, 481 E_SEAL_SEC_KEY_PROT_PM =214, 482 E_SEAL_DID_KEY_PROT_PM =215, 483 E_SEAL_REG_PIU_MISC_0_PROT_PM =216, 484 E_SEAL_IR_PROT_PM =217, 485 E_SEAL_PM_SPARE0_PROT_PM =218, 486 E_SEAL_PM_SPARE1_PROT_PM =219, 487 E_SEAL_FUART1_PROT_NONPM =220, 488 E_SEAL_URDMA1_PROT_NONPM =221, 489 E_SEAL_UPLL0_PROT_NONPM =222, 490 E_SEAL_UPLL1_PROT_NONPM =223, 491 E_SEAL_UART3_PROT_NONPM =224, 492 E_SEAL_CLKGEN2_PROT_NONPM =225, 493 E_SEAL_VDMCU51_1_IF_PROT_NONPM =226, 494 E_SEAL_ADC_ATOPB_PROT_NONPM =227, 495 E_SEAL_UART4_PROT_NONPM =228, 496 E_SEAL_ANA_MISC_GMAC_PROT_NONPM =229, 497 E_SEAL_USB30PHY_DTOP_M_0_PROT_NONPM =230, 498 E_SEAL_USB30PHY_DTOP_M_1_PROT_NONPM =231, 499 E_SEAL_USB3_PROT_NONPM =232, 500 E_SEAL_TSO_PROT_NONPM =233, 501 E_SEAL_SDIO0_PROT_NONPM =234, 502 E_SEAL_MIU_ARB256_PROT_NONPM =235, 503 E_SEAL_HDMITX_MISC_PROT_NONPM =236, 504 E_SEAL_MIIC4_PROT_NONPM =237, 505 E_SEAL_MIIC5_PROT_NONPM =238, 506 E_SEAL_HDMITX_VIDEO_PROT_NONPM =239, 507 E_SEAL_HDMITX_AUDIO_PROT_NONPM =240, 508 E_SEAL_USB30PHY_ATOP_M_0_PROT_NONPM =241, 509 E_SEAL_USB30PHY_ATOP_M_1_PROT_NONPM =242, 510 E_SEAL_UTMISS0_PROT_NONPM =243, 511 E_SEAL_UTMISS1_PROT_NONPM =244, 512 E_SEAL_UHC3_PROT_NONPM =245, 513 E_SEAL_SDIO1_PROT_NONPM =246, 514 E_SEAL_SDIO2_PROT_NONPM =247, 515 E_SEAL_USBBC3_PROT_NONPM =248, 516 E_SEAL_USB3_BC1_PROT_NONPM =249, 517 E_SEAL_SECURERANGE0_PROT_NONPM =250, 518 E_SEAL_SECURERANGE1_PROT_NONPM =251, 519 E_SEAL_TZPC_NONPM_PROT_NONPM =252, 520 E_SEAL_NFIE3_PROT_NONPM =253, 521 E_SEAL_DSCRMB5_PROT_NONPM =254, 522 E_SEAL_EMMC_PLL_PROT_NONPM =255, 523 E_SEAL_VIVALDI6_PROT_NONPM =256, 524 E_SEAL_VIVALDI7_PROT_NONPM =257, 525 E_SEAL_GMAC0_PROT_NONPM =258, 526 E_SEAL_GMAC1_PROT_NONPM =259, 527 E_SEAL_GMAC2_PROT_NONPM =260, 528 E_SEAL_GMAC3_PROT_NONPM =261, 529 E_SEAL_GMAC4_PROT_NONPM =262, 530 E_SEAL_PCM2_PROT_NONPM =263, 531 E_SEAL_TSP3_PROT_NONPM =264, 532 E_SEAL_HEVC0_PROT_NONPM =265, 533 E_SEAL_HEVC1_PROT_NONPM =266, 534 E_SEAL_DYN_SCL_PROT_NONPM =267, 535 E_SEAL_X32_MVD1_PROT_NONPM =268, 536 E_SEAL_X32_MVD2_PROT_NONPM =269, 537 E_SEAL_X32_MVD3_PROT_NONPM =270, 538 E_SEAL_X32_MVD4_PROT_NONPM =271, 539 E_SEAL_CODEC_MRQ_PROT_NONPM =272, 540 E_SEAL_MIU3_PROT_NONPM =273, 541 E_SEAL_MIU_ATOP2_PROT_NONPM =274, 542 E_SEAL_X32_HVD0_PROT_NONPM =275, 543 E_SEAL_X32_HVD1_PROT_NONPM =276, 544 E_SEAL_X32_HVD2_PROT_NONPM =277, 545 E_SEAL_X32_HVD3_PROT_NONPM =278, 546 E_SEAL_X32_HVD4_PROT_NONPM =279, 547 E_SEAL_X32_HVD5_PROT_NONPM =280, 548 E_SEAL_X32_HVD6_PROT_NONPM =281, 549 E_SEAL_X32_HVD7_PROT_NONPM =282, 550 E_SEAL_X32_EVD0_PROT_NONPM =283, 551 E_SEAL_X32_EVD1_PROT_NONPM =284, 552 E_SEAL_X32_EVD2_PROT_NONPM =285, 553 E_SEAL_X32_EVD3_PROT_NONPM =286, 554 E_SEAL_X32_EVD4_PROT_NONPM =287, 555 E_SEAL_X32_EVD5_PROT_NONPM =288, 556 E_SEAL_X32_EVD6_PROT_NONPM =289, 557 E_SEAL_X32_EVD7_PROT_NONPM =290, 558 E_SEAL_X32_EVD8_PROT_NONPM =291, 559 E_SEAL_X32_GPUAPB0_PROT_NONPM =292, 560 E_SEAL_X32_GPUAPB1_PROT_NONPM =293, 561 E_SEAL_X32_GPUAPB2_PROT_NONPM =294, 562 E_SEAL_TIMER2_PROT_PM =295, 563 E_SEAL_ALBANY0_PROT_PM =296, 564 E_SEAL_ALBANY1_PROT_PM =297, 565 E_SEAL_ALBANY2_PROT_PM =298, 566 E_SEAL_NORPF_PROT_NONPM =299, 567 E_SEAL_PM_PROT_NONPM =300, 568 E_SEAL_ON_PROT_NONPM =301, 569 E_SEAL_SWCD_PROT_NONPM =302, 570 E_SEAL_ALBANY2_PROT_NONPM =303, 571 E_SEAL_TZPC_PROT_PM =304, 572 E_SEAL_SPARE4_PROT_NONPM =305, 573 E_SEAL_SPARE5_PROT_NONPM =306, 574 E_SEAL_JPD4_PROT_NONPM =307, 575 E_SEAL_RIU_DBG_PROT_PM =308, 576 E_SEAL_UHC4_PROT_NONPM =309, 577 E_SEAL_USB4_PROT_NONPM =310, 578 E_SEAL_UTMI4_PROT_NONPM =311, 579 E_SEAL_USBBC4_PROT_NONPM =312, 580 E_SEAL_UTMISS_PROT_NONPM =313, 581 E_SEAL_VDR2_PROT_NONPM =314, 582 E_SEAL_INTR_CTRL1_PROT_NONPM =315, 583 E_SEAL_L3_AXI_PROT_NONPM =316, 584 E_SEAL_MCU_ARM_PROT_NONPM =317, 585 E_SEAL_VDMCU51_1_IF_NONPM =318, 586 E_SEAL_SC_GP1_NONPM =319, 587 E_SEAL_CHIPGPIO1_NONPM =320, 588 E_SEAL_GPU_NONPM =321, 589 E_SEAL_ANA_MISC2_NONPM =322, 590 E_SEAL_AU_MAU_NONPM =323, 591 E_SEAL_AU_GDMA_NONPM =324, 592 E_SEAL_USB3_NONPM =325, 593 E_SEAL_OTG0_NONPM =326, 594 E_SEAL_OTG1_NONPM =327, 595 E_SEAL_OTG2_NONPM =328, 596 E_SEAL_OTG3_NONPM =329, 597 E_SEAL_SECURERANGE2_NONPM =330, 598 E_SEAL_TZPC_NONPM2_NONPM =331, 599 E_SEAL_TSO1_NONPM =332, 600 E_SEAL_MSC1_NONPM =333, 601 E_SEAL_EVD_NONPM =334, 602 E_SEAL_MIU_ARB_NONPM =335, 603 E_SEAL_TSP4_NONPM =336, 604 E_SEAL_DVI_ATOP3_NONPM =337, 605 E_SEAL_HDMI_P4_NONPM =338, 606 E_SEAL_HDMI2_P4_NONPM =339, 607 E_SEAL_DVI_ATOP_P4_NONPM =340, 608 E_SEAL_DVI_DTOP_P4_NONPM =341, 609 E_SEAL_DVI_EQ_P4_NONPM =342, 610 E_SEAL_HDCP_P4_NONPM =343, 611 E_SEAL_DVI_POWERSAVE_P4_NONPM =344, 612 E_SEAL_MIU3_NONPM =345, 613 E_SEAL_MIU_ATOP3_NONPM =346, 614 E_SEAL_MIU_ARB2_NONPM =347, 615 E_SEAL_MIU_ARB3_NONPM =348, 616 E_SEAL_MIU4_NONPM =349, 617 E_SEAL_MIU_ATOP4_NONPM =350, 618 E_SEAL_MIU_ARB4_NONPM =351, 619 E_SEAL_GE2_NONPM =352, 620 E_SEAL_GE3_NONPM =353, 621 E_SEAL_HDCP22_P0_NONPM =354, 622 E_SEAL_HDCP22_P1_NONPM =355, 623 E_SEAL_HDCP22_P2_NONPM =356, 624 E_SEAL_HDCP22_P3_NONPM =357, 625 E_SEAL_HDCP22_P4_NONPM =358, 626 E_SEAL_AU_R2_1_NONPM =359, 627 E_SEAL_AU_MAU_1_NONPM =360, 628 E_SEAL_AU_GDMA_1_NONPM =361, 629 E_SEAL_VD_EVD_R2_NONPM =362, 630 E_SEAL_MAU_EVD_NONPM =363, 631 E_SEAL_MAU1_LV2_0_NONPM =364, 632 E_SEAL_MAU1_LV2_1_NONPM =365, 633 E_SEAL_MAU_EVD_LV2_0_NONPM =366, 634 E_SEAL_MAU_EVD_LV2_1_NONPM =367, 635 E_SEAL_SEC_MAU_LV2_0_NONPM =368, 636 E_SEAL_SEC_MAU_LV2_1_NONPM =369, 637 E_SEAL_TSP5_NONPM =370, 638 E_SEAL_X32_USB3XHCI_NONPM =371, 639 E_SEAL_X32_GPUAPB0_NONPM =372, 640 E_SEAL_X32_GPUAPB1_NONPM =373, 641 E_SEAL_X32_GPUAPB2_NONPM =374, 642 E_SEAL_SECURERANGE3_PROT_NONPM =375, 643 E_SEAL_HIREG_EVD_PROT_NONPM =376, 644 E_SEAL_PM_RTC0_PROT_PM =377, 645 E_SEAL_PM_RTC1_PROT_PM =378, 646 E_SEAL_PM_CEC1_PROT_PM =379, 647 E_SEAL_PM_CEC2_PROT_PM =380, 648 E_SEAL_PM_CEC3_PROT_PM =381, 649 E_SEAL_MOD2_PROT_NONPM =382, 650 E_SEAL_GOPG4_0_PROT_NONPM =383, 651 E_SEAL_GOPG4_1_PROT_NONPM =384, 652 E_SEAL_GOPG4_ST_PROT_NONPM =385, 653 E_SEAL_USB30_MIU_ARB_PROT_NONPM =386, 654 E_SEAL_ZDEC_PROT_NONPM =387, 655 E_SEAL_PATGEN_CODEC_PROT_NONPM =388, 656 E_SEAL_PATGEN_VIV_PROT_NONPM =389, 657 E_SEAL_PATGEN_CPU_PROT_NONPM =390, 658 E_SEAL_PATGEN_GPU_PROT_NONPM =391, 659 E_SEAL_PATGEN_DEMOD_PROT_NONPM =392, 660 E_SEAL_PATGEN_TSP_PROT_NONPM =393, 661 E_SEAL_PATGEN_DVI_PROT_NONPM =394, 662 E_SEAL_PATGEN_EVD_PROT_NONPM =395, 663 E_SEAL_PATGEN_SC0_PROT_NONPM =396, 664 E_SEAL_PATGEN_SC1_PROT_NONPM =397, 665 E_SEAL_PATGEN_SC2_PROT_NONPM =398, 666 E_SEAL_COMBO_PHY0_P0_PROT_NONPM =399, 667 E_SEAL_COMBO_PHY1_P0_PROT_NONPM =400, 668 E_SEAL_COMBO_PHY0_P1_PROT_NONPM =401, 669 E_SEAL_COMBO_PHY1_P1_PROT_NONPM =402, 670 E_SEAL_COMBO_PHY0_P2_PROT_NONPM =403, 671 E_SEAL_COMBO_PHY1_P2_PROT_NONPM =404, 672 E_SEAL_COMBO_PHY0_P3_PROT_NONPM =405, 673 E_SEAL_COMBO_PHY1_P3_PROT_NONPM =406, 674 E_SEAL_DVI_DTOP_DUAL_P0_PROT_NONPM =407, 675 E_SEAL_DVI_RSV_DUAL_P0_PROT_NONPM =408, 676 E_SEAL_HDCP_DUAL_P0_PROT_NONPM =409, 677 E_SEAL_DVI_DTOP_DUAL_P1_PROT_NONPM =410, 678 E_SEAL_DVI_RSV_DUAL_P1_PROT_NONPM =411, 679 E_SEAL_HDCP_DUAL_P1_PROT_NONPM =412, 680 E_SEAL_DVI_DTOP_DUAL_P2_PROT_NONPM =413, 681 E_SEAL_DVI_RSV_DUAL_P2_PROT_NONPM =414, 682 E_SEAL_HDCP_DUAL_P2_PROT_NONPM =415, 683 E_SEAL_DVI_DTOP_DUAL_P3_PROT_NONPM =416, 684 E_SEAL_DVI_RSV_DUAL_P3_PROT_NONPM =417, 685 E_SEAL_HDCP_DUAL_P3_PROT_NONPM =418, 686 E_SEAL_HDMI_DUAL_0_PROT_NONPM =419, 687 E_SEAL_HDMI2_DUAL_0_PROT_NONPM =420, 688 E_SEAL_HDMI_DUAL_1_PROT_NONPM =421, 689 E_SEAL_HDMI2_DUAL_1_PROT_NONPM =422, 690 E_SEAL_COMBO_GP_TOP_PROT_NONPM =423, 691 E_SEAL_USB30HS_UHC_PROT_NONPM =424, 692 E_SEAL_USB30HS1_UHC_PROT_NONPM =425, 693 E_SEAL_USB30HS_USBC_PROT_NONPM =426, 694 E_SEAL_USB30HS1_USBC_PROT_NONPM =427, 695 E_SEAL_USB30PHY1_DTOP_M_0_PROT_NONPM =428, 696 E_SEAL_USB30PHY1_ATOP_M_0_NONPM =429, 697 E_SEAL_MSPI_MCARD_PROT_NONPM =430, 698 E_SEAL_VP9_TOP_PROT_NONPM =431, 699 E_SEAL_GPU_PLL_PROT_NONPM =432, 700 E_SEAL_VIVALDI8_PROT_NONPM =433, 701 E_SEAL_VIVALDI9_PROT_NONPM =434, 702 E_SEAL_VIVALDIa_PROT_NONPM =435, 703 E_SEAL_VIVALDIb_PROT_NONPM =436, 704 E_SEAL_PM_PATGEN_PROT_PM =437, 705 E_SEAL_SCDC_0_PROT_PM =438, 706 E_SEAL_SCDC_1_PROT_PM =439, 707 E_SEAL_SCDC_2_PROT_PM =440, 708 E_SEAL_SCDC_3_PROT_PM =441, 709 E_SEAL_SECURE_TZPC_PROT_NONPM =442, 710 E_SEAL_UP110_PORT_NONPM =443, 711 E_SEAL_UP111_PORT_NONPM =444, 712 E_SEAL_IDAC_NONPM =445, 713 E_SEAL_DIPW_NONPM =446, 714 E_SEAL_VE_DISC_NONPM =447, 715 E_SEAL_VE_GAMA_NONPM =448, 716 E_SEAL_GOP0G_0_PROT_NONPM =449, 717 E_SEAL_GOP0G_1_PROT_NONPM =450, 718 E_SEAL_GOP0G_ST_PROT_NONPM =451, 719 E_SEAL_GOP3G_0_PROT_NONPM =452, 720 E_SEAL_GOP3G_1_PROT_NONPM =453, 721 E_SEAL_GOP3G_ST_PROT_NONPM =454, 722 E_SEAL_PM_SPARE2_PROT_PM =455, 723 E_SEAL_PM_SPARE3_PROT_PM =456, 724 E_SEAL_HDMITX_PROT_NONPM =457, 725 E_SEAL_HDCPTX_PROT_NONPM =458, 726 E_SEAL_SDIO_PLL_PROT_NONPM =459, 727 E_SEAL_TSP4_PROT_NONPM =460, 728 E_SEAL_TSP5_PROT_NONPM =461, 729 E_SEAL_MIIC_PM0_PROT_PM =462, 730 E_SEAL_TZPC_PM_PROT_PM =463, 731 E_SEAL_TS_SAMPLE_NONPM =464, 732 E_SEAL_CLKGEN_SC_FE =465, 733 E_SEAL_CLKGEN_SC_BE =466, 734 E_SEAL_CLKGEN_SC_GP2 =467, 735 E_SEAL_SC_GPLUS =468, 736 E_SEAL_SRAM_LDO =469, 737 E_SEAL_VIVALDIa_0_PROT_NONPM =470, 738 E_SEAL_VIVALDIa_1_PROT_NONPM =471, 739 E_SEAL_VIVALDIa_2_PROT_NONPM =472, 740 E_SEAL_VIVALDIa_3_PROT_NONPM =473, 741 E_SEAL_MHL_ECBUS_PROT_NONPM =474, 742 E_SEAL_CBUS_AUDIO_PROT_NONPM =475, 743 E_SEAL_MHL_ECBUS_PHY_PROT_NONPM =476, 744 E_SEAL_L2_CACHE_PROT_NONPM =477, 745 E_SEAL_PADTOP0_PROT_NONPM =478, 746 E_SEAL_PADTOP1_PROT_NONPM =479, 747 E_SEAL_MIPS_PATGEN_PROT_NONPM =480, 748 E_SEAL_ANA_MISC_MIPSPLL_PROT_NONPM =481, 749 E_SEAL_ANA_MISC_HDMI_PROT_NONPM =482, 750 E_SEAL_ANA_MISC_DSP_PROT_NONPM =483, 751 E_SEAL_RASP0_PROT_NONPM =484, 752 E_SEAL_RASP1_PROT_NONPM =485, 753 E_SEAL_RASP2_PROT_NONPM =486, 754 E_SEAL_RASP3_PROT_NONPM =487, 755 E_SEAL_HDNITX_MISC_PROT_NONPM =488, 756 E_SEAL_GOPMIX_PROT_NONPM =489, 757 E_SEAL_DAC_PLL_PROT_NONPM =490, 758 E_SEAL_SECEMAC0_PROT_NONPM =491, 759 E_SEAL_SECEMAC1_PROT_NONPM =492, 760 E_SEAL_SECEMAC2_PROT_NONPM =493, 761 E_SEAL_SECEMAC3_PROT_NONPM =494, 762 E_SEAL_SECEMAC4_PROT_NONPM =495, 763 E_SEAL_VE_VTRACK_NONPM =496, 764 E_SEAL_VE_P2I_NONPM =497, 765 E_SEAL_RASP0_FILE_PROT_NONPM =498, 766 E_SEAL_RASP1_FILE_PROT_NONPM =499, 767 E_SEAL_MIU_KEY_PROT_NONPM =500, 768 E_SEAL_PCM1_PROT_NONPM =501, 769 E_SEAL_FI_QUEUE_PROT_NONPM =502, 770 E_SEAL_CH34_MOD_PROT_NONPM =503, 771 E_SEAL_BYTE_WR_PROT_NONPM =504, 772 E_SEAL_ONEWAY_PROT_NONPM =505, 773 E_SEAL_TSP6_PROT_NONPM =506, 774 E_SEAL_TSP7_PROT_NONPM =507, 775 E_SEAL_CA_MIUCROSSBAR_PROT_NONPM =508, 776 E_SEAL_EMM_FLT1_PROT_NONPM =509, 777 E_SEAL_CA_PWD_PROT_NONPM =510, 778 E_SEAL_EMM_FLT0_PROT_NONPM =511, 779 E_SEAL_TSO0_PROT_NONPM =512, 780 E_SEAL_KC_DESC_PROT_NONPM =513, 781 E_SEAL_SEC_R2_CPU_PROT_NONPM =514, 782 E_SEAL_X32_NSK_NONPM =515, 783 E_SEAL_X32_BRIDGE_NONPM =516, 784 E_SEAL_X32_CIPHERCH0_NONPM =517, 785 E_SEAL_X32_CIPHERCH1_NONPM =518, 786 E_SEAL_X32_TSCEBANK0_NONPM =519, 787 E_SEAL_X32_TSCEBANK1_NONPM =520, 788 E_SEAL_X32_CRYPTODMA0_NONPM =521, 789 E_SEAL_X32_CRYPTODMA1_NONPM =522, 790 E_SEAL_X32_KEYTABLE_NONPM =523, 791 E_SEAL_X32_KEYLADDER0_NONPM =524, 792 E_SEAL_X32_KEYLADDER1_NONPM =525, 793 E_SEAL_X32_KEYLADDER2_NONPM =526, 794 E_SEAL_X32_PROGPVR0_NONPM =527, 795 E_SEAL_X32_PROGPVR1_NONPM =528, 796 E_SEAL_X32_PROGPVR2_NONPM =529, 797 E_SEAL_X32_PROGPVR3_NONPM =530, 798 E_SEAL_X32_RSA_NONPM =531, 799 E_SEAL_X32_MAILBOX_NONPM =532, 800 E_SEAL_X32_OTP_CTRL_NONPM =533, 801 E_SEAL_X32_OTP_PUB0_NONPM =534, 802 E_SEAL_X32_OTP_PUB1_NONPM =535, 803 E_SEAL_X32_OTP_PUB2_NONPM =536, 804 E_SEAL_X32_OTP_PUB3_NONPM =537, 805 E_SEAL_X32_NI_NONPM =538, 806 E_SEAL_X32_AKL0_NONPM =539, 807 E_SEAL_X32_AKL1_NONPM =540, 808 E_SEAL_X32_XIUGEN_NONPM =541, 809 E_SEAL_ONEWAY_PROT_PM =542, 810 E_SEAL_SEC_PROT_PM =543, 811 E_SEAL_UART5_PROT_NONPM =544, 812 E_SEAL_SPARE6_PROT_NONPM =545, 813 E_SEAL_SPARE7_PROT_NONPM =546, 814 E_SEAL_USBC0_PROT_NONPM =547, 815 E_SEAL_USBC1_PROT_NONPM =548, 816 E_SEAL_USBC2_PROT_NONPM =549, 817 E_SEAL_USBC3_PROT_NONPM =550, 818 E_SEAL_SPI2FCIE_PROT_NONPM =551, 819 E_SEAL_GPU_PLL_PROT_NONPN =552, 820 E_SEAL_VIVALDIc_PROT_NONPM =553, 821 E_SEAL_VIVALDId_PROT_NONPM =554, 822 E_SEAL_DMD_MCU2_PROT_NONPM =555, 823 E_SEAL_MIU_ARB_SC_NONPM =556, 824 E_SEAL_MIU_ARB2_SC_NONPM =557, 825 E_SEAL_VIVALDIb_0_PROT_NONPM =558, 826 E_SEAL_VIVALDIb_1_PROT_NONPM =559, 827 E_SEAL_VIVALDIb_2_PROT_NONPM =560, 828 E_SEAL_VIVALDIb_3_PROT_NONPM =561, 829 E_SEAL_PM_POR_PROT_PM =562, 830 E_SEAL_TSP8_PROT_NONPM =563, 831 E_SEAL_MCM_DIG_PROT_NONPM =564, 832 E_SEAL_MCM_CODEC_PROT_NONPM =565, 833 E_SEAL_MCM_TSP_PROT_NONPM =566, 834 E_SEAL_MCM_VIVALdi9_PROT_NONPM =567, 835 E_SEAL_MCM_SC_PROT_NONPM =568, 836 E_SEAL_MCM_DMD_PROT_NONPM =569, 837 E_SEAL_OTV23_PROT_NONPM =570, 838 E_SEAL_OTV01_PROT_NONPM =571, 839 E_SEAL_EVD_1_PROT_NONPM =572, 840 E_SEAL_SMART2_PROT_NONPM =573, 841 E_SEAL_SECMCU51_PROT_NONPM =574, 842 E_SEAL_ANA_MISC_EVDPLL_MIUPLL_PROT_NONPM =575, 843 E_SEAL_ANA_MISC_MPLLTOP_PROT_NONPM =576, 844 E_SEAL_HI_VDR2_PROT_NONPM =577, 845 E_SEAL_HI_VDR2_HIREG_PROT_NONPM =578, 846 E_SEAL_AU_R2_PROT_NONPM =579, 847 E_SEAL_GOP_AFBC_PROT_NONPM =580, 848 E_SEAL_MCU_ARM_PMU0_PROT_NONPM =581, 849 E_SEAL_GOPMIX_SD_PROT_NONPM =582, 850 E_SEAL_SPI_PRE_ARB_PROT_NONPM =583, 851 E_SEAL_SECGMAC0_PROT_NONPM =584, 852 E_SEAL_SECGMAC1_PROT_NONPM =585, 853 E_SEAL_SECGMAC2_PROT_NONPM =586, 854 E_SEAL_SECGMAC3_PROT_NONPM =587, 855 E_SEAL_SECGMAC4_PROT_NONPM =588, 856 E_SEAL_PCIE_MAC_PROT_NONPM =589, 857 E_SEAL_PCIE_AXI2MI_BRI_PROT_NONPM =590, 858 E_SEAL_USB30_SS_MIUPROT0_PROT_NONPM =591, 859 E_SEAL_USB30_HS0_MIUPROT1_PROT_NONPM =592, 860 E_SEAL_USB30_HS1_MIUPROT2_PROT_NONPM =593, 861 E_SEAL_CLKDET_PROT_NONPM =594, 862 E_SEAL_EMACMIUPROT_PROT_NONPM =595, 863 E_SEAL_CALB_PROT_NONPM =596, 864 E_SEAL_VIVALDIa_4_PROT_NONPM =597, 865 E_SEAL_VIVALDIa_5_PROT_NONPM =598, 866 E_SEAL_TSP9_PROT_NONPM =599, 867 E_SEAL_TSP10_PROT_NONPM =600, 868 E_SEAL_USBMIUPROT0_PROT_NONPM =601, 869 E_SEAL_USBMIUPROT1_PROT_NONPM =602, 870 E_SEAL_USBMIUPROT2_PROT_NONPM =603, 871 E_SEAL_DIG_TOP_PROT_NONPM =604, 872 E_SEAL_PATGEN_ROOT_PROT_NONPM =605, 873 E_SEAL_CODEC_BLOCK_PROT_NONPM =606, 874 E_SEAL_HI_CODEC_BLOCK_PROT_NONPM =607, 875 E_SEAL_PATGEN_HI_CODEC_BLOCK_PROT_NONPM =608, 876 E_SEAL_SC_BLOCK_PROT_NONPM =609, 877 E_SEAL_PATGEN_SC_PROT_NONPM =610, 878 E_SEAL_TSP_BLOCK_PROT_NONPM =611, 879 E_SEAL_VIVALDI9_BLOCK_PROT_NONPM =612, 880 E_SEAL_PATGEN_VIVALDI9_PROT_NONPM =613, 881 E_SEAL_GPU_BLOCK_PROT_NONPM =614, 882 E_SEAL_HI_CODEC_LITE_BLOCK_PROT_NONPM =615, 883 E_SEAL_PATGEN_HI_CODEC_BLOCK_LITE_NONPM =616, 884 E_SEAL_PATGEN_GPU_DIE_PROT_NONPM =617, 885 E_SEAL_HDCP22TX_PROT_NONPM =618, 886 E_SEAL_HDMITX_PHY_PROT_NONPM =619, 887 E_SEAL_VMX_VMARK_SC0_PROT_NONPM =620, 888 E_SEAL_VMX_VMARK_SC1_PROT_NONPM =621, 889 E_SEAL_HDMI3_DUAL_0_PROT_NONPM =622, 890 E_SEAL_HDMITX2_PROT_NONPM =623, 891 E_SEAL_X32_RNG_PROT_NONPM =624, 892 E_SEAL_X32_GPUAPB_PROT_NONPM =625, 893 E_SEAL_X32_PCIE_MAC_PROT_NONPM =626, 894 E_SEAL_CRYPTODMA_GEN_SECURE_PROT_NONPM =627, 895 E_SEAL_CRYPTODMA_GEN_NON_SEcure_PROT_NONPM =628, 896 E_SEAL_CRYPTODMA_SEC_R2_PROT_NONPM =629, 897 E_SEAL_CRYPTODMA_SEC_51_PROT_NONPM =630, 898 E_SEAL_PM51_TO_MIU_PROT_NONPM =631, 899 E_SEAL_ARM2MIU_NON_SECURE_PROT_NONPM =632, 900 E_SEAL_ARM2MIU_SECURE_PROT_NONPM =633, 901 E_SEAL_DEMOD_DMDMCU51_MIU_PROT_NONPM =634, 902 E_SEAL_ANA_MISC_MPOP_PROT_NONPM =635, 903 E_SEAL_CRYPTODMA_SEC_R2_PROT_NONPN =636, 904 E_SEAL_MSPI0_PROT_PM =637, 905 E_SEAL_BYTE2WORD_PROT_PM =638, 906 E_SEAL_FSC1_PROT_PM =639, 907 E_SEAL_OTP_LDO_PROT_PM =640, 908 E_SEAL_MFSC_PROT_NONPM =641, 909 E_SEAL_PATGEN_FSC_PROT_NONPM =642, 910 E_SEAL_USB0_MIUPROT_PROT_NONPM =643, 911 E_SEAL_USB1_MIUPROT_PROT_NONPM =644, 912 E_SEAL_USB2_MIUPROT_PROT_NONPM =645, 913 E_SEAL_USB3_MIUPROT_PROT_NONPM =646, 914 E_SEAL_VIVALDIe_PROT_NONPM =647, 915 E_SEAL_VIVALDIf_PROT_NONPM =648, 916 E_SEAL_MIU_ARB3_SC_NONPM =649, 917 E_SEAL_MIU_ARB_FRC_NONPM =650, 918 E_SEAL_MIU_ARB2_FRC_NONPM =651, 919 E_SEAL_DSCRMB6_PROT_NONPM =652, 920 E_SEAL_DSCRMB7_PROT_NONPM =653, 921 E_SEAL_CRI_KL_PROT_NONPM =654, 922 E_SEAL_CERT_KL_PROT_NONPM =655, 923 E_SEAL_X32_CRI_APB_PROT_NONPM =656, 924 E_SEAL_X32_CERT_PROT_NONPM =657, // E_SEAL_X32_CERT_APB_PROT_NONPM ? 925 E_SEAL_COMB1_PROT_NONPM =658, 926 E_SEAL_COMB2_PROT_NONPM =659, 927 E_SEAL_COMB3_PROT_NONPM =660, 928 E_SEAL_COMB4_PROT_NONPM =661, 929 E_SEAL_COMB5_PROT_NONPM =662, 930 E_SEAL_PDW0_PROT_NONPM =663, 931 E_SEAL_PDW1_PROT_NONPM =664, 932 E_SEAL_DIP_PROT_NONPM =665, 933 E_SEAL_STR_PROT_PM =666, 934 E_SEAL_TSP_SPARE_PROT_NONPM =667, 935 E_SEAL_CODEC_SPARE_PROT_NONPM =668, 936 E_SEAL_MHEG5_SPARE_PROT_NONPM =669, 937 E_SEAL_CCI400_PROT_NONPM =670, 938 E_SEAL_ARM_CA72_PROT_NONPM =671, 939 E_SEAL_SCPLL_PROT_NONPM =672, 940 E_SEAL_TOP_SPARE0_PROT_NONPM =673, 941 E_SEAL_TOP_SPARE1_PROT_NONPM =674, 942 E_SEAL_MIPSPLL_2_PROT_NONPM =675, 943 E_SEAL_SC_GPLUS_TOP_PROT_NONPM =676, 944 E_SEAL_DSCRMB23_PROT_NONPM =677, 945 E_SEAL_DSCRMB24_PROT_NONPM =678, 946 E_SEAL_MFT_PROT_NONPM =679, 947 E_SEAL_CMDQ_SUB_PROT_NONPM =680, 948 E_SEAL_PATGEN_DEMOD1_PROT_NONPM =681, 949 E_SEAL_DEMOD_8_PROT_NONPM =682, 950 E_SEAL_DEMOD_9_PROT_NONPM =683, 951 E_SEAL_MIU_DIG_E_PROT_NONPM =684, 952 E_SEAL_MIU_DIG_E2_PROT_NONPM =685, 953 E_SEAL_MIU_DIG_E3_PROT_NONPM =686, 954 E_SEAL_MIU_DIG_E4_PROT_NONPM =687, 955 E_SEAL_DMD_TOP_1_PROT_NONPM =688, 956 E_SEAL_TSO2_PROT_NONPM =689, 957 E_SEAL_GPU2MIU_MASK_PROT_NONPM =690, 958 E_SEAL_MIU_ARBB_NONPM =691, 959 E_SEAL_MIU_ARBB2_NONPM =692, 960 E_SEAL_MIU_ARBB3_NONPM =693, 961 E_SEAL_MIU_ARBB4_NONPM =694, 962 E_SEAL_DSCRMB25_PROT_NONPM =695, 963 E_SEAL_DSCRMB26_PROT_NONPM =696, 964 E_SEAL_DSCRMB27_PROT_NONPM =697, 965 E_SEAL_MIU_ARB3_FRC_NONPM =698, 966 E_SEAL_VIVALDIa_6_PROT_NONPM =699, 967 E_SEAL_HDMI3_DUAL_1_PROT_NONPM =700, 968 E_SEAL_X32_PKA_APB_PROT_NONPM =701, 969 E_SEAL_SC_GPLUS_TOP =702, 970 E_SEAL_ZDEC_TOP_PROT_NONPM =703, 971 E_SEAL_GS_PROT_NONPM =704, 972 E_SEAL_STB_DC_PROT_NONPM =705, 973 E_SEAL_SVP3_PROT_NONPM =706, 974 E_SEAL_PM_DIG_TOP_PROT_PM =707, 975 E_SEAL_BLK_DIG_PROT_NONPM =708, 976 E_SEAL_PATGEN_DIG_PROT_NONPM =709, 977 E_SEAL_BLK_CODEC_PROT_NONPM =710, 978 E_SEAL_BLK_DMD0_PROT_NONPM =711, 979 E_SEAL_BLK_HICODEC_PROT_NONPM =712, 980 E_SEAL_BLK_SC_PROT_NONPM =713, 981 E_SEAL_BLK_TSP_PROT_NONPM =714, 982 E_SEAL_BLK_VIVALDI9_PROT_NONPM =715, 983 E_SEAL_INTR_CTRL_CPU0_1_PROT_NONPM =716, 984 E_SEAL_INTR_CTRL_CPU1_1_PROT_NONPM =717, 985 E_SEAL_INTR_CTRL_CPU2_1_PROT_NONPM =718, 986 E_SEAL_INTR_CTRL_CPU3_1_PROT_NONPM =719, 987 E_SEAL_HVD1_PROT_NONPM =720, 988 E_SEAL_INTR_CTRL_CPU0_0_PROT_NONPM =721, 989 E_SEAL_INTR_CTRL_CPU1_0_PROT_NONPM =722, 990 E_SEAL_INTR_CTRL_CPU2_0_PROT_NONPM =723, 991 E_SEAL_INTR_CTRL_CPU3_0_PROT_NONPM =724, 992 E_SEAL_SATA_GHC_PROT_NONPM =725, 993 E_SEAL_SATA_P0_PROT_NONPM =726, 994 E_SEAL_SATA_MISC_PROT_NONPM =727, 995 E_SEAL_SATA_MIUPROT_PROT_NONPM =728, 996 E_SEAL_SATA_PHY_PROT_NONPM =729, 997 E_SEAL_INTR_CTRL_CPU4_0_PROT_NONPM =730, 998 E_SEAL_INTR_CTRL_CPU4_1_PROT_NONPM =731, 999 E_SEAL_MFDEC_PROT_NONPM =732, 1000 E_SEAL_CLKGEN_AUR2_0_PROT_NONPM =733, // riu_clkgen_au_r2_20_prot_ns 1001 E_SEAL_PATGEN_AUR2_0_PROT_NONPM =734, 1002 E_SEAL_CLKGEN_AUR2_1_PROT_NONPM =735, // riu_clkgen_au_r2_21_prot_ns 1003 E_SEAL_PATGEN_AUR2_1_PROT_NONPM =736, 1004 E_SEAL_GOP5G_0_PROT_NONPM =737, 1005 E_SEAL_GOP5G_1_PROT_NONPM =738, 1006 E_SEAL_GOP5G_ST_PROT_NONPM =739, 1007 E_SEAL_TZPC_MIU0_PROT_NONPM =740, 1008 E_SEAL_TZPC_MIU1_PROT_NONPM =741, 1009 E_SEAL_TZPC_HOSTID_NONPM_PROT_NONPM =742, 1010 E_SEAL_IMONITOR_PROT_NONPM =743, 1011 E_SEAL_MIU_PROTECT_PROT_NONPM =744, 1012 E_SEAL_MIU_PROTECT2_PROT_NONPM =745, 1013 E_SEAL_PKA_PROT_NONPM =746, 1014 E_SEAL_PKA_BYTE2WORD_PROT_NONPM =747, 1015 E_SEAL_TSIO0_PROT_NONPM =748, 1016 E_SEAL_TSIO1_PROT_NONPM =749, 1017 E_SEAL_TSIO2_PROT_NONPM =750, 1018 E_SEAL_TSIO3_PROT_NONPM =751, 1019 E_SEAL_TSO3_PROT_NONPM =752, 1020 E_SEAL_TSIO_LOC_DEC_PROT_NONPM =753, 1021 E_SEAL_TSIO_PHY_PROT_NONPM =754, 1022 E_SEAL_VD_R2_SUBSYS_PROT_NONPM =755, 1023 E_SEAL_X32_PIDSLOTMTN_PROT_NONPM =756, 1024 E_SEAL_X32_KEYLADDER0_1_NONPM =757, 1025 E_SEAL_X32_CA_MPROT_NONPM =758, 1026 E_SEAL_X32_CA_RPROT_NONPM =759, 1027 E_SEAL_X32_GMAC0_NONPM =760, 1028 E_SEAL_X32_GMAC1_NONPM =761, 1029 E_SEAL_X32_GMAC2_NONPM =762, 1030 E_SEAL_X32_EMAC0_NONPM =763, 1031 E_SEAL_X32_EMAC1_NONPM =764, 1032 E_SEAL_X32_EMAC2_NONPM =765, 1033 E_SEAL_X32_SATA_MAC_PROT_NONPM =766, 1034 E_SEAL_TSP_PVR4_PROT_NONPM =767, 1035 E_SEAL_TSP_VQ_PROT_NONPM =768, 1036 E_SEAL_TSP_OR_PROT_NONPM =769, 1037 E_SEAL_TSP_SEC_PROT_NONPM =770, 1038 E_SEAL_TSP_FILEIN_ILLEGAL_PROT_NONPM =771, 1039 E_SEAL_TSP_NON_SECURE_PROT_NONPM =772, 1040 E_SEAL_STR_DATA_PM_PROT_PM =773, 1041 E_SEAL_MIU_BWFLAG_PROT_NONPM =774, 1042 E_SEAL_MIU_BWFLAG2_PROT_NONPM =775, 1043 E_SEAL_X32_CPUAPB0_NONPM =776, 1044 E_SEAL_PAD_MUX_NONPM =777, 1045 E_SEAL_ROM_CRC_NONPM =778, 1046 E_SEAL_SECURE_HDMITX_NONPM =779, 1047 E_SEAL_DEMOD_MIU_ARB_PROT_NONPM =780, 1048 E_SEAL_DEMOD_BLOCK_PROT_NONPM =781, 1049 E_SEAL_SECPVR_LUT_PROT_NONPM =782, 1050 E_SEAL_PVR_FSC0_PROT_NONPM =783, 1051 E_SEAL_PVR_FSC1_PROT_NONPM =784, 1052 E_SEAL_PVR_FSC2_PROT_NONPM =785, 1053 E_SEAL_PVR_FSC3_PROT_NONPM =786, 1054 E_SEAL_X32_CFB_0_PROT_NONPM =787, 1055 E_SEAL_X32_CFB_1_PROT_NONPM =788, 1056 E_SEAL_AEON_I_PROT_NONPM =789, 1057 E_SEAL_DSP_I_PROT_NONPM =790, 1058 E_SEAL_SECU_51_I_PROT_NONPM =791, 1059 E_SEAL_AU_R2_1_I_PROT_NONPM =792, 1060 E_SEAL_AU_R2_0_I_PROT_NONPM =793, 1061 E_SEAL_VD_R2_I_PROT_NONPM =794, 1062 E_SEAL_SECU_R2_I_PROT_NONPM =795, 1063 E_SEAL_DMD51_I_PROT_NONPM =796, 1064 E_SEAL_ARM_I_NON_SECURE_PROT_NONPM =797, 1065 E_SEAL_ARM_I_SECURE_PROT_NONPM =798, 1066 E_SEAL_PM51_I_PROT_NONPM =799, 1067 E_SEAL_X32_SATA_MAC_01_PROT_NONPM =800, 1068 E_SEAL_X32_SATA_MAC_02_PROT_NONPM =801, 1069 E_SEAL_X32_SATA_MAC_03_PROT_NONPM =802, 1070 E_SEAL_AEON_D_PROT_NONPM =803, 1071 E_SEAL_DSP_D_PROT_NONPM =804, 1072 E_SEAL_SECU_51_D_PROT_NONPM =805, 1073 E_SEAL_AU_R2_1_D_PROT_NONPM =806, 1074 E_SEAL_AU_R2_0_D_PROT_NONPM =807, 1075 E_SEAL_VD_R2_D_PROT_NONPM =808, 1076 E_SEAL_SECU_R2_D_PROT_NONPM =809, 1077 E_SEAL_DMD51_D_PROT_NONPM =810, 1078 E_SEAL_ARM_D_NON_SECURE_PROT_NONPM =811, 1079 E_SEAL_ARM_D_SECURE_PROT_NONPM =812, 1080 E_SEAL_PM51_D_PROT_NONPM =813, 1081 E_SEAL_IR_TX_PROT_PM =814, 1082 E_SEAL_IR_TX_MEM_PROT_PM =815, 1083 E_SEAL_IR2_PROT_PM =816, 1084 E_SEAL_MAILBOX_PQ_PROT_NONPM =817, 1085 E_SEAL_BAT_PROT_NONPM =818, 1086 E_SEAL_SC_EXT_PROT_NONPM =819, 1087 E_SEAL_MSC_EXT_PROT_NONPM =820, 1088 E_SEAL_DWIN0_PROT_NONPM =821, 1089 E_SEAL_DWIN1_PROT_NONPM =822, 1090 E_SEAL_DIP_0_PROT_NONPM =823, 1091 E_SEAL_DIP_1_PROT_NONPM =824, 1092 E_SEAL_DDI_0_PROT_NONPM =825, 1093 E_SEAL_DDI_1_PROT_NONPM =826, 1094 E_SEAL_WFIMON_PROT_PM =827, 1095 E_SEAL_ANA_MISC_MIPSPLL1_PROT_NONPM =828, 1096 E_SEAL_ANA_MISC_MIPSPLL2_PROT_NONPM =829, 1097 E_SEAL_X32_MAILBOX_1_NONPM =830, 1098 E_SEAL_ANA_MISC_LPF_PROT_NONPM =831, 1099 E_SEAL_ANA_MISC_DDR_SCAL_PROT_NONPM =832, 1100 E_SEAL_GEMAC0_PROT_NONPM =833, 1101 E_SEAL_GEMAC1_PROT_NONPM =834, 1102 E_SEAL_GEMAC2_PROT_NONPM =835, 1103 E_SEAL_GEMAC3_PROT_NONPM =836, 1104 E_SEAL_GEMAC4_PROT_NONPM =837, 1105 E_SEAL_CH34_MOD1_PROT_NONPM =838, 1106 E_SEAL_X32_GEMAC0_NONPM =839, 1107 E_SEAL_X32_GEMAC1_NONPM =840, 1108 E_SEAL_X32_GEMAC2_NONPM =841, 1109 E_SEAL_BLK_DIG_PM_PROT_PM =842, 1110 E_SEAL_IP_NUM =843 1111 }eSeal_IP; 1112 1113 typedef enum 1114 { 1115 E_SEAL_LOCK_NONE =0, 1116 E_SEAL_LOCK_DUMMY =1, 1117 E_SEAL_VD_R2_INST_BUF =2, 1118 E_SEAL_HK_R2_INST_BUF =3, 1119 E_SEAL_AUDIO_DEC_R2_INST_BUF =4, 1120 E_SEAL_AUDIO_DEC_ES_BUF =5, 1121 E_SEAL_AUDIO_ENC_R2_INST_BUF =6, 1122 E_SEAL_AUDIO_ENC_ES_BUF =7, 1123 E_SEAL_HVD_ES0_BUF =8, 1124 E_SEAL_HVD_ES1_BUF =9, 1125 E_SEAL_HVD_ES2_BUF =10, 1126 E_SEAL_MFE0_ES_BUF =11, 1127 E_SEAL_MFE1_ES_BUF =12, 1128 E_SEAL_TSP_AEON_INS_BUF =13, 1129 E_SEAL_PVR_BUF =14, 1130 E_SEAL_SECURE_RANGE =15, 1131 E_SEAL_SC_BUF =16, 1132 E_SEAL_GE_BUF =17, 1133 E_SEAL_SC_WP_DIPW =18, 1134 E_SEAL_SC_RP_DIPW =19, 1135 E_SEAL_SC_WP_DIPR =20, 1136 E_SEAL_SC_RP_DIPR =21, 1137 E_SEAL_CIPHERENG_WP_SYSKEY =22, 1138 E_SEAL_CIPHERENG_RP_SYSKEY =23, 1139 E_SEAL_DSCRMB_WP_RIV0 =24, 1140 E_SEAL_DSCRMB_RP_RIV0 =25, 1141 E_SEAL_DSCRMB_WP_RIV1 =26, 1142 E_SEAL_DSCRMB_RP_RIV1 =27, 1143 E_SEAL_DSCRMB_WP_WDATA =28, 1144 E_SEAL_DSCRMB_RP_WDATA =29, 1145 E_SEAL_DSCRMB_RP_RDATA =30, 1146 E_SEAL_RNG_PROTECT =31, 1147 E_SEAL_RSA_PROTECT =32, 1148 E_SEAL_SHA_PROTECT =33, 1149 E_SEAL_MVD_WR_PROTN_0 =34, 1150 E_SEAL_MVD_WR_PROTN_1 =35, 1151 E_SEAL_MVD_WR_PROTN_2 =36, 1152 E_SEAL_EVD_0_WR_PROTN_0 =37, 1153 E_SEAL_EVD_1_WR_PROTN_0 =38, 1154 E_SEAL_MHEG5_WR_PROTN_0 =39, 1155 E_SEAL_TSO_WP_TSOFI =40, 1156 E_SEAL_TSO_RP_TSOFI =41, 1157 E_SEAL_MMFI_WP_MMFI0 =42, 1158 E_SEAL_MMFI_RP_MMFI0 =43, 1159 E_SEAL_MMFI_WP_MMFI1 =44, 1160 E_SEAL_MMFI_RP_MMFI1 =45, 1161 E_SEAL_TSP0_WP_PVR =46, 1162 E_SEAL_TSP0_RP_PVR =47, 1163 E_SEAL_TSP0_WP_PVR1 =48, 1164 E_SEAL_TSP0_RP_PVR1 =49, 1165 E_SEAL_TSP0_WP_FILEIN =50, 1166 E_SEAL_TSP0_RP_FILEIN =51, 1167 E_SEAL_TSP0_WP_QMEM =52, 1168 E_SEAL_TSP0_RP_QMEM =53, 1169 E_SEAL_TSP0_WP_FW =54, 1170 E_SEAL_TSP0_RP_FW =55, 1171 E_SEAL_VE_WP =56, 1172 E_SEAL_VE_RP =57, 1173 E_SEAL_SC_WP_OD =58, 1174 E_SEAL_SC_RP_OD =59, 1175 E_SEAL_SC_WP_SCM_M =60, 1176 E_SEAL_SC_RP_SCM_M =61, 1177 E_SEAL_SC_WP_SCM_S =62, 1178 E_SEAL_SC_RP_SCM_S =63, 1179 E_SEAL_SC_WP_PDW0 =64, 1180 E_SEAL_SC_RP_PDW0 =65, 1181 E_SEAL_SC_WP_PDW1 =66, 1182 E_SEAL_SC_RP_PDW1 =67, 1183 E_SEAL_SC_WP_OPW =68, 1184 E_SEAL_SC_RP_OPW =69, 1185 E_SEAL_GOPD_PROTN =70, 1186 E_SEAL_GE0_SB_PROTN =71, 1187 E_SEAL_GE0_DB_PROTN =72, 1188 E_SEAL_GE1_SB_PROTN =73, 1189 E_SEAL_GE1_DB_PROTN =74, 1190 E_SEAL_AUDIO_LCL_R2_WR_PROTN_0 =75, 1191 E_SEAL_AUDIO_LCL_R2_WR_PROTN_1 =76, 1192 E_SEAL_AUDIO_LCL_R2_WR_PROTN_2 =77, 1193 E_SEAL_AUDIO_LCL_R2_WR_PROTN_3 =78, 1194 E_SEAL_AUDIO_SCL_R2_WR_PROTN_0 =79, 1195 E_SEAL_AUDIO_SCL_R2_WR_PROTN_1 =80, 1196 E_SEAL_AUDIO_SCL_R2_WR_PROTN_2 =81, 1197 E_SEAL_AUDIO_SCL_R2_WR_PROTN_3 =82, 1198 E_SEAL_SECURE_R2_WR_PROTN_0 =83, 1199 E_SEAL_SECURE_R2_WR_PROTN_1 =84, 1200 E_SEAL_SECURE_R2_WR_PROTN_2 =85, 1201 E_SEAL_SECURE_R2_WR_PROTN_3 =86, 1202 E_SEAL_EVD_R2_WR_PROTN_0 =87, 1203 E_SEAL_EVD_R2_WR_PROTN_1 =88, 1204 E_SEAL_EVD_R2_WR_PROTN_2 =89, 1205 E_SEAL_EVD_R2_WR_PROTN_3 =90, 1206 E_SEAL_HVD_R2_WR_PROTN_0 =91, 1207 E_SEAL_HVD_R2_WR_PROTN_1 =92, 1208 E_SEAL_HVD_R2_WR_PROTN_2 =93, 1209 E_SEAL_HVD_R2_WR_PROTN_3 =94, 1210 E_SEAL_AUDIO_DSP_ES_PROTN =95, 1211 E_SEAL_AUDIO_DSP_CACHE_PROTN =96, 1212 E_SEAL_EVD_0_WR_PROTN_1 =97, 1213 E_SEAL_EVD_1_WR_PROTN_1 =98, 1214 E_SEAL_DSCRMB_WP_RIV2 =99, 1215 E_SEAL_DSCRMB_RP_RIV2 =100, 1216 E_SEAL_DSCRMB_WP_RIV3 =101, 1217 E_SEAL_DSCRMB_RP_RIV3 =102, 1218 E_SEAL_SC2_WP_SCM_M =103, 1219 E_SEAL_SC2_RP_SCM_M =104, 1220 E_SEAL_VP9_TOP =105, 1221 E_SEAL_TSP0_WP_FILEIN1 =106, 1222 E_SEAL_TSP0_RP_FILEIN1 =107, 1223 E_SEAL_TSP0_WP_PVR2 =108, 1224 E_SEAL_TSP0_RP_PVR2 =109, 1225 E_SEAL_TSP0_WP_FIQ =110, 1226 E_SEAL_TSP0_RP_FIQ =111, 1227 E_SEAL_MVOP_WP_TLB =112, 1228 E_SEAL_AUDIO_PAS_PROTN =113, 1229 E_SEAL_AUDIO_AL_PROTN =114, 1230 E_SEAL_TSP_WP_PVR3 =115, 1231 E_SEAL_TSP_RP_PVR3 =116, 1232 E_SEAL_TSP_WP_FILEIN2 =117, 1233 E_SEAL_TSP_RP_FILEIN2 =118, 1234 E_SEAL_TSP_WP_FILEIN3 =119, 1235 E_SEAL_TSP_RP_FILEIN3 =120, 1236 E_SEAL_TSP_WP_FILEIN4 =121, 1237 E_SEAL_TSP_RP_FILEIN4 =122, 1238 E_SEAL_TSP_WP_FILEIN5 =123, 1239 E_SEAL_TSP_RP_FILEIN5 =124, 1240 E_SEAL_CRI_KL_WP_N =125, 1241 E_SEAL_PCIERC_IBWP_PROTN =126, 1242 E_SEAL_PCIERC_OBWP_PROTN =127, 1243 E_SEAL_TSP_WP_FILEIN1 =128, 1244 E_SEAL_TSP_RP_FILEIN1 =129, 1245 E_SEAL_TSP_WP_FIQ0 =130, 1246 E_SEAL_TSP_RP_FIQ0 =131, 1247 E_SEAL_TSP_WP_PVR4 =132, 1248 E_SEAL_TSP_RP_PVR4 =133, 1249 E_SEAL_TSP_WP_FIQ1 =134, 1250 E_SEAL_TSP_RP_FIQ1 =135, 1251 E_SEAL_TSP_WP_ORZ =136, 1252 E_SEAL_TSP_RP_ORZ =137, 1253 E_SEAL_USB_MIUPROT_WP_N =138, 1254 E_SEAL_EMAC_MIUPROT_WP_N =139, 1255 E_SEAL_PCIE_MIUPROT_WP_N =140, 1256 E_SEAL_AU_HDMI_DMA_WP_N =141, 1257 E_SEAL_TSP_WP_VQ =142, 1258 E_SEAL_TSP_RP_VQ =143, 1259 E_SEAL_TSP_WP_SEC =144, 1260 E_SEAL_TSP_RP_SEC =145, 1261 E_SEAL_TSP_WP_FIQ2 =146, 1262 E_SEAL_TSP_RP_FIQ2 =147, 1263 E_SEAL_TSP_WP_FIQ3 =148, 1264 E_SEAL_TSP_RP_FIQ3 =149, 1265 E_SEAL_EVD_LITE_0_WR_PROTN_0 =150, 1266 E_SEAL_EVD_LITE_1_WR_PROTN_1 =151, 1267 E_SEAL_GOPG_WP_N =152, 1268 E_SEAL_DIP_PROTN =153, 1269 E_SEAL_HDGEN_WP_N =154, 1270 E_SEAL_HDGEN_RP_N =155, 1271 E_SEAL_HDGEN_DCS_MV_WP_N =156, 1272 E_SEAL_HDGEN_DCS_MV_RP_N =157, 1273 E_SEAL_VE_DCS_MV_WP_N =158, 1274 E_SEAL_VE_DCS_MV_RP_N =159, 1275 E_SEAL_LOCK_ECO =160, 1276 E_SEAL_VTRACK_PROTN =161, 1277 E_SEAL_FCIE_WR_PROT_ENABLE_0 =162, 1278 E_SEAL_FCIE_WR_PROT_ENABLE_1 =163, 1279 E_SEAL_FCIE_WR_PROT_ENABLE_2 =164, 1280 E_SEAL_FCIE_WR_PROT_ENABLE_3 =165, 1281 E_SEAL_HDCP_RIU_R_PROTN =166, 1282 E_SEAL_HDCP_XIU_R_PROTN =167, 1283 E_SEAL_HDCP_RIU_W_PROTN =168, 1284 E_SEAL_HDCP_XIU_W_PROTN =169, 1285 E_SEAL_FCIE_WR_PROT_0_LOCK =170, 1286 E_SEAL_FCIE_WR_PROT_1_LOCK =171, 1287 E_SEAL_FCIE_WR_PROT_2_LOCK =172, 1288 E_SEAL_FCIE_WR_PROT_3_LOCK =173, 1289 E_SEAL_LOCK_NUM =174 1290 }eSeal_Lock; 1291 1292 typedef enum 1293 { 1294 E_SEAL_OVERLAP =0, 1295 E_SEAL_CONTAIN =1 1296 } eSeal_CheckSecureRangeType; 1297 1298 typedef enum 1299 { 1300 E_SEAL_IPGROUP_VDEC_R2, 1301 E_SEAL_IPGROUP_VDEC_DECODER, 1302 } eSeal_IPGroup; 1303 1304 typedef struct 1305 { 1306 MS_BOOL bIsHit; 1307 MS_U8 u8MiuDev; 1308 MS_U8 u8SecureRangeId; 1309 MS_U8 u8ClientId; 1310 MS_BOOL bIsSecure; 1311 MS_BOOL bIsWrite; 1312 MS_U64 u64HitAddr; 1313 }Seal_PortectInfo; 1314 1315 typedef struct 1316 { 1317 MS_U8 u8MiuDev; 1318 MS_U8 u8SecureRangeId; 1319 MS_U64 u64StartAddr; 1320 MS_U64 u64EndAddr; 1321 MS_U32 u32Attribute; 1322 }Seal_SecureRangeInfo; 1323 1324 typedef void (*SEAL_CB_FUNC)(InterruptNum eIntNum); 1325 //------------------------------------------------------------------------------------------------- 1326 // Extern Global Variabls 1327 //------------------------------------------------------------------------------------------------- 1328 1329 //------------------------------------------------------------------------------------------------- 1330 // Extern Functions 1331 //------------------------------------------------------------------------------------------------- 1332 //------------------------------------------------------------------------------------------------- 1333 /// Set IR enable function. 1334 /// @ingroup G_SEAL_INIT 1335 /// @param bEnable \b IN: TRUE: enable IR, FALSE: disable IR 1336 /// @return E_IR_OK: Success 1337 /// @return E_IR_FAIL or other values: Failure 1338 //------------------------------------------------------------------------------------------------- 1339 MS_BOOL MDrv_SEAL_Init(void); 1340 //------------------------------------------------------------------------------------------------- 1341 /// Set IR enable function. 1342 /// @ingroup G_SEAL_CONTROL 1343 /// @param bEnable \b IN: TRUE: enable IR, FALSE: disable IR 1344 /// @return E_IR_OK: Success 1345 /// @return E_IR_FAIL or other values: Failure 1346 //------------------------------------------------------------------------------------------------- 1347 MS_BOOL MDrv_Seal_SecureRangeSet(MS_U8 u8SecureRangeId ,MS_U64 u64StartAddr, MS_U64 u64EndAddr, MS_U32 u32Attribute); 1348 //------------------------------------------------------------------------------------------------- 1349 /// Set IR enable function. 1350 /// @ingroup G_SEAL_CONTROL 1351 /// @param bEnable \b IN: TRUE: enable IR, FALSE: disable IR 1352 /// @return E_IR_OK: Success 1353 /// @return E_IR_FAIL or other values: Failure 1354 //------------------------------------------------------------------------------------------------- 1355 MS_BOOL MDrv_Seal_SecureRangeQuery(MS_U8 u8MiuDev, MS_U8 u8SecureRangeId, Seal_SecureRangeInfo *pSecureRangeInfo); 1356 //------------------------------------------------------------------------------------------------- 1357 /// Set IR enable function. 1358 /// @ingroup G_SEAL_CONTROL 1359 /// @param bEnable \b IN: TRUE: enable IR, FALSE: disable IR 1360 /// @return E_IR_OK: Success 1361 /// @return E_IR_FAIL or other values: Failure 1362 //------------------------------------------------------------------------------------------------- 1363 MS_BOOL MDrv_Seal_IMI_RangeSet(MS_U32 u32StartAddr, MS_U32 u32EndAddr, MS_BOOL bEnable); 1364 //------------------------------------------------------------------------------------------------- 1365 /// Set IR enable function. 1366 /// @ingroup G_SEAL_CONTROL 1367 /// @param bEnable \b IN: TRUE: enable IR, FALSE: disable IR 1368 /// @return E_IR_OK: Success 1369 /// @return E_IR_FAIL or other values: Failure 1370 //------------------------------------------------------------------------------------------------- 1371 MS_BOOL MDrv_Seal_GetHittedInfo(MS_U8 u8MiuDev, Seal_PortectInfo *pInfo); 1372 //------------------------------------------------------------------------------------------------- 1373 /// Set IR enable function. 1374 /// @ingroup G_SEAL_CONTROL 1375 /// @param bEnable \b IN: TRUE: enable IR, FALSE: disable IR 1376 /// @return E_IR_OK: Success 1377 /// @return E_IR_FAIL or other values: Failure 1378 //------------------------------------------------------------------------------------------------- 1379 MS_BOOL MDrv_Seal_SecureRangeLock(MS_U8 u8MiuDev, MS_U8 u8SecureRangeId); 1380 //------------------------------------------------------------------------------------------------- 1381 /// Set IR enable function. 1382 /// @ingroup G_SEAL_CONTROL 1383 /// @param bEnable \b IN: TRUE: enable IR, FALSE: disable IR 1384 /// @return E_IR_OK: Success 1385 /// @return E_IR_FAIL or other values: Failure 1386 //------------------------------------------------------------------------------------------------- 1387 MS_BOOL MDrv_Seal_NonSecureProcessorSet(MS_U8 u8ProcessorId, MS_BOOL bNonEnable); 1388 //------------------------------------------------------------------------------------------------- 1389 /// Set IR enable function. 1390 /// @ingroup G_SEAL_CONTROL 1391 /// @param bEnable \b IN: TRUE: enable IR, FALSE: disable IR 1392 /// @return E_IR_OK: Success 1393 /// @return E_IR_FAIL or other values: Failure 1394 //------------------------------------------------------------------------------------------------- 1395 MS_BOOL MDrv_Seal_NonSecureProcessorQuery(MS_U8 u8ProcessorId, MS_BOOL *bNonSecure); 1396 //------------------------------------------------------------------------------------------------- 1397 /// Set IR enable function. 1398 /// @ingroup G_SEAL_CONTROL 1399 /// @param bEnable \b IN: TRUE: enable IR, FALSE: disable IR 1400 /// @return E_IR_OK: Success 1401 /// @return E_IR_FAIL or other values: Failure 1402 //------------------------------------------------------------------------------------------------- 1403 MS_BOOL MDrv_Seal_SecureSlaveSet(MS_U32 u32SlaveId, MS_BOOL bSecure); 1404 //------------------------------------------------------------------------------------------------- 1405 /// Set IR enable function. 1406 /// @ingroup G_SEAL_CONTROL 1407 /// @param bEnable \b IN: TRUE: enable IR, FALSE: disable IR 1408 /// @return E_IR_OK: Success 1409 /// @return E_IR_FAIL or other values: Failure 1410 //------------------------------------------------------------------------------------------------- 1411 MS_BOOL MDrv_Seal_SecureSlaveQuery(MS_U32 u32SlaveId, MS_BOOL *pSecure); 1412 //------------------------------------------------------------------------------------------------- 1413 /// Set IR enable function. 1414 /// @ingroup G_SEAL_CONTROL 1415 /// @param bEnable \b IN: TRUE: enable IR, FALSE: disable IR 1416 /// @return E_IR_OK: Success 1417 /// @return E_IR_FAIL or other values: Failure 1418 //------------------------------------------------------------------------------------------------- 1419 MS_BOOL MDrv_Seal_SecureMasterSet(MS_U32 u32MasterId, MS_BOOL bSecure); 1420 //------------------------------------------------------------------------------------------------- 1421 /// Set IR enable function. 1422 /// @ingroup G_SEAL_CONTROL 1423 /// @param bEnable \b IN: TRUE: enable IR, FALSE: disable IR 1424 /// @return E_IR_OK: Success 1425 /// @return E_IR_FAIL or other values: Failure 1426 //------------------------------------------------------------------------------------------------- 1427 MS_BOOL MDrv_Seal_SecureMasterQuery(MS_U32 u32MasterId, MS_BOOL *pSecure); 1428 //------------------------------------------------------------------------------------------------- 1429 /// Set IR enable function. 1430 /// @ingroup G_SEAL_CONTROL 1431 /// @param bEnable \b IN: TRUE: enable IR, FALSE: disable IR 1432 /// @return E_IR_OK: Success 1433 /// @return E_IR_FAIL or other values: Failure 1434 //------------------------------------------------------------------------------------------------- 1435 MS_U32 MDrv_Seal_SetPowerState(EN_POWER_MODE u16PowerState); 1436 //------------------------------------------------------------------------------------------------- 1437 /// Set IR enable function. 1438 /// @ingroup G_SEAL_CONTROL 1439 /// @param bEnable \b IN: TRUE: enable IR, FALSE: disable IR 1440 /// @return E_IR_OK: Success 1441 /// @return E_IR_FAIL or other values: Failure 1442 //------------------------------------------------------------------------------------------------- 1443 MS_BOOL MDrv_Seal_BufferLock(MS_U8 u8BufferLockId, MS_BOOL bLock); 1444 //------------------------------------------------------------------------------------------------- 1445 /// Set IR enable function. 1446 /// @ingroup G_SEAL_INT 1447 /// @param bEnable \b IN: TRUE: enable IR, FALSE: disable IR 1448 /// @return E_IR_OK: Success 1449 /// @return E_IR_FAIL or other values: Failure 1450 //------------------------------------------------------------------------------------------------- 1451 MS_BOOL MDrv_Seal_ENInterrupt(MS_BOOL bEnable); 1452 //------------------------------------------------------------------------------------------------- 1453 /// Set IR enable function. 1454 /// @ingroup G_SEAL_INT 1455 /// @param bEnable \b IN: TRUE: enable IR, FALSE: disable IR 1456 /// @return E_IR_OK: Success 1457 /// @return E_IR_FAIL or other values: Failure 1458 //------------------------------------------------------------------------------------------------- 1459 MS_BOOL MDrv_Seal_AttachCallbackFunc(SEAL_CB_FUNC pSEALCBFunc); 1460 //------------------------------------------------------------------------------------------------- 1461 /// Set IR enable function. 1462 /// @ingroup G_SEAL_INT 1463 /// @param bEnable \b IN: TRUE: enable IR, FALSE: disable IR 1464 /// @return E_IR_OK: Success 1465 /// @return E_IR_FAIL or other values: Failure 1466 //------------------------------------------------------------------------------------------------- 1467 MS_BOOL MDrv_Seal_DispatchCallbackFunc(void); 1468 1469 MS_BOOL MDrv_Seal_CheckSecureRange(MS_PHY phyStartAddr, MS_U32 u32Length, eSeal_CheckSecureRangeType eCheckSecureRangeType); 1470 1471 MS_BOOL MDrv_Seal_QueryBufferLocked(eSeal_Lock eLockId, MS_BOOL* bLocked); 1472 1473 #ifdef MSOS_TYPE_OPTEE 1474 MS_BOOL MDrv_Seal_ChangeIPSecureDMAAbillity(MS_U32 u32ModuleID, MS_U32 u32ModuleParameter, MS_U32 u32IsSecure); 1475 MS_BOOL MDrv_Seal_SetSecureRange(MS_PHY u64phy, MS_U32 u32Length, MS_U32 u32IsSecure); 1476 #endif 1477 1478 #ifdef __cplusplus 1479 } 1480 #endif 1481 1482 #endif // _DRV_SEAL_H_ 1483