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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 ////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// @file drvMSPI_v2.h 98 /// @brief MSPI Driver Interface 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _DRV_MSPI_V2_H_ 103 #define _DRV_MSPI_V2_H_ 104 105 #ifdef __cplusplus 106 extern "C" 107 { 108 #endif 109 110 //------------------------------------------------------------------------------------------------- 111 // Defines 112 //------------------------------------------------------------------------------------------------- 113 // below for utopia20 structure 114 115 116 typedef enum { 117 MDrv_CMD_MSPI_Init_Ext, 118 MDrv_CMD_MSPI_Init, 119 MDrv_CMD_MSPI_Read, 120 MDrv_CMD_MSPI_Write, 121 MDrv_CMD_MSPI_DCConfig, 122 MDrv_CMD_MSPI_CLKConfig, 123 MDrv_CMD_MSPI_FRAMEConfig, 124 MDrv_CMD_MSPI_SlaveEnable, 125 MDrv_CMD_MSPI_SetPowerState, 126 MDrv_CMD_MSPI_DbgLEvel, 127 MDrv_CMD_MasterSPI_Init_Ext, 128 MDrv_CMD_MasterSPI_Init, 129 MDrv_CMD_MasterSPI_Read, 130 MDrv_CMD_MasterSPI_Write, 131 MDrv_CMD_MasterSPI_DCConfig, 132 MDrv_CMD_MasterSPI_CLKConfig, 133 MDrv_CMD_MasterSPI_FRAMEConfig, 134 MDrv_CMD_MasterSPI_SlaveEnable, 135 MDrv_CMD_MasterSPI_CSPadConfig, 136 MDrv_CMD_MasterSPI_MaxClkConfig, 137 } eMSPIIoctlOpt; 138 139 //------------------------------------------------------------------------------------------------- 140 // Macros 141 //------------------------------------------------------------------------------------------------- 142 143 144 //------------------------------------------------------------------------------------------------- 145 // Type and Structure Declaration 146 //------------------------------------------------------------------------------------------------- 147 148 typedef struct _MPSI_INIT_EXT 149 { 150 MS_U8 u8HWNum; 151 }MSPI_INIT_EXT, *PMSPI_INIT_EXT; 152 153 typedef struct _MSPI_INIT 154 { 155 MSPI_config *ptMSPIConfig; 156 MS_U8 u8HWNum; 157 }MSPI_INIT, *PMSPI_INIT; 158 159 typedef struct _MSPI_READ 160 { 161 MS_U8 *pu8Data; 162 MS_U16 u16Size; 163 }MSPI_READ, *PMSPI_READ; 164 165 typedef struct _MSPI_WRITE 166 { 167 MS_U8 *pu8Data; 168 MS_U16 u16Size; 169 }MSPI_WRITE, *PMSPI_WRITE; 170 171 typedef struct _MSPI_DCCONFIG 172 { 173 MSPI_DCConfig *ptDCConfig; 174 }MSPI_DCCONFIG, *PMSPI_DCCONFIG; 175 176 typedef struct _MSPI_CLKCONFIG 177 { 178 MSPI_CLKConfig *ptCLKConfig; 179 }MSPI_CLKCONFIG, *PMSPI_CLKCONFIG; 180 181 typedef struct _MSPI_FRAMECONFIG 182 { 183 MSPI_FrameConfig *ptFrameConfig; 184 }MSPI_FRAMECONFIG, *PMSPI_FRAMECONFIG; 185 186 typedef struct _MSPI_SLAVE_ENABLE 187 { 188 MS_BOOL bEnable; 189 }MSPI_SLAVE_ENABLE, *PMSPI_SLAVE_ENABLE; 190 191 typedef struct _MSPI_SETPOWERSTATE 192 { 193 EN_POWER_MODE enPowerState; 194 }MSPISETPOWERSTATE, *PMSPISETPOWERSTATE; 195 196 typedef struct _MASTERSPI_READ 197 { 198 MS_U32 u32DevID; 199 MS_U8 *pu8Data; 200 MS_U16 u16Size; 201 }MASTERSPI_READ, *PMASTERSPI_READ; 202 203 typedef struct _MASTERSPI_WRITE 204 { 205 MS_U32 u32DevID; 206 MS_U8 *pu8Data; 207 MS_U16 u16Size; 208 }MASTERSPI_WRITE, *PMASTERSPI_WRITE; 209 210 typedef struct _MASTERSPI_DCCONFIG 211 { 212 MS_U32 u32DevID; 213 MSPI_DCConfig *ptDCConfig; 214 }MASTERSPI_DCCONFIG, *PMASTERSPI_DCCONFIG; 215 216 typedef struct _MASTERSPI_CLKCONFIG 217 { 218 MS_U32 u32DevID; 219 MSPI_CLKConfig *ptCLKConfig; 220 }MASTERSPI_CLKCONFIG, *PMASTERSPI_CLKCONFIG; 221 222 typedef struct _MASTERSPI_FRAMECONFIG 223 { 224 MS_U32 u32DevID; 225 MSPI_FrameConfig *ptFrameConfig; 226 }MASTERSPI_FRAMECONFIG, *PMASTERSPI_FRAMECONFIG; 227 228 typedef struct _MASTERSPI_SLAVE_ENABLE 229 { 230 MS_U32 u32DevID; 231 MS_BOOL bEnable; 232 }MASTERSPI_SLAVE_ENABLE, *PMASTERSPI_SLAVE_ENABLE; 233 234 typedef struct _MASTERSPI_CSPADCONFIG 235 { 236 MS_U32 u32DevID; 237 MS_U32 u32CsPad; 238 }MASTERSPI_CS_PADCONFIG, *PMASTERSPI_CSPADCONFIG; 239 240 typedef struct _MASTERSPI_MAXCLKCONFIG 241 { 242 MS_U32 u32DevID; 243 MS_U32 u32MaxClk; 244 }MASTERSPI_MAXCLKCONFIG, *PMASTERSPI_MAXCLKCONFIG; 245 246 typedef struct _MSPI_SETDBGLEVEL 247 { 248 MS_U8 u8DbgLevel; 249 }MSPI_SETDBGLEVEL, *PMSPI_SETDBGLEVEL; 250 251 252 //MSPI DRV For Local Dimming API Structure Declaration 253 254 //ST_DRV_MSPI_INFO describe mspi spec 255 typedef struct 256 { 257 MS_U8 u8MspiChanel; //mspi chanel 258 MS_U8 u8MspiMode; //mspi triggle mode 259 MS_U32 u32MspiClk; //spi clk 260 MS_U8 u8WBitConfig[8]; //write mode :The bits for per byte 261 MS_U8 u8RBitConfig[8]; //read mode :The bits for per byte 262 MS_U8 u8TrStart; //start delay time The time from "reg_MSPI_trigger" to first SPI clock 263 MS_U8 u8TrEnd; //end delay time The time from last SPI clock to "reg_MSPI_done_flag" 264 MS_U8 u8TB; //The time between byte to byte transfer 265 MS_U8 u8TRW; //The time between last write and first read 266 }ST_DRV_MSPI_INFO; 267 268 //------------------------------------------------------------------------------------------------- 269 // Extern Global Variabls 270 //------------------------------------------------------------------------------------------------- 271 272 //------------------------------------------------------------------------------------------------- 273 // Extern Functions 274 //------------------------------------------------------------------------------------------------- 275 276 ////////////////////////////////////////////////////////////// 277 278 #ifdef __cplusplus 279 } 280 #endif 281 282 #endif // _DRV_MSPI_V2_H_ 283 284