1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34 // kind. Any warranties are hereby expressly disclaimed by MStar, including 35 // without limitation, any warranties of merchantability, non-infringement of 36 // intellectual property rights, fitness for a particular purpose, error free 37 // and in conformity with any international standard. You agree to waive any 38 // claim against MStar for any loss, damage, cost or expense that you may 39 // incur related to your use of MStar Software. 40 // In no event shall MStar be liable for any direct, indirect, incidental or 41 // consequential damages, including without limitation, lost of profit or 42 // revenues, lost or damage of data, and unauthorized system use. 43 // You agree that this Section 4 shall still apply without being affected 44 // even if MStar Software has been modified by MStar in accordance with your 45 // request or instruction for your use, except otherwise agreed by both 46 // parties in writing. 47 // 48 // 5. If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 //////////////////////////////////////////////////////////////////////////////// 79 // 80 // Copyright (c) 2006-2009 MStar Semiconductor, Inc. 81 // All rights reserved. 82 // 83 // Unless otherwise stipulated in writing, any and all information contained 84 // herein regardless in any format shall remain the sole proprietary of 85 // MStar Semiconductor Inc. and be kept in strict confidence 86 // ("MStar Confidential Information") by the recipient. 87 // Any unauthorized act including without limitation unauthorized disclosure, 88 // copying, use, reproduction, sale, distribution, modification, disassembling, 89 // reverse engineering and compiling of the contents of MStar Confidential 90 // Information is unlawful and strictly prohibited. MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// @file drvIPAPool.h 98 /// @brief drv IPA Pool Control Interface 99 /// @author MStar Semiconductor,Inc. 100 /// 101 //////////////////////////////////////////////////////////////////////////////////////////////////// 102 #ifndef _DRVCMAPOOL_H_ 103 #define _DRVCMAPOOL_H_ 104 105 #if defined (CONFIG_MSTAR_IPAPOOL) 106 #ifdef __cplusplus 107 extern "C" 108 { 109 #endif 110 111 #include "MsTypes.h" 112 #define TEST_USE_SELF_KO_MAKEFILE_TOTAL 0//do not enable this in p4.this only test code. 113 114 #define IPAPOOL_HEAP_NAME_MAX_LEN_Param 32 115 116 enum IPA_SPACE_TYPE 117 { 118 IPA_SPACE_TYPE_PA = 0,//directly PA space 119 IPA_SPACE_TYPE_CMA = 1, //CMA space 120 IPA_IPA_SPACE_TYPE_INVALID = 0xFFFFFFFF//force enum size to be 4 byte alignment 121 }; 122 123 struct IPA_Pool_InstallIpcHandle_Param 124 { 125 MS_U32 ipc_handle_id; //in: returned by kernel, when get IPC handle 126 MS_U32 pool_handle_id; //out: pool handle id 127 MS_S32 error_code; // out: error code when failed 128 }; 129 130 struct IPA_Pool_GetIpcHandle_Param 131 { 132 MS_U32 pool_handle_id; //in: pool handle id, when pool init, returned by kernel 133 MS_U32 ipc_handle_id; //out: returned by kernel 134 MS_S32 error_code; // out: error code when failed 135 }; 136 137 struct IPA_Pool_Heap_Attr_Param 138 { 139 MS_U32 heap_id; //in: maybe shared with more than one pools which based on this heap 140 141 char name[IPAPOOL_HEAP_NAME_MAX_LEN_Param]; //out: heap name 142 MS_U64 heap_miu_start_offset; //out: heap start offset in miu 143 MS_U64 heap_length; //out: heap length 144 MS_U32 miu; //out: miu id this heap belongs, index from 0. 145 enum IPA_SPACE_TYPE heap_type;//out: return heap type to application (enum IPA_SPACE_TYPE ) 146 MS_S32 error_code; // error code when failed 147 }; 148 enum IPA_DCACHE_FLUSH_TYPE_Param 149 { 150 IPA_DCACHE_FLUSH_Param,//flush dcache into DRAM 151 IPA_DCACHE_INVALID_Param,// invalid dcache lines 152 IPA_DCACHE_FLUSH_INVALID_Param// flush and invalid dcache lines 153 }; 154 155 struct IPA_Pool_DCacheFlush_Param 156 { 157 MS_U64 virt_addr; //in: the VA need to flush 158 MS_U64 length; //in: flush length 159 enum IPA_DCACHE_FLUSH_TYPE_Param flush_type;// in: flush type (enum IPA_DCACHE_FLUSH_TYPE) 160 }; 161 162 struct IPA_Pool_Unmap_Param 163 { 164 MS_U64 virt_addr; //in: the VA need to unmap 165 MS_U64 length; //in: unmap length 166 }; 167 168 //enum for mapping virtual address type 169 enum IPA_MAP_VA_TYPE_Param 170 { 171 IPA_MAP_VA_NO_NEEDED_Param = 0, //we don't need to map VA 172 IPA_VA_CACHE_WRITE_BACK_Param = 1, //we need to map VA with cache type "write back", which is normally used 173 IPA_VA_CACHE_WRITE_THROUGH_Param = 2, //we need to map VA with cache type "write through", which is //mostly used by graphic system 174 IPA_VA_CACHE_NONE_CACHE_Param = 3, //we don't need data cache 175 IPA_VA_TYPE_MAX_Param = 0xFFFFFFFF//force enum size to be 4 byte alignment 176 }; 177 178 struct IPA_Pool_Map_Param 179 { 180 MS_U32 pool_handle_id; //in: pool handle id, when pool init, returned by kernel 181 MS_U64 offset_in_pool; //in: offset in pool 182 MS_U64 length; //in get memory length 183 enum IPA_MAP_VA_TYPE_Param cache_type; //in cache type of mapping 184 185 MS_U64 virt_addr; //out: virtual address for user mode access 186 MS_S32 error_code; // out�� reason about why map failed 187 }; 188 189 190 struct IPA_Pool_PutMem_Param 191 { 192 MS_U32 pool_handle_id; //in: pool handle id, when pool init, returned by kernel 193 MS_U64 offset_in_pool; //in: offset in pool 194 MS_U64 length; //in 195 }; 196 197 struct IPA_Pool_GetMem_Param 198 { 199 MS_U32 pool_handle_id; //in: pool handle id, when pool init, returned by kernel 200 MS_U64 offset_in_pool; //in: offset in pool 201 MS_U64 length; //in get memory length 202 MS_S32 error_code; // out�� reason about why MApi_IPA_Pool_GetMem failed 203 }; 204 205 struct IPA_Pool_Init_Param 206 { 207 MS_U32 space_id; //in: space id the pool will be created in 208 char *pool_name;//in: global identify name for pool to shared between multiple process 209 210 MS_U64 offset_in_heap; //in: pool location in space 211 MS_U64 len; //in: pool length in space 212 213 MS_U32 pool_handle_id; //out: generate pool id based on space specified by space_id 214 MS_U32 miu; //out: miu id this space belongs, index from 0. 215 enum IPA_SPACE_TYPE space_type;//out: return space type to application 216 MS_S32 error_code; // error code when pool init failed 217 218 MS_U64 space_length; //out: space leagth 219 MS_U64 space_miu_start_offset; //out: space start offset in miu 220 }; 221 222 223 enum IPA_event_Param 224 { 225 IPA_EVENT_FREE_Param = 0, 226 IPA_EVENT_NO_WAIT_Param, 227 IPA_EVNET_NUM_Param 228 }; 229 230 struct IPA_Pool_Event_Param 231 { 232 enum IPA_event_Param event; 233 MS_U32 pool_handle_id; 234 }; 235 236 struct IPA_Pool_Polling_Param 237 { 238 MS_U32 pool_handle_id;//pool handle 239 void (*polling_callback)(MS_U32 pool_handle_id,MS_U64 start,MS_U64 length); 240 }; 241 242 243 ////////////////////////////////////// 244 // function for utopia2.0 //////////// 245 ////////////////////////////////////// 246 MS_BOOL __attribute__((weak)) MApi_IPA_Pool_Init(struct IPA_Pool_Init_Param * Init_Param); 247 MS_BOOL __attribute__((weak)) MApi_IPA_Pool_Release(MS_U32 pool_handle_id); 248 MS_BOOL __attribute__((weak)) MApi_IPA_Pool_GetMem(struct IPA_Pool_GetMem_Param * get_param); 249 MS_BOOL __attribute__((weak)) MApi_IPA_Pool_PutMem(struct IPA_Pool_PutMem_Param * put_param); 250 251 MS_BOOL __attribute__((weak)) MApi_IPA_Pool_MapVA(struct IPA_Pool_Map_Param * map_param); 252 void __attribute__((weak)) MApi_IPA_Pool_UnmapVA(struct IPA_Pool_Unmap_Param * unmap_param); 253 MS_BOOL __attribute__((weak)) MApi_IPA_Pool_MapKerVA(struct IPA_Pool_Map_Param * map_param); 254 void __attribute__((weak)) MApi_IPA_Pool_UnmapKerVA(struct IPA_Pool_Unmap_Param * unmap_param); 255 256 MS_BOOL __attribute__((weak)) MApi_IPA_Pool_DCacheFlush(struct IPA_Pool_DCacheFlush_Param* dcache_flush_param); 257 MS_BOOL __attribute__((weak)) MApi_IPA_Pool_HEAP_ATTR(struct IPA_Pool_Heap_Attr_Param* heap_attr_param); 258 MS_BOOL __attribute__((weak)) MApi_IPA_Pool_GETIPCHANDLE(struct IPA_Pool_GetIpcHandle_Param* getipchandle_param); 259 MS_BOOL __attribute__((weak)) MApi_IPA_Pool_InstallIpcHandle(struct IPA_Pool_InstallIpcHandle_Param* installipchandle_param); 260 MS_BOOL __attribute__((weak)) MApi_IPA_Pool_GetMem_Timeout(struct IPA_Pool_GetMem_Param* get_param,MS_U32 timeout); 261 MS_BOOL __attribute__((weak)) MApi_IPA_Pool_Notify(struct IPA_Pool_Polling_Param *polling_param); 262 #ifdef __cplusplus 263 } 264 #endif 265 #endif 266 #endif 267