xref: /utopia/UTPA2-700.0.x/mxlib/include/drvDMD_common.h (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)
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94 
95 ///////////////////////////////////////////////////////////////////////////////////////////////////
96 ///
97 /// @file   drvDMD_common.h
98 /// @brief  DVBC Driver Interface
99 /// @author MStar Semiconductor Inc.
100 ///////////////////////////////////////////////////////////////////////////////////////////////////
101 
102 #ifndef _DRV_DMD_COMMON_H_
103 #define _DRV_DMD_COMMON_H_
104 
105 #ifdef __cplusplus
106 extern "C"
107 {
108 #endif
109 
110 
111 //-------------------------------------------------------------------------------------------------
112 //  Driver Capability
113 //-------------------------------------------------------------------------------------------------
114 
115 
116 //-------------------------------------------------------------------------------------------------
117 //  Macro and Define
118 //-------------------------------------------------------------------------------------------------
119 #define USE_UTOPIA2P0
120 
121 //-------------------------------------------------------------------------------------------------
122 //  Type and Structure
123 //-------------------------------------------------------------------------------------------------
124 typedef enum
125 {
126     _QPSK        = 0x0,
127     _16QAM        = 0x1,
128     _64QAM        = 0x2,
129     _UNKNOW_QAM   = 0xff,
130 }DMD_CONSTEL;
131 
132 typedef enum
133 {
134     _CR1Y2        = 0x0,
135     _CR2Y3        = 0x1,
136     _CR3Y4        = 0x2,
137     _CR5Y6        = 0x3,
138     _CR7Y8        = 0x4,
139     _UNKNOW_CR   = 0xff,
140 }DMD_CODERATE;
141 
142 
143 //bryan temp mark
144 #if(1)
145 typedef struct
146 {
147     float   power_db;
148     MS_U8   sar3_val;
149 }DMD_RFAGC_SSI;
150 
151 typedef struct
152 {
153     float   power_db;
154     MS_U8   agc_val;
155 }DMD_IFAGC_SSI;
156 
157 typedef struct
158 {
159     float   attn_db;
160     MS_U8   agc_err;
161 }DMD_IFAGC_ERR;
162 
163 typedef struct
164 {
165     DMD_CONSTEL         constel;
166     DMD_CODERATE        code_rate;
167     float               p_ref;
168 }DMD_SSI_DBM_NORDIGP1;
169 
170 typedef struct
171 {
172     DMD_CONSTEL   constel;
173     DMD_CODERATE   code_rate;
174     float   cn_ref;
175 }DMD_SQI_CN_NORDIGP1;
176 
177 typedef struct
178 {
179     DMD_RFAGC_SSI *pRfagcSsi;
180     MS_U16 u16RfagcSsi_Size;
181     DMD_IFAGC_SSI *pIfagcSsi_LoRef;
182     MS_U16 u16IfagcSsi_LoRef_Size;
183     DMD_IFAGC_SSI *pIfagcSsi_HiRef;
184     MS_U16 u16IfagcSsi_HiRef_Size;
185     DMD_IFAGC_ERR *pIfagcErr_LoRef;
186     MS_U16 u16IfagcErr_LoRef_Size;
187     DMD_IFAGC_ERR *pIfagcErr_HiRef;
188     MS_U16 u16IfagcErr_HiRef_Size;
189 }DMD_SSI_TABLE;
190 #endif
191 typedef struct _s_I2C_Interface_func
192 {
193     MS_BOOL (*I2C_WriteBytes)(MS_U16 u16BusNumSlaveID, MS_U8 u8addrcount, MS_U8* pu8addr, MS_U16 u16size, MS_U8* pu8data);
194     MS_BOOL (*I2C_ReadBytes)(MS_U16 u16BusNumSlaveID, MS_U8 u8AddrNum, MS_U8* paddr, MS_U16 u16size, MS_U8* pu8data);
195 }s_I2C_Interface_func;
196 
197 
198 //-------------------------------------------------------------------------------------------------
199 //  Function and Variable
200 //-------------------------------------------------------------------------------------------------
201 DLL_PUBLIC MS_BOOL MDrv_DMD_PreInit(void);
202 DLL_PUBLIC void MDrv_DMD_RFAGC_Tristate(MS_BOOL bEnable);
203 DLL_PUBLIC void MDrv_DMD_IFAGC_Tristate(MS_BOOL bEnable);
204 
205 /************************************************************************************************
206   Subject:    MDrv_DMD_TSO_Clk_Control
207   Function:   ts output clock frequency and phase configure
208   Parmeter:   u8cmd_array, clock div,           0x01, div (0x00~0x1f),
209                            clock phase inv,     0x02, inv_en (0,1),
210                            clock phase tuning,  0x03, phase_tuning_en (0,1), tuning_num (0x00~0x1f)
211   Return:     MS_BOOL
212   Remark:
213 *************************************************************************************************/
214 DLL_PUBLIC MS_BOOL MDrv_DMD_TSO_Clk_Control(MS_U8 *u8cmd_array);
215 DLL_PUBLIC MS_BOOL MDrv_DMD_ReadReg(MS_U32 u32Reg, MS_U8 *u8Value);
216 DLL_PUBLIC MS_BOOL MDrv_DMD_WriteReg(MS_U32 u32Reg, MS_U8 u8Value);
217 DLL_PUBLIC MS_BOOL MDrv_DMD_WriteRegs(MS_U32 u32Reg, MS_U8 *u8Value, MS_U8 u8Length);
218 DLL_PUBLIC MS_BOOL MDrv_DMD_I2C_Channel_Change(MS_U8 ch_num);
219 DLL_PUBLIC MS_BOOL MDrv_DMD_I2C_Channel_Set(MS_U8  ch_num);
220 
221 DLL_PUBLIC MS_BOOL MDrv_DMD_SSPI_Init(MS_U8  u8DeviceNum);
222 DLL_PUBLIC MS_BOOL MDrv_DMD_SSPI_MIU_Writes(MS_U32 u32Addr, MS_U8 *pdata, MS_U16 u16Size);
223 DLL_PUBLIC MS_BOOL MDrv_DMD_SSPI_MIU_Reads(MS_U32 u32Addr, MS_U8 *pdata, MS_U16 u16Size);
224 DLL_PUBLIC MS_BOOL MDrv_DMD_SSPI_RIU_Write8(MS_U16 u16Addr, MS_U8 data);
225 DLL_PUBLIC MS_BOOL MDrv_DMD_SSPI_RIU_Read8(MS_U16 u16Addr, MS_U8 *pdata);
226 #ifdef __cplusplus
227 }
228 #endif
229 
230 
231 #endif // _DRV_DVBC_H_
232 
233