1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34 // kind. Any warranties are hereby expressly disclaimed by MStar, including 35 // without limitation, any warranties of merchantability, non-infringement of 36 // intellectual property rights, fitness for a particular purpose, error free 37 // and in conformity with any international standard. You agree to waive any 38 // claim against MStar for any loss, damage, cost or expense that you may 39 // incur related to your use of MStar Software. 40 // In no event shall MStar be liable for any direct, indirect, incidental or 41 // consequential damages, including without limitation, lost of profit or 42 // revenues, lost or damage of data, and unauthorized system use. 43 // You agree that this Section 4 shall still apply without being affected 44 // even if MStar Software has been modified by MStar in accordance with your 45 // request or instruction for your use, except otherwise agreed by both 46 // parties in writing. 47 // 48 // 5. If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 //////////////////////////////////////////////////////////////////////////////// 79 // 80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc. 81 // All rights reserved. 82 // 83 // Unless otherwise stipulated in writing, any and all information contained 84 // herein regardless in any format shall remain the sole proprietary of 85 // MStar Semiconductor Inc. and be kept in strict confidence 86 // ("MStar Confidential Information") by the recipient. 87 // Any unauthorized act including without limitation unauthorized disclosure, 88 // copying, use, reproduction, sale, distribution, modification, disassembling, 89 // reverse engineering and compiling of the contents of MStar Confidential 90 // Information is unlawful and strictly prohibited. MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// @file drvDMD_DVBT2_INTERN.h 98 /// @brief DVBT Driver Interface 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _DRV_DVBT2_H_ 103 #define _DRV_DVBT2_H_ 104 105 #include "MsTypes.h" 106 107 #include "MsCommon.h" 108 #include "drvDMD_common.h" 109 #ifdef __cplusplus 110 extern "C" 111 { 112 #endif 113 114 115 //------------------------------------------------------------------------------------------------- 116 // Driver Capability 117 //------------------------------------------------------------------------------------------------- 118 119 120 //------------------------------------------------------------------------------------------------- 121 // Macro and Define 122 //------------------------------------------------------------------------------------------------- 123 #define MSIF_DMD_DVBT2_INTERN_LIB_CODE {'D','V', 'B','T'} //Lib code 124 #define MSIF_DMD_DVBT2_INTERN_LIBVER {'0','1'} //LIB version 125 #define MSIF_DMD_DVBT2_INTERN_BUILDNUM {'2','1' } //Build Number 126 #define MSIF_DMD_DVBT2_INTERN_CHANGELIST {'0','0','0','0','0','0','0','0'} //P4 ChangeList Number 127 128 #define DMD_DVBT2_INTERN_VER /* Character String for DRV/API version */ \ 129 MSIF_TAG, /* 'MSIF' */ \ 130 MSIF_CLASS, /* '00' */ \ 131 MSIF_CUS, /* 0x0000 */ \ 132 MSIF_MOD, /* 0x0000 */ \ 133 MSIF_CHIP, \ 134 MSIF_CPU, \ 135 MSIF_DMD_DVBT2_INTERN_LIB_CODE, /* IP__ */ \ 136 MSIF_DMD_DVBT2_INTERN_LIBVER, /* 0.0 ~ Z.Z */ \ 137 MSIF_DMD_DVBT2_INTERN_BUILDNUM, /* 00 ~ 99 */ \ 138 MSIF_DMD_DVBT2_INTERN_CHANGELIST, /* CL# */ \ 139 MSIF_OS 140 141 #define IS_BITS_SET(val, bits) (((val)&(bits)) == (bits)) 142 143 //------------------------------------------------------------------------------------------------- 144 // Type and Structure 145 //------------------------------------------------------------------------------------------------- 146 typedef enum 147 { 148 DMD_T2_DBGLV_NONE, // disable all the debug message 149 DMD_T2_DBGLV_INFO, // information 150 DMD_T2_DBGLV_NOTICE, // normal but significant condition 151 DMD_T2_DBGLV_WARNING, // warning conditions 152 DMD_T2_DBGLV_ERR, // error conditions 153 DMD_T2_DBGLV_CRIT, // critical conditions 154 DMD_T2_DBGLV_ALERT, // action must be taken immediately 155 DMD_T2_DBGLV_EMERG, // system is unusable 156 DMD_T2_DBGLV_DEBUG, // debug-level messages 157 } DMD_T2_DbgLv; 158 159 typedef enum 160 { 161 E_DMD_T2_LOCK, 162 E_DMD_T2_CHECKING, 163 E_DMD_T2_CHECKEND, 164 E_DMD_T2_UNLOCK, 165 E_DMD_T2_NULL, 166 } DMD_T2_LOCK_STATUS; 167 168 typedef enum 169 { 170 E_DMD_DVBT2_GETLOCK, 171 E_DMD_DVBT2_FEC_LOCK, 172 E_DMD_DVBT2_P1_LOCK, 173 E_DMD_DVBT2_DCR_LOCK, 174 E_DMD_DVBT2_AGC_LOCK, 175 E_DMD_DVBT2_MODE_DET, 176 E_DMD_DVBT2_P1_EVER_LOCK, 177 E_DMD_DVBT2_L1_CRC_LOCK, 178 E_DMD_DVBT2_NO_CHANNEL, 179 E_DMD_DVBT2_NO_CHANNEL_IFAGC, 180 E_DMD_DVBT2_ATV_DETECT, 181 E_DMD_DVBT2_BER_LOCK, 182 E_DMD_DVBT2_SNR_LOCK, 183 } DMD_DVBT2_GETLOCK_TYPE; 184 185 typedef enum 186 { 187 E_DMD_T2_RF_BAND_5MHz = 0x01, 188 E_DMD_T2_RF_BAND_1p7MHz = 0x00, 189 E_DMD_T2_RF_BAND_6MHz = 0x02, 190 E_DMD_T2_RF_BAND_7MHz = 0x03, 191 E_DMD_T2_RF_BAND_8MHz = 0x04, 192 E_DMD_T2_RF_BAND_10MHz = 0x05, 193 E_DMD_T2_RF_BAND_INVALID 194 } DMD_DVBT2_RF_CHANNEL_BANDWIDTH; 195 196 typedef enum 197 { 198 // fw version, check sum 199 E_DMD_T2_CHECK_SUM_L = 0x00, 200 E_DMD_T2_CHECK_SUM_H, 201 E_DMD_T2_FW_VER_0, 202 E_DMD_T2_FW_VER_1, 203 E_DMD_T2_FW_VER_2, 204 205 // operation mode 206 E_DMD_T2_ZIF_EN = 0x20, 207 E_DMD_T2_RF_AGC_EN, 208 E_DMD_T2_HUM_DET_EN, 209 E_DMD_T2_DCR_EN, 210 E_DMD_T2_IQB_EN, 211 E_DMD_T2_IIS_EN, 212 E_DMD_T2_CCI_EN, 213 E_DMD_T2_LOW_PWR_DET_EN, 214 E_DMD_T2_ACI_DET_EN, 215 E_DMD_T2_TD_MOTION_EN, 216 E_DMD_T2_FD_MOTION_EN, 217 218 // channel tuning param 219 E_DMD_T2_BW = 0x40, 220 E_DMD_T2_FC_L = 0x41, 221 E_DMD_T2_FC_H = 0x42, 222 E_DMD_T2_FS_L, 223 E_DMD_T2_FS_H, 224 E_DMD_T2_ZIF, 225 E_DMD_T2_GI, 226 E_DMD_T2_ACI_DET_TYPE, 227 E_DMD_T2_AGC_REF, //0x48 228 E_DMD_T2_RSSI_REF, 229 E_DMD_T2_SNR_TIME_L, 230 E_DMD_T2_SNR_TIME_H, 231 E_DMD_T2_BER_CMP_TIME_L, 232 E_DMD_T2_BER_CMP_TIME_H, 233 E_DMD_T2_SFO_CFO_NUM, 234 E_DMD_T2_CCI, 235 E_DMD_T2_ACI_DET_TH_L, //0x50 236 E_DMD_T2_ACI_DET_TH_H, 237 E_DMD_T2_TS_SERIAL = 0x52, 238 E_DMD_T2_TS_CLK_RATE = 0x53, 239 E_DMD_T2_TS_OUT_INV = 0x54, 240 E_DMD_T2_TS_DATA_SWAP = 0x55, 241 E_DMD_T2_TDP_CCI_KP, 242 E_DMD_T2_CCI_FSWEEP, //0x57 243 E_DMD_T2_TS_ERR_POL, //0x58 244 E_DMD_T2_IF_AGC_INV_PWM_EN, // 0x59 245 E_DMD_T2_CCI_TYPE, //0x5A 246 E_DMD_T2_LITE, //0x5B 247 248 E_DMD_T2_TOTAL_CFO_0 = 0x85, 249 E_DMD_T2_TOTAL_CFO_1, 250 251 // EQ of SDRAM arrangement 252 E_T2EQ_START_ADDR_0 = 0x90, 253 E_T2EQ_START_ADDR_1, 254 E_T2EQ_START_ADDR_2, 255 E_T2EQ_START_ADDR_3, 256 257 // TDI of SDRAM arrangement 258 E_T2TDI_START_ADDR_0, 259 E_T2TDI_START_ADDR_1, 260 E_T2TDI_START_ADDR_2, 261 E_T2TDI_START_ADDR_3, 262 263 // DJB of SDRAM arrangement 264 E_T2DJB_START_ADDR_0, 265 E_T2DJB_START_ADDR_1, 266 E_T2DJB_START_ADDR_2, 267 E_T2DJB_START_ADDR_3, 268 269 // DJB of SDRAM arrangement 270 E_T2FW_START_ADDR_0, 271 E_T2FW_START_ADDR_1, 272 E_T2FW_START_ADDR_2, 273 E_T2FW_START_ADDR_3, 274 275 // dvbt2 lock history 276 E_DMD_T2_DVBT2_LOCK_HIS = 0xF0, 277 E_DMD_T2_FEF_DET_IND, 278 E_DMD_T2_MPLP_NO_COMMON_IND, 279 E_DMD_T2_SNR_L, // 0xf3 280 E_DMD_T2_SNR_H, // 0xf4 281 E_DMD_T2_DOPPLER_DET_FLAG, // 0xf5 282 E_DMD_T2_DOPPLER_DET_TH_L, // 0xf6 283 E_DMD_T2_DOPPLER_DET_TH_H, // 0xf7 284 285 // splp, mplp releted 286 E_DMD_T2_PLP_ID_ARR = 0x100, 287 E_DMD_T2_L1_FLAG = 0x120, 288 E_DMD_T2_PLP_ID, 289 E_DMD_T2_GROUP_ID, 290 291 //dvbt2 auto ts data rate 292 E_DMD_T2_TS_DATA_RATE_0 = 0x130, 293 E_DMD_T2_TS_DATA_RATE_1 = 0x131, 294 E_DMD_T2_TS_DATA_RATE_2 = 0x132, 295 E_DMD_T2_TS_DATA_RATE_3 = 0x133, 296 E_DMD_T2_TS_DATA_RATE_CHANGE_IND = 0x134, 297 E_DMD_T2_TS_DIV_172 = 0x135, 298 E_DMD_T2_TS_DIV_288 = 0x136, 299 E_DMD_T2_TS_DIV_432 = 0x137, 300 E_DMD_T2_PARAM_NUM, 301 } DVBT2_PARAM; 302 303 typedef enum 304 { 305 _T2_QPSK = 0x0, 306 _T2_16QAM = 0x1, 307 _T2_64QAM = 0x2, 308 _T2_256QAM = 0x3, 309 _T2_QAM_UNKNOWN = 0xFF, 310 } DMD_T2_CONSTEL; 311 312 typedef enum 313 { 314 _T2_CR1Y2 = 0x0, 315 _T2_CR3Y5 = 0x1, 316 _T2_CR2Y3 = 0x2, 317 _T2_CR3Y4 = 0x3, 318 _T2_CR4Y5 = 0x4, 319 _T2_CR5Y6 = 0x5, 320 _T2_CR_UNKNOWN = 0xFF, 321 } DMD_T2_CODERATE; 322 323 typedef struct 324 { 325 DMD_T2_CONSTEL constel; 326 DMD_T2_CODERATE code_rate; 327 float p_ref; 328 }DMD_T2_SSI_DBM_NORDIGP1; 329 330 typedef struct 331 { 332 DMD_T2_CONSTEL constel; 333 DMD_T2_CODERATE code_rate; 334 float cn_ref; 335 }DMD_T2_SQI_CN_NORDIGP1; 336 337 338 // For Interrupt mode 339 typedef enum 340 { 341 E_DMD_DVBT2_INT_UNKNOWN=0, 342 E_DMD_DVBT2_INT_LOCK, 343 E_DMD_DVBT2_INT_UNLOCK 344 } DMD_DVBT2_INT_TYPE; 345 346 #ifdef UFO_DEMOD_DVBT2_SUPPORT_DMD_INT 347 typedef void (*fpIntCallBack)(MS_U8 u8arg); 348 #endif 349 350 351 /// For demod init 352 typedef struct 353 { 354 // tuner parameter 355 MS_U8 u8SarChannel; 356 DMD_RFAGC_SSI *pTuner_RfagcSsi; 357 MS_U16 u16Tuner_RfagcSsi_Size; 358 DMD_IFAGC_SSI *pTuner_IfagcSsi_LoRef; 359 MS_U16 u16Tuner_IfagcSsi_LoRef_Size; 360 DMD_IFAGC_SSI *pTuner_IfagcSsi_HiRef; 361 MS_U16 u16Tuner_IfagcSsi_HiRef_Size; 362 DMD_IFAGC_ERR *pTuner_IfagcErr_LoRef; 363 MS_U16 u16Tuner_IfagcErr_LoRef_Size; 364 DMD_IFAGC_ERR *pTuner_IfagcErr_HiRef; 365 MS_U16 u16Tuner_IfagcErr_HiRef_Size; 366 DMD_T2_SQI_CN_NORDIGP1 *pSqiCnNordigP1; 367 MS_U16 u16SqiCnNordigP1_Size; 368 369 // register init 370 MS_U8 *u8DMD_DVBT2_DSPRegInitExt; // TODO use system variable type 371 MS_U8 u8DMD_DVBT2_DSPRegInitSize; 372 MS_U8 *u8DMD_DVBT2_InitExt; // TODO use system variable type 373 MS_U32 u32EqStartAddr; 374 MS_U32 u32TdiStartAddr; 375 MS_U32 u32DjbStartAddr; 376 MS_U32 u32FwStartAddr; 377 } DMD_DVBT2_InitData; 378 379 typedef enum 380 { 381 E_DMD_DVBT2_FAIL=0, 382 E_DMD_DVBT2_OK=1 383 } DMD_DVBT2_Result; 384 385 386 typedef enum 387 { 388 E_DMD_DVBT2_MODULATION_INFO, 389 E_DMD_DVBT2_DEMOD_INFO, 390 E_DMD_DVBT2_LOCK_INFO, 391 E_DMD_DVBT2_PRESFO_INFO, 392 E_DMD_DVBT2_LOCK_TIME_INFO, 393 E_DMD_DVBT2_BER_INFO, 394 E_DMD_DVBT2_AGC_INFO, 395 } DMD_DVBT2_INFO_TYPE; 396 397 typedef struct 398 { 399 MS_U16 u16Version; 400 MS_U8 u16DemodState; // 401 float SfoValue; // 402 float TotalCfo; // 403 MS_U16 u16ChannelLength; // 404 MS_U8 u8Fft; // 405 MS_U8 u8Constel; // 406 MS_U8 u8Gi; // 407 MS_U8 u8HpCr; // 408 MS_U8 u8LpCr; // 409 MS_U8 u8Hiearchy; // 410 MS_U8 u8Fd; // 411 MS_U8 u8ChLen; // 412 MS_U8 u8SnrSel; // 413 MS_U8 u8PertoneNum; // 414 MS_U8 u8DigAci; // 415 MS_U8 u8FlagCi; // 416 MS_U8 u8TdCoef; // 417 } DMD_DVBT2_Info; 418 419 /******************************************************** 420 *Constellation (b2 ~ b0) : 0~3 => QPSK, 16QAM, 64QAM, 256QAM 421 *Code Rate (b5 ~ b3) : 0~5 => 1/2, 3/5, 2/3, 3/4, 4/5, 5/6 422 *GI (b8 ~ b6) : 0~6 => 1/32, 1/16, 1/8, 1/4, 1/128, 19/128, 19/256 423 *FFT (b11 ~ b9) : 0~7 => 2K, 8K, 4K, 1K, 16K, 32K, 8KE, 32KE 424 *Preamble(b12) : 0~1 => mixed, not_mixed 425 *S1_Signaling(b14~b13) : 0~3 => t2_siso, t2_miso, "non_t2, reserved 426 *pilot_pattern(b18~b15) : 0~8 => PP1, PP2, PP3, PP4, PP5, PP6, PP7, PP8 427 *BW_Extend(b19) : 0~1 => normal, extension 428 *PAPR(b22~b20) : 0~4 => none, ace, tr, tr_and_ace, reserved 429 *OFDM_SYMBOLS_PER_FRAME : 4~2098 430 *PLP_ROTATION : 0/1 => none, rotated constellation 431 *PLP_FEC_TYPE : 0/1 => LDPC_16K, LDPC_64K 432 *NUM_PLP : 1~255 433 *PLP_TYPE : 0~2 => common, Type 1, Type 2 434 *PLP_TIME_IL_TYPE : 0/1 435 *PLP_TIME_IL_LENGTH : 0~3 436 *DAT_ISSY : 0/1 437 *T2_PLP_MODE : 0/1: Normal mode /High Efficiency Mode 438 *L1_MODULATION : 0~3 => BPSK, QPSK, 16QAM, 64QAM 439 *T2_NUM_T2_FRAMES : 2 ~ 255 440 *T2_PLP_NUM_BLOCKS_MAX : 441 *FEF_ENABLE : 0/1 442 ********************************/ 443 typedef enum 444 { 445 T2_MODUL_MODE, 446 T2_FFT_VALUE, 447 T2_GUARD_INTERVAL, 448 T2_CODE_RATE, 449 T2_PREAMBLE, 450 T2_S1_SIGNALLING, 451 T2_PILOT_PATTERN, 452 T2_BW_EXT, 453 T2_PAPR_REDUCTION, 454 T2_OFDM_SYMBOLS_PER_FRAME, 455 T2_PLP_ROTATION, 456 T2_PLP_FEC_TYPE, 457 T2_NUM_PLP, 458 T2_PLP_TYPE, 459 T2_PLP_TIME_IL_TYPE, 460 T2_PLP_TIME_IL_LENGTH, 461 T2_DAT_ISSY, 462 T2_PLP_MODE, 463 T2_L1_MODULATION, 464 T2_NUM_T2_FRAMES, 465 T2_PLP_NUM_BLOCKS_MAX, 466 T2_FEF_ENABLE, 467 T2_PARAM_MAX_NUM, 468 } DMD_DVBT2_SIGNAL_INFO; 469 470 //typedef void(*P_DMD_ISR_Proc)(MS_U8 u8DMDID); 471 472 473 //------------------------------------------------------------------------------------------------- 474 // Function and Variable 475 //------------------------------------------------------------------------------------------------- 476 //////////////////////////////////////////////////////////////////////////////// 477 /// MDrv_DMD_DVBT2_Init 478 //////////////////////////////////////////////////////////////////////////////// 479 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBT2_Init(DMD_DVBT2_InitData *pDMD_DVBT2_InitData, MS_U32 u32InitDataLen); 480 //////////////////////////////////////////////////////////////////////////////// 481 /// Should be called when exit VD input source 482 //////////////////////////////////////////////////////////////////////////////// 483 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBT2_Exit(void); 484 //------------------------------------------------------------------------------ 485 /// Set detailed level of DVBT2 driver debug message 486 /// u8DbgLevel : debug level for Parallel Flash driver\n 487 /// AVD_DBGLV_NONE, ///< disable all the debug message\n 488 /// AVD_DBGLV_INFO, ///< information\n 489 /// AVD_DBGLV_NOTICE, ///< normal but significant condition\n 490 /// AVD_DBGLV_WARNING, ///< warning conditions\n 491 /// AVD_DBGLV_ERR, ///< error conditions\n 492 /// AVD_DBGLV_CRIT, ///< critical conditions\n 493 /// AVD_DBGLV_ALERT, ///< action must be taken immediately\n 494 /// AVD_DBGLV_EMERG, ///< system is unusable\n 495 /// AVD_DBGLV_DEBUG, ///< debug-level messages\n 496 /// @return TRUE : succeed 497 /// @return FALSE : failed to set the debug level 498 //------------------------------------------------------------------------------ 499 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBT2_SetDbgLevel(DMD_T2_DbgLv u8DbgLevel); 500 //------------------------------------------------------------------------------------------------- 501 /// Get the information of DVBT2 driver\n 502 /// @return the pointer to the driver information 503 //------------------------------------------------------------------------------------------------- 504 extern DLL_PUBLIC DMD_DVBT2_Info* MDrv_DMD_DVBT2_GetInfo(DMD_DVBT2_INFO_TYPE eInfoType); 505 //------------------------------------------------------------------------------------------------- 506 /// Get DVBT2 driver version 507 /// when get ok, return the pointer to the driver version 508 //------------------------------------------------------------------------------------------------- 509 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBT2_GetLibVer(const MSIF_Version **ppVersion); 510 //////////////////////////////////////////////////////////////////////////////// 511 /// To get DVBT2's register value, only for special purpose.\n 512 /// u16Addr : the address of DVBT2's register\n 513 /// return the value of AFEC's register\n 514 //////////////////////////////////////////////////////////////////////////////// 515 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBT2_GetReg(MS_U16 u16Addr, MS_U8 *pu8Data); 516 //////////////////////////////////////////////////////////////////////////////// 517 /// To set DVBT2's register value, only for special purpose.\n 518 /// u16Addr : the address of DVBT2's register\n 519 /// u8Value : the value to be set\n 520 //////////////////////////////////////////////////////////////////////////////// 521 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBT2_SetReg(MS_U16 u16Addr, MS_U8 u8Data); 522 //////////////////////////////////////////////////////////////////////////////// 523 /// Get DVBT2 FW version 524 /// u16Addr : the address of DVBT's register\n 525 //////////////////////////////////////////////////////////////////////////////// 526 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBT2_GetFWVer(MS_U16 *ver); 527 528 //////////////////////////////////////////////////////////////////////////////// 529 /// MDrv_DMD_DVBT2_SetSerialControl 530 //////////////////////////////////////////////////////////////////////////////// 531 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBT2_SetSerialControl(MS_BOOL bEnable); 532 //////////////////////////////////////////////////////////////////////////////// 533 /// MDrv_DMD_DVBT2_SetReset 534 //////////////////////////////////////////////////////////////////////////////// 535 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBT2_SetReset(void); 536 //////////////////////////////////////////////////////////////////////////////// 537 /// MDrv_DMD_DVBT2_SetConfig 538 //////////////////////////////////////////////////////////////////////////////// 539 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBT2_SetConfig(DMD_DVBT2_RF_CHANNEL_BANDWIDTH BW, MS_BOOL bSerialTS, MS_U8 u8PlpID); 540 /////////////////////////////////////////////////////////////////////////////// 541 /// MDrv_DMD_DVBT2_SetActive 542 //////////////////////////////////////////////////////////////////////////////// 543 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBT2_SetActive(MS_BOOL bEnable); 544 //////////////////////////////////////////////////////////////////////////////// 545 /// MDrv_DMD_DVBT2_Get_Lock 546 //////////////////////////////////////////////////////////////////////////////// 547 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBT2_GetLock(DMD_DVBT2_GETLOCK_TYPE eType, DMD_T2_LOCK_STATUS *eLockStatus); 548 //////////////////////////////////////////////////////////////////////////////// 549 /// MDrv_DMD_DVBT2_GetSignalStrength 550 //////////////////////////////////////////////////////////////////////////////// 551 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBT2_GetSignalStrength(MS_U16 *u16Strength); 552 //////////////////////////////////////////////////////////////////////////////// 553 /// MDrv_DMD_DVBT2_GetSignalStrengthWithRFPower 554 //////////////////////////////////////////////////////////////////////////////// 555 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBT2_GetSignalStrengthWithRFPower(MS_U16 *u16Strength, float fRFPowerDbm); 556 //////////////////////////////////////////////////////////////////////////////// 557 /// MDrv_DMD_DVBT2_GetSignalQuality 558 //////////////////////////////////////////////////////////////////////////////// 559 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBT2_GetSignalQuality(MS_U16 *u16Quality); 560 //////////////////////////////////////////////////////////////////////////////// 561 /// MDrv_DMD_DVBT2_GetSignalQualityWithRFPower 562 //////////////////////////////////////////////////////////////////////////////// 563 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBT2_GetSignalQualityWithRFPower(MS_U16 *u16Quality, float fRFPowerDbm); 564 //////////////////////////////////////////////////////////////////////////////// 565 /// MDrv_DMD_DVBT2_GetSNR 566 //////////////////////////////////////////////////////////////////////////////// 567 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBT2_GetSNR(float *fSNR); 568 //////////////////////////////////////////////////////////////////////////////// 569 /// MDrv_DMD_DVBT2_GetPostLDPCBer 570 //////////////////////////////////////////////////////////////////////////////// 571 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBT2_GetPostLdpcBer(float *ber); 572 //////////////////////////////////////////////////////////////////////////////// 573 /// MDrv_DMD_DVBT2_GetPreLDPCBer 574 //////////////////////////////////////////////////////////////////////////////// 575 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBT2_GetPreLdpcBer(float *ber); 576 //////////////////////////////////////////////////////////////////////////////// 577 /// MDrv_DMD_DVBT2_GetPacketErr 578 //////////////////////////////////////////////////////////////////////////////// 579 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBT2_GetPacketErr(MS_U16 *pktErr); 580 //////////////////////////////////////////////////////////////////////////////// 581 /// MDrv_DMD_DVBT2_GetL1Info 582 //////////////////////////////////////////////////////////////////////////////// 583 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBT2_GetL1Info(MS_U16 *u16Info, DMD_DVBT2_SIGNAL_INFO eSignalType); 584 //////////////////////////////////////////////////////////////////////////////// 585 /// MDrv_DMD_DVBT2_GetFreqOffset 586 //////////////////////////////////////////////////////////////////////////////// 587 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBT2_GetFreqOffset(float *pFreqOff); 588 //////////////////////////////////////////////////////////////////////////////// 589 /// MDrv_DMD_DVBT2_NORDIG_SSI_Table_Write 590 //////////////////////////////////////////////////////////////////////////////// 591 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBT2_NORDIG_SSI_Table_Write(DMD_T2_CONSTEL constel, DMD_T2_CODERATE code_rate, float write_value); 592 //////////////////////////////////////////////////////////////////////////////// 593 /// MDrv_DMD_DVBT2_NORDIG_SSI_Table_Read 594 //////////////////////////////////////////////////////////////////////////////// 595 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBT2_NORDIG_SSI_Table_Read(DMD_T2_CONSTEL constel, DMD_T2_CODERATE code_rate, float *read_value); 596 597 extern DLL_PUBLIC MS_U32 MDrv_DMD_DVBT2_SetPowerState(EN_POWER_MODE u16PowerState); 598 599 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBT2_GetPlpBitMap(MS_U8* u8PlpBitMap); 600 601 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBT2_GetPlpGroupID(MS_U8 u8PlpID, MS_U8* u8GroupID); 602 603 extern DLL_PUBLIC MS_BOOL MDrv_DMD_DVBT2_SetPlpID(MS_U8 u8PlpID, MS_U8 u8GroupID); 604 605 #ifdef UFO_DEMOD_DVBT2_SUPPORT_DMD_INT 606 MS_BOOL MDrv_DMD_DVBT2_Reg_INT_CB(fpIntCallBack fpCBReg); 607 #endif 608 609 #ifdef __cplusplus 610 } 611 #endif 612 613 614 #endif // _DRV_DVBT_H_ 615 616