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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// @file drvDMD_DVBT_INTERN.h 98 /// @brief DVBT Driver Interface 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _DRV_DVBT_H_ 103 #define _DRV_DVBT_H_ 104 105 #include "MsCommon.h" 106 #include "drvDMD_common.h" 107 #include "MsOS.h" 108 #include "UFO.h" 109 #ifdef __cplusplus 110 extern "C" 111 { 112 #endif 113 114 115 //------------------------------------------------------------------------------------------------- 116 // Driver Capability 117 //------------------------------------------------------------------------------------------------- 118 119 120 //------------------------------------------------------------------------------------------------- 121 // Macro and Define 122 //------------------------------------------------------------------------------------------------- 123 #define MSIF_DMD_DVBT_INTERN_LIB_CODE {'D','V', 'B','T'} //Lib code 124 #define MSIF_DMD_DVBT_INTERN_LIBVER {'0','1'} //LIB version 125 #define MSIF_DMD_DVBT_INTERN_BUILDNUM {'2','1' } //Build Number 126 #define MSIF_DMD_DVBT_INTERN_CHANGELIST {'0','0','0','0','0','0','0','0'} //P4 ChangeList Number 127 128 #define DMD_DVBT_INTERN_VER /* Character String for DRV/API version */ \ 129 MSIF_TAG, /* 'MSIF' */ \ 130 MSIF_CLASS, /* '00' */ \ 131 MSIF_CUS, /* 0x0000 */ \ 132 MSIF_MOD, /* 0x0000 */ \ 133 MSIF_CHIP, \ 134 MSIF_CPU, \ 135 MSIF_DMD_DVBT_INTERN_LIB_CODE, /* IP__ */ \ 136 MSIF_DMD_DVBT_INTERN_LIBVER, /* 0.0 ~ Z.Z */ \ 137 MSIF_DMD_DVBT_INTERN_BUILDNUM, /* 00 ~ 99 */ \ 138 MSIF_DMD_DVBT_INTERN_CHANGELIST, /* CL# */ \ 139 MSIF_OS 140 141 #define IS_BITS_SET(val, bits) (((val)&(bits)) == (bits)) 142 143 //------------------------------------------------------------------------------------------------- 144 // Type and Structure 145 //------------------------------------------------------------------------------------------------- 146 typedef enum 147 { 148 T_DVBT2_NOCHAN_Flag = 0xF1, 149 T_DVBT_NOCHAN_Flag = 0xF2, 150 T_DETECT_DONE_FLAG = 0xF3, 151 } DVT_FLAG; 152 153 typedef enum 154 { 155 DMD_DBGLV_NONE, // disable all the debug message 156 DMD_DBGLV_INFO, // information 157 DMD_DBGLV_NOTICE, // normal but significant condition 158 DMD_DBGLV_WARNING, // warning conditions 159 DMD_DBGLV_ERR, // error conditions 160 DMD_DBGLV_CRIT, // critical conditions 161 DMD_DBGLV_ALERT, // action must be taken immediately 162 DMD_DBGLV_EMERG, // system is unusable 163 DMD_DBGLV_DEBUG, // debug-level messages 164 } DMD_DbgLv; 165 166 typedef enum 167 { 168 E_DMD_LOCK, 169 E_DMD_CHECKING, 170 E_DMD_CHECKEND, 171 E_DMD_UNLOCK, 172 E_DMD_NULL, 173 } DMD_LOCK_STATUS; 174 175 typedef enum 176 { 177 E_DMD_DMD_DVBT_GETLOCK, 178 E_DMD_COFDM_FEC_LOCK, 179 E_DMD_COFDM_PSYNC_LOCK, 180 E_DMD_COFDM_TPS_LOCK, 181 E_DMD_COFDM_DCR_LOCK, 182 E_DMD_COFDM_AGC_LOCK, 183 E_DMD_COFDM_MODE_DET, 184 E_DMD_COFDM_TPS_EVER_LOCK, 185 E_DMD_COFDM_NO_CHANNEL, 186 E_DMD_COFDM_NO_CHANNEL_IFAGC, 187 E_DMD_COFDM_ATV_DETECT, 188 E_DMD_COFDM_BER_LOCK, 189 E_DMD_COFDM_SNR_LOCK, 190 E_DMD_COFDM_TR_LOCK, 191 } DMD_DVBT_GETLOCK_TYPE; 192 193 typedef enum 194 { 195 E_DMD_RF_CH_BAND_6MHz = 0x01, 196 E_DMD_RF_CH_BAND_7MHz = 0x02, 197 E_DMD_RF_CH_BAND_8MHz = 0x03, 198 E_DMD_RF_CH_BAND_INVALID 199 } DMD_RF_CHANNEL_BANDWIDTH; 200 201 typedef enum 202 { 203 E_DMD_DVBT_N_PARAM_VERSION = 0x00, //0x00 204 E_DMD_DVBT_N_OP_RFAGC_EN, 205 E_DMD_DVBT_N_OP_HUMDET_EN, 206 E_DMD_DVBT_N_OP_DCR_EN, 207 E_DMD_DVBT_N_OP_IIS_EN, 208 E_DMD_DVBT_N_OP_CCI_EN, 209 E_DMD_DVBT_N_OP_ACI_EN, 210 E_DMD_DVBT_N_OP_IQB_EN, 211 E_DMD_DVBT_N_OP_AUTO_IQ_SWAP_EN, //0x08 212 E_DMD_DVBT_N_OP_AUTO_RF_MAX_EN, 213 E_DMD_DVBT_N_OP_FORCE_ACI_EN, 214 E_DMD_DVBT_N_OP_FIX_MODE_CP_EN, 215 E_DMD_DVBT_N_OP_FIX_TPS_EN, 216 E_DMD_DVBT_N_OP_AUTO_SCAN_MODE_EN, 217 E_DMD_DVBT_N_CFG_RSSI, 218 E_DMD_DVBT_N_CFG_ZIF, //0x0F 219 220 E_DMD_DVBT_N_CFG_NIF, //0x10 221 E_DMD_DVBT_N_CFG_LIF, 222 E_DMD_DVBT_N_CFG_SAWLESS, 223 E_DMD_DVBT_N_CFG_FS_L, 224 E_DMD_DVBT_N_CFG_FS_H, 225 E_DMD_DVBT_N_CFG_FIF_L, 226 E_DMD_DVBT_N_CFG_FIF_H, 227 E_DMD_DVBT_N_CFG_FC_L, 228 E_DMD_DVBT_N_CFG_FC_H, //0x18 229 E_DMD_DVBT_N_CFG_BW, 230 E_DMD_DVBT_N_CFG_MODE, 231 E_DMD_DVBT_N_CFG_CP, 232 E_DMD_DVBT_N_CFG_LP_SEL, 233 E_DMD_DVBT_N_CFG_CSTL, 234 E_DMD_DVBT_N_CFG_HIER, 235 E_DMD_DVBT_N_CFG_HPCR, //0x1F 236 237 E_DMD_DVBT_N_CFG_LPCR, //0x20 238 E_DMD_DVBT_N_CFG_IQ_SWAP, 239 E_DMD_DVBT_N_CFG_RFMAX, 240 E_DMD_DVBT_N_CFG_CCI, 241 E_DMD_DVBT_N_CFG_ICFO_RANGE, 242 E_DMD_DVBT_N_CFG_RFAGC_REF, 243 E_DMD_DVBT_N_CFG_IFAGC_REF_2K, 244 E_DMD_DVBT_N_CFG_IFAGC_REF_8K, 245 E_DMD_DVBT_N_CFG_IFAGC_REF_ACI, //0x28 246 E_DMD_DVBT_N_CFG_IFAGC_REF_IIS, 247 E_DMD_DVBT_N_CFG_IFAGC_REF_2K_H, 248 E_DMD_DVBT_N_CFG_IFAGC_REF_8K_H, 249 E_DMD_DVBT_N_CFG_IFAGC_REF_ACI_H, 250 E_DMD_DVBT_N_CFG_IFAGC_REF_IIS_H, 251 E_DMD_DVBT_N_CFG_TS_SERIAL, 252 E_DMD_DVBT_N_CFG_TS_CLK_INV, //0x2F 253 254 E_DMD_DVBT_N_CFG_TS_DATA_SWAP, //0x30 255 E_DMD_DVBT_N_CFG_8M_DACI_DET_TH_L, 256 E_DMD_DVBT_N_CFG_8M_DACI_DET_TH_H, 257 E_DMD_DVBT_N_CFG_8M_ANM1_DET_TH_L, 258 E_DMD_DVBT_N_CFG_8M_ANM1_DET_TH_H, 259 E_DMD_DVBT_N_CFG_8M_ANP1_DET_TH_L, 260 E_DMD_DVBT_N_CFG_8M_ANP1_DET_TH_H, 261 E_DMD_DVBT_N_CFG_7M_DACI_DET_TH_L, 262 E_DMD_DVBT_N_CFG_7M_DACI_DET_TH_H, //0x38 263 E_DMD_DVBT_N_CFG_7M_ANM1_DET_TH_L, 264 E_DMD_DVBT_N_CFG_7M_ANM1_DET_TH_H, 265 E_DMD_DVBT_N_CFG_7M_ANP1_DET_TH_L, 266 E_DMD_DVBT_N_CFG_7M_ANP1_DET_TH_H, 267 268 E_DMD_DVBT_N_CFO10K_L, 269 E_DMD_DVBT_N_CFO10K_H, 270 E_DMD_DVBT_N_SNR100_L, //0x3F 271 E_DMD_DVBT_N_SNR100_H, //0x40 272 273 E_DMD_DVBT_N_AGC_LOCK_TH, 274 E_DMD_DVBT_N_AGC_LOCK_NUM, 275 E_DMD_DVBT_N_ADC_PGA_GAIN_I, 276 E_DMD_DVBT_N_ADC_PGA_GAIN_Q, 277 E_DMD_DVBT_N_PWDN_ADCI, 278 E_DMD_DVBT_N_PWDN_ADCQ, 279 E_DMD_DVBT_N_MPLL_ADC_DIV_SEL, 280 E_DMD_DVBT_N_DCR_LOCK, //0x48 281 E_DMD_DVBT_N_MIXER_IQ_SWAP_MODE, 282 E_DMD_DVBT_N_CCI_BYPASS, 283 E_DMD_DVBT_N_CCI_LOCK_DET, 284 E_DMD_DVBT_N_CCI_FSWEEP_L, 285 E_DMD_DVBT_N_CCI_FSWEEP_H, 286 E_DMD_DVBT_N_CCI_KPKI, 287 E_DMD_DVBT_N_INTP_RATEM1_0, //0x4F 288 289 E_DMD_DVBT_N_INTP_RATEM1_1, //0x50 290 E_DMD_DVBT_N_INTP_RATEM1_2, 291 E_DMD_DVBT_N_INTP_RATEM1_3, 292 E_DMD_DVBT_N_8K_MC_MODE, 293 E_DMD_DVBT_N_8K_MC_CP, 294 E_DMD_DVBT_N_8K_MC_CPOBS_NUM, 295 E_DMD_DVBT_N_8K_MODECP_DET, 296 E_DMD_DVBT_N_2K_MC_MODE, 297 E_DMD_DVBT_N_2K_MC_CP, //0x58 298 E_DMD_DVBT_N_2K_MC_CPOBS_NUM, 299 E_DMD_DVBT_N_2K_MODECP_DET, 300 E_DMD_DVBT_N_ICFO_SCAN_WINDOW_L, 301 E_DMD_DVBT_N_ICFO_SCAN_WINDOW_H, 302 E_DMD_DVBT_N_ICFO_MAX_OFFSET_L, 303 E_DMD_DVBT_N_ICFO_MAX_OFFSET_H, 304 E_DMD_DVBT_N_ICFO_DONE, //0x5F 305 306 E_DMD_DVBT_N_TPS_SYNC_LOCK, //0x60 307 E_DMD_DVBT_N_CONSTELLATION, 308 E_DMD_DVBT_N_HIERARCHY, 309 E_DMD_DVBT_N_HP_CODE_RATE, 310 E_DMD_DVBT_N_LP_CODE_RATE, 311 E_DMD_DVBT_N_GUARD_INTERVAL, 312 E_DMD_DVBT_N_TRANSMISSION_MODE, 313 E_DMD_DVBT_N_OFDM_SYMBOL_NUMBER, 314 E_DMD_DVBT_N_LENGTH_INDICATOR, //0x68 315 E_DMD_DVBT_N_FRAME_NUMBER, 316 E_DMD_DVBT_N_CELL_IDENTIFIER, 317 E_DMD_DVBT_N_DVBH_SIGNALLING, 318 E_DMD_DVBT_N_SNR_2K_ALPHA, 319 E_DMD_DVBT_N_SNR_8K_ALPHA, 320 E_DMD_DVBT_N_TS_EN, 321 E_DMD_DVBT_N_2K_DAGC1_REF, //0x6F 322 323 E_DMD_DVBT_N_8K_DAGC1_REF, //0x70 324 E_DMD_DVBT_N_2K_8K_DAGC2_REF, 325 E_DMD_DVBT_N_IF_INV_PWM_OUT_EN, 326 E_DMD_DVBT_N_RESERVE_0, 327 E_DMD_DVBT_N_RESERVE_1, 328 E_DMD_DVBT_N_RESERVE_2, 329 E_DMD_DVBT_N_RESERVE_3, 330 E_DMD_DVBT_N_RESERVE_4, 331 E_DMD_DVBT_N_RESERVE_5, //0x78 332 E_DMD_DVBT_N_RESERVE_6, 333 E_DMD_DVBT_N_RESERVE_7, 334 E_DMD_DVBT_N_RESERVE_8, 335 E_DMD_DVBT_N_RESERVE_9, 336 E_DMD_DVBT_N_RESERVE_10, 337 E_DMD_DVBT_N_RESERVE_11, //0x7E 338 }DVBT_N_Param; 339 340 typedef enum 341 { 342 //Parameter version 343 E_DMD_DVBT_PARAM_VERSION = 0x00,// 0x00 344 //System 345 E_DMD_DVBT_OP_AUTO_SCAN_MODE_EN,// 346 E_DMD_DVBT_CFG_FREQ,// 347 E_DMD_DVBT_CFG_BW,// 348 E_DMD_DVBT_CFG_MODE,// 349 E_DMD_DVBT_CFG_CP,// 350 E_DMD_DVBT_CFG_LP_SEL,// 351 E_DMD_DVBT_CFG_CSTL,// 352 E_DMD_DVBT_CFG_HIER, //0x08 353 E_DMD_DVBT_CFG_HPCR,// 354 E_DMD_DVBT_CFG_LPCR,// 355 356 //AGC 357 E_DMD_DVBT_OP_RFAGC_EN,// 358 E_DMD_DVBT_OP_HUMDET_EN,// 359 E_DMD_DVBT_OP_AUTO_RF_MAX_EN,// 360 E_DMD_DVBT_CFG_RFMAX,// 361 E_DMD_DVBT_CFG_ZIF,// 362 E_DMD_DVBT_CFG_RSSI, //0x10 363 E_DMD_DVBT_CFG_RFAGC_REF,// 364 E_DMD_DVBT_AGC_K,// 365 E_DMD_DVBT_CFG_IFAGC_REF_2K,// 366 E_DMD_DVBT_CFG_IFAGC_REF_8K,// 367 E_DMD_DVBT_CFG_IFAGC_REF_ACI,// 368 E_DMD_DVBT_CFG_IFAGC_REF_IIS,// 369 E_DMD_DVBT_AGC_REF, 370 E_DMD_DVBT_AGC_LOCK_TH, //0x18 371 E_DMD_DVBT_AGC_LOCK_NUM, // 372 E_DMD_DVBT_AGC_GAIN_LOCK,// 373 374 //ADC 375 E_DMD_DVBT_PWDN_ADCI,// 376 E_DMD_DVBT_PWDN_ADCQ,// 377 E_DMD_DVBT_MPLL_ADC_DIV_SEL,// 378 379 //DCR 380 E_DMD_DVBT_OP_DCR_EN,// 381 E_DMD_DVBT_DCR_LOCK,// 382 E_DMD_DVBT_DCR_LEAKY_I_FF_0,//0x20 383 E_DMD_DVBT_DCR_LEAKY_I_FF_1,//0x20 384 E_DMD_DVBT_DCR_LEAKY_I_FF_2,//0x20 385 E_DMD_DVBT_DCR_LEAKY_Q_FF_0, // 386 E_DMD_DVBT_DCR_LEAKY_Q_FF_1, // 387 E_DMD_DVBT_DCR_LEAKY_Q_FF_2, // 388 389 //IIS 390 E_DMD_DVBT_OP_IIS_EN,// 391 392 //Mixer 393 E_DMD_DVBT_CFG_FC_L,// 394 E_DMD_DVBT_CFG_FC_H,// 395 E_DMD_DVBT_CFG_FS_L,// 396 E_DMD_DVBT_CFG_FS_H,// 397 E_DMD_DVBT_MIXER_IQ_SWAP_MODE,// 398 E_DMD_DVBT_MIXER_IQ_SWAP_OUT_0,//0x28 399 E_DMD_DVBT_MIXER_IQ_SWAP_OUT_1, 400 E_DMD_DVBT_MIXER_IQ_SWAP_OUT_2, 401 E_DMD_DVBT_MIXER_IQ_SWAP_OUT_3, 402 E_DMD_DVBT_MIXER_IQ_DBG_SEL,// 403 404 //IQ Swap 405 E_DMD_DVBT_OP_IQB_EN,// 406 E_DMD_DVBT_OP_AUTO_IQ_SWAP_EN,// 407 E_DMD_DVBT_CFG_IQ_SWAP,// 408 E_DMD_DVBT_IQB_PHASE_COARSE_0,// 409 E_DMD_DVBT_IQB_PHASE_COARSE_1,// 410 E_DMD_DVBT_IQB_GAIN_COARSE_0,// 411 E_DMD_DVBT_IQB_GAIN_COARSE_1,// 412 413 //ACI 414 E_DMD_DVBT_OP_ACI_EN,//0x30 415 E_DMD_DVBT_OP_AUTO_ACI_EN, // 416 E_DMD_DVBT_CFG_ACI_DET_TH_L,// 417 E_DMD_DVBT_CFG_ACI_DET_TH_H,// 418 419 //CCI 420 E_DMD_DVBT_OP_CCI_EN,// 421 E_DMD_DVBT_CFG_CCI,// 422 E_DMD_DVBT_CCI_BYPASS,// 423 E_DMD_DVBT_CCI_TRACK_SW_RST,// 424 E_DMD_DVBT_CCI_LOCK_DET,//0x38 425 E_DMD_DVBT_CCI_FREQN_OUT_0, // 426 E_DMD_DVBT_CCI_FREQN_OUT_1, // 427 428 //Interpolator 429 E_DMD_DVBT_CFG_2K_SFO_DELAY_TIME_H,// 430 E_DMD_DVBT_CFG_2K_SFO_DELAY_TIME_L,// 431 E_DMD_DVBT_CFG_8K_SFO_DELAY_TIME_H,// 432 E_DMD_DVBT_CFG_8K_SFO_DELAY_TIME_L,// 433 E_DMD_DVBT_INTP_RATEM1_0,// 434 E_DMD_DVBT_INTP_RATEM1_1,// 435 E_DMD_DVBT_INTP_RATEM1_2,// 436 E_DMD_DVBT_INTP_RATEM1_3,// 437 438 //ModeCP 439 E_DMD_DVBT_OP_FIX_MODE_CP_EN,// 440 E_DMD_DVBT_8K_MC_MODE,// 441 E_DMD_DVBT_8K_MC_CP,// 442 E_DMD_DVBT_8K_MC_CPOBS_NUM,// 443 E_DMD_DVBT_8K_MODECP_DET, // 444 E_DMD_DVBT_2K_MC_MODE, // 445 E_DMD_DVBT_2K_MC_CP, // 446 E_DMD_DVBT_2K_MC_CPOBS_NUM, // 447 E_DMD_DVBT_2K_MODECP_DET, // 448 449 //ICFO 450 E_DMD_DVBT_CFG_ICFO_RANGE,// 451 //E_DMD_DVBT_ICFO_RANGE,//0x40 452 E_DMD_DVBT_ICFO_SCAN_WINDOW_0, // 453 E_DMD_DVBT_ICFO_SCAN_WINDOW_1, // 454 E_DMD_DVBT_ICFO_MAX_OFFSET_0,// 455 E_DMD_DVBT_ICFO_MAX_OFFSET_1,// 456 E_DMD_DVBT_ICFO_DONE,// 457 458 //TPS 459 E_DMD_DVBT_OP_FIX_TPS_EN,// 460 E_DMD_DVBT_TPS_SYNC_LOCK,// 461 E_DMD_DVBT_CONSTELLATION,// 462 E_DMD_DVBT_HIERARCHY,// 463 E_DMD_DVBT_HP_CODE_RATE,//0x48 464 E_DMD_DVBT_LP_CODE_RATE, // 465 E_DMD_DVBT_GUARD_INTERVAL,// 466 E_DMD_DVBT_TRANSMISSION_MODE,// 467 E_DMD_DVBT_OFDM_SYMBOL_NUMBER,// 468 E_DMD_DVBT_LENGTH_INDICATOR,// 469 E_DMD_DVBT_FRAME_NUMBER,// 470 E_DMD_DVBT_CELL_IDENTIFIER,// 471 E_DMD_DVBT_DVBH_SIGNALLING,//0x50 472 473 //SNR 474 E_DMD_DVBT_SNR_ACCU_0, // 475 E_DMD_DVBT_SNR_ACCU_1, // 476 E_DMD_DVBT_SNR_ACCU_2, // 477 E_DMD_DVBT_SNR_ACCU_3, // 478 E_DMD_DVBT_BIT_ERR_NUM_7_0,// 479 E_DMD_DVBT_BIT_ERR_NUM_15_8,// 480 E_DMD_DVBT_BIT_ERR_NUM_23_16,// 481 E_DMD_DVBT_BIT_ERR_NUM_31_24,// 482 E_DMD_DVBT_UNCRT_PKT_NUM_7_0,// 483 E_DMD_DVBT_UNCRT_PKT_NUM_15_8,// 484 485 //TS 486 E_DMD_DVBT_CFG_TS_SERIAL,//0x58 487 E_DMD_DVBT_CFG_TS_CLK_RATE,// 488 E_DMD_DVBT_CFG_TS_CLK_INV,// 489 E_DMD_DVBT_CFG_TS_DATA_SWAP,// 490 E_DMD_DVBT_TS_EN,// 491 E_DMD_DVBT_TS_SOURCE_SEL,// 492 E_DMD_DVBT_DVBTM_TS_CLK_POL,// 493 E_DMD_DVBT_DVBTM_TS_CLK_DIVNUM,//0x60 494 E_DMD_DVBT_EN_TS_PAD, // 495 E_DMD_DVBT_IF_INV_PWM_OUT_EN, 496 497 //Reserve 498 E_DMD_DVBT_RESERVE_1, 499 E_DMD_DVBT_RESERVE_2, 500 E_DMD_DVBT_RESERVE_3, 501 E_DMD_DVBT_RESERVE_4, 502 503 //Debug 504 E_DMD_DVBT_CHECKSUM,//0x62 505 } DVBT_Param; 506 507 /// For demod init 508 typedef void (*fpIntCallBack)(MS_U8 u8arg); 509 typedef struct 510 { 511 // tuner parameter 512 MS_U8 u8SarChannel; 513 DMD_RFAGC_SSI *pTuner_RfagcSsi; 514 MS_U16 u16Tuner_RfagcSsi_Size; 515 DMD_IFAGC_SSI *pTuner_IfagcSsi_LoRef; 516 MS_U16 u16Tuner_IfagcSsi_LoRef_Size; 517 DMD_IFAGC_SSI *pTuner_IfagcSsi_HiRef; 518 MS_U16 u16Tuner_IfagcSsi_HiRef_Size; 519 DMD_IFAGC_ERR *pTuner_IfagcErr_LoRef; 520 MS_U16 u16Tuner_IfagcErr_LoRef_Size; 521 DMD_IFAGC_ERR *pTuner_IfagcErr_HiRef; 522 MS_U16 u16Tuner_IfagcErr_HiRef_Size; 523 DMD_SQI_CN_NORDIGP1 *pSqiCnNordigP1; 524 MS_U16 u16SqiCnNordigP1_Size; 525 526 // register init 527 MS_U8 *u8DMD_DVBT_DSPRegInitExt; // TODO use system variable type 528 MS_U8 u8DMD_DVBT_DSPRegInitSize; 529 MS_U8 *u8DMD_DVBT_InitExt; // TODO use system variable type 530 } DMD_DVBT_InitData; 531 532 typedef enum 533 { 534 E_DMD_DVBT_FAIL=0, 535 E_DMD_DVBT_OK=1 536 } DMD_DVBT_Result; 537 538 539 typedef enum 540 { 541 E_DMD_DVBT_MODULATION_INFO, 542 E_DMD_DVBT_DEMOD_INFO, 543 E_DMD_DVBT_LOCK_INFO, 544 E_DMD_DVBT_PRESFO_INFO, 545 E_DMD_DVBT_LOCK_TIME_INFO, 546 E_DMD_DVBT_BER_INFO, 547 E_DMD_DVBT_AGC_INFO, 548 } DMD_DVBT_INFO_TYPE; 549 550 typedef struct 551 { 552 MS_U16 u16Version; 553 MS_U8 u16DemodState; // 554 float SfoValue; // 555 float TotalCfo; // 556 MS_U16 u16ChannelLength; // 557 MS_U8 u8Fft; // 558 MS_U8 u8Constel; // 559 MS_U8 u8Gi; // 560 MS_U8 u8HpCr; // 561 MS_U8 u8LpCr; // 562 MS_U8 u8Hiearchy; // 563 MS_U8 u8Fd; // 564 MS_U8 u8ChLen; // 565 MS_U8 u8SnrSel; // 566 MS_U8 u8PertoneNum; // 567 MS_U8 u8DigAci; // 568 MS_U8 u8FlagCi; // 569 MS_U8 u8TdCoef; // 570 } DMD_DVBT_Info; 571 572 //typedef void(*P_DMD_ISR_Proc)(MS_U8 u8DMDID); 573 574 575 //------------------------------------------------------------------------------------------------- 576 // Function and Variable 577 //------------------------------------------------------------------------------------------------- 578 //////////////////////////////////////////////////////////////////////////////// 579 /// MDrv_DMD_DVBT_Init 580 //////////////////////////////////////////////////////////////////////////////// 581 extern MS_BOOL MDrv_DMD_DVBT_Init(DMD_DVBT_InitData *pDMD_DVBT_InitData, MS_U32 u32InitDataLen); 582 //////////////////////////////////////////////////////////////////////////////// 583 /// Should be called when exit VD input source 584 //////////////////////////////////////////////////////////////////////////////// 585 extern MS_BOOL MDrv_DMD_DVBT_Exit(void); 586 //////////////////////////////////////////////////////////////////////////////// 587 /// Get Initial Data 588 /// @ingroup DVBT_BASIC 589 /// @param pDMD_DVBT_InitData \b IN: DVBT initial parameters 590 /// @return TRUE : succeed 591 /// @return FALSE : fail 592 //------------------------------------------------------------------------------------------------- 593 extern MS_U32 SYMBOL_WEAK MDrv_DMD_DVBT_GetConfig(DMD_DVBT_InitData *pDMD_DVBT_InitData); 594 //////////////////////////////////////////////////////////////////////////////// 595 //------------------------------------------------------------------------------ 596 /// Set detailed level of DVBT driver debug message 597 /// u8DbgLevel : debug level for Parallel Flash driver\n 598 /// AVD_DBGLV_NONE, ///< disable all the debug message\n 599 /// AVD_DBGLV_INFO, ///< information\n 600 /// AVD_DBGLV_NOTICE, ///< normal but significant condition\n 601 /// AVD_DBGLV_WARNING, ///< warning conditions\n 602 /// AVD_DBGLV_ERR, ///< error conditions\n 603 /// AVD_DBGLV_CRIT, ///< critical conditions\n 604 /// AVD_DBGLV_ALERT, ///< action must be taken immediately\n 605 /// AVD_DBGLV_EMERG, ///< system is unusable\n 606 /// AVD_DBGLV_DEBUG, ///< debug-level messages\n 607 /// @return TRUE : succeed 608 /// @return FALSE : failed to set the debug level 609 //------------------------------------------------------------------------------ 610 extern MS_BOOL MDrv_DMD_DVBT_SetDbgLevel(DMD_DbgLv u8DbgLevel); 611 //------------------------------------------------------------------------------------------------- 612 /// Get the information of DVBT driver\n 613 /// @return the pointer to the driver information 614 //------------------------------------------------------------------------------------------------- 615 extern DMD_DVBT_Info* MDrv_DMD_DVBT_GetInfo(DMD_DVBT_INFO_TYPE eInfoType); 616 //------------------------------------------------------------------------------------------------- 617 /// Get DVBT driver version 618 /// when get ok, return the pointer to the driver version 619 //------------------------------------------------------------------------------------------------- 620 extern MS_BOOL MDrv_DMD_DVBT_GetLibVer(const MSIF_Version **ppVersion); 621 //////////////////////////////////////////////////////////////////////////////// 622 /// To get DVBT's register value, only for special purpose.\n 623 /// u16Addr : the address of DVBT's register\n 624 /// return the value of AFEC's register\n 625 //////////////////////////////////////////////////////////////////////////////// 626 extern MS_BOOL MDrv_DMD_DVBT_GetReg(MS_U16 u16Addr, MS_U8 *pu8Data); 627 //////////////////////////////////////////////////////////////////////////////// 628 /// To set DVBT's register value, only for special purpose.\n 629 /// u16Addr : the address of DVBT's register\n 630 /// u8Value : the value to be set\n 631 //////////////////////////////////////////////////////////////////////////////// 632 extern MS_BOOL MDrv_DMD_DVBTGetFWVer(MS_U16 *ver); 633 //////////////////////////////////////////////////////////////////////////////// 634 /// Get DVBT FW version 635 /// u16Addr : the address of DVBT's register\n 636 //////////////////////////////////////////////////////////////////////////////// 637 extern MS_BOOL MDrv_DMD_DVBT_SetReg(MS_U16 u16Addr, MS_U8 u8Data); 638 //////////////////////////////////////////////////////////////////////////////// 639 /// MDrv_DMD_DVBT_SetSerialControl 640 //////////////////////////////////////////////////////////////////////////////// 641 extern MS_BOOL MDrv_DMD_DVBT_SetSerialControl(MS_BOOL bEnable); 642 //////////////////////////////////////////////////////////////////////////////// 643 /// MDrv_DMD_DVBT_SetConfig 644 //////////////////////////////////////////////////////////////////////////////// 645 extern MS_BOOL MDrv_DMD_DVBT_SetConfig(DMD_RF_CHANNEL_BANDWIDTH BW, MS_BOOL bSerialTS, MS_BOOL bPalBG); 646 //////////////////////////////////////////////////////////////////////////////// 647 /// MDrv_DMD_DVBT_SetConfigHPLP 648 //////////////////////////////////////////////////////////////////////////////// 649 extern MS_BOOL MDrv_DMD_DVBT_SetConfigHPLP(DMD_RF_CHANNEL_BANDWIDTH BW, MS_BOOL bSerialTS, MS_BOOL bPalBG, MS_BOOL bLPSel); 650 //////////////////////////////////////////////////////////////////////////////// 651 /// MDrv_DMD_DVBT_SetConfigHPLPSetIF 652 //////////////////////////////////////////////////////////////////////////////// 653 extern MS_BOOL MDrv_DMD_DVBT_SetConfigHPLPSetIF(DMD_RF_CHANNEL_BANDWIDTH BW, MS_BOOL bSerialTS, MS_BOOL bPalBG, MS_BOOL bLPSel, MS_U32 u32IFFreq, MS_U32 u32FSFreq, MS_U8 u8IQSwap); 654 /////////////////////////////////////////////////////////////////////////////// 655 /// MDrv_DMD_DVBT_SetActive 656 //////////////////////////////////////////////////////////////////////////////// 657 extern MS_BOOL MDrv_DMD_DVBT_SetActive(MS_BOOL bEnable); 658 //////////////////////////////////////////////////////////////////////////////// 659 /// MDrv_DMD_DVBT_Get_Lock 660 //////////////////////////////////////////////////////////////////////////////// 661 extern MS_BOOL MDrv_DMD_DVBT_GetLock(DMD_DVBT_GETLOCK_TYPE eType, DMD_LOCK_STATUS *eLockStatus); 662 //////////////////////////////////////////////////////////////////////////////// 663 /// MDrv_DMD_DVBT_GetSignalStrength 664 //////////////////////////////////////////////////////////////////////////////// 665 extern MS_BOOL MDrv_DMD_DVBT_GetSignalStrength(MS_U16 *u16Strength); 666 //////////////////////////////////////////////////////////////////////////////// 667 /// MDrv_DMD_DVBT_GetSignalStrengthWithRFPower 668 //////////////////////////////////////////////////////////////////////////////// 669 extern MS_BOOL MDrv_DMD_DVBT_GetSignalStrengthWithRFPower(MS_U16 *u16Strength, float fRFPowerDbm); 670 //////////////////////////////////////////////////////////////////////////////// 671 /// MDrv_DMD_DVBT_GetSignalQuality 672 //////////////////////////////////////////////////////////////////////////////// 673 extern MS_BOOL MDrv_DMD_DVBT_GetSignalQuality(MS_U16 *u16Quality); 674 //////////////////////////////////////////////////////////////////////////////// 675 /// MDrv_DMD_DVBT_GetSignalQualityWithRFPower 676 //////////////////////////////////////////////////////////////////////////////// 677 extern MS_BOOL MDrv_DMD_DVBT_GetSignalQualityWithRFPower(MS_U16 *u16Quality, float fRFPowerDbm); 678 //////////////////////////////////////////////////////////////////////////////// 679 /// MDrv_DMD_DVBT_GetSNR 680 //////////////////////////////////////////////////////////////////////////////// 681 extern MS_BOOL MDrv_DMD_DVBT_GetSNR(float *fSNR); 682 //////////////////////////////////////////////////////////////////////////////// 683 /// MDrv_DMD_DVBT_GetPostViterbiBer 684 //////////////////////////////////////////////////////////////////////////////// 685 extern MS_BOOL MDrv_DMD_DVBT_GetPostViterbiBer(float *ber); 686 //////////////////////////////////////////////////////////////////////////////// 687 /// MDrv_DMD_DVBT_GetPreViterbiBer 688 //////////////////////////////////////////////////////////////////////////////// 689 extern MS_BOOL MDrv_DMD_DVBT_GetPreViterbiBer(float *ber); 690 //////////////////////////////////////////////////////////////////////////////// 691 /// MDrv_DMD_DVBT_GetPacketErr 692 //////////////////////////////////////////////////////////////////////////////// 693 extern MS_BOOL MDrv_DMD_DVBT_GetPacketErr(MS_U16 *pktErr); 694 //////////////////////////////////////////////////////////////////////////////// 695 /// MDrv_DMD_DVBT_GetTPSInfo 696 //////////////////////////////////////////////////////////////////////////////// 697 extern MS_BOOL MDrv_DMD_DVBT_GetTPSInfo(MS_U16 *u16Info); 698 //////////////////////////////////////////////////////////////////////////////// 699 /// MDrv_DMD_DVBT_GetCellID 700 //////////////////////////////////////////////////////////////////////////////// 701 extern MS_BOOL MDrv_DMD_DVBT_GetCellID(MS_U16 *u16CellID); 702 //////////////////////////////////////////////////////////////////////////////// 703 /// MDrv_DMD_DVBT_GetFreqOffset 704 //////////////////////////////////////////////////////////////////////////////// 705 extern MS_BOOL MDrv_DMD_DVBT_GetFreqOffset(float *pFreqOff); 706 //////////////////////////////////////////////////////////////////////////////// 707 /// MDrv_DMD_DVBT_NORDIG_SSI_Table_Write 708 //////////////////////////////////////////////////////////////////////////////// 709 extern MS_BOOL MDrv_DMD_DVBT_NORDIG_SSI_Table_Write(DMD_CONSTEL constel, DMD_CODERATE code_rate, float write_value); 710 //////////////////////////////////////////////////////////////////////////////// 711 /// MDrv_DMD_DVBT_NORDIG_SSI_Table_Read 712 //////////////////////////////////////////////////////////////////////////////// 713 extern MS_BOOL MDrv_DMD_DVBT_NORDIG_SSI_Table_Read(DMD_CONSTEL constel, DMD_CODERATE code_rate, float *read_value); 714 715 extern MS_U32 MDrv_DMD_DVBT_SetPowerState(EN_POWER_MODE u16PowerState); 716 717 #ifdef UFO_DEMOD_DVBT_SUPPORT_DMD_INT 718 MS_BOOL MDrv_DMD_DVBT_Reg_INT_CB(fpIntCallBack fpCBReg); 719 #endif 720 721 #ifdef __cplusplus 722 } 723 #endif 724 725 726 #endif // _DRV_DVBT_H_ 727 728