1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. 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If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 78 #ifndef _VDEC_EX_V2_H_ 79 #define _VDEC_EX_V2_H_ 80 81 #if (!defined(MSOS_TYPE_NUTTX) && !defined(MSOS_TYPE_OPTEE)) || defined(SUPPORT_X_MODEL_FEATURE) 82 #ifdef __cplusplus 83 extern "C" 84 { 85 #endif 86 87 #include "MsTypes.h" 88 //------------------------------------------------------------------------------------------------- 89 // Define for Upper layer 90 //------------------------------------------------------------------------------------------------- 91 //------------------------------------------------------------------------------------------------- 92 // Macro and Define 93 //------------------------------------------------------------------------------------------------- 94 #define MSIF_VDEC_EX_V2_LIB_CODE {'V','E','X','2'} 95 #define MSIF_VDEC_EX_V2_LIBVER {'0','5'} 96 #define MSIF_VDEC_EX_V2_BUILDNUM {'0','3'} 97 #define MSIF_VDEC_EX_V2_CHANGELIST {'0','0','6','9','3','0','7','7'} 98 99 /// Version string. 100 #define VDEC_EX_V2_API_VERSION /* Character String for DRV/API version */ \ 101 MSIF_TAG, /* 'MSIF' */ \ 102 MSIF_CLASS, /* '00' */ \ 103 MSIF_CUS, /* 0x0000 */ \ 104 MSIF_MOD, /* 0x0000 */ \ 105 MSIF_CHIP, \ 106 MSIF_CPU, \ 107 MSIF_VDEC_EX_V2_LIB_CODE, /* IP__ */ \ 108 MSIF_VDEC_EX_V2_LIBVER, /* 0.0 ~ Z.Z */ \ 109 MSIF_VDEC_EX_V2_BUILDNUM, /* 00 ~ 99 */ \ 110 MSIF_VDEC_EX_V2_CHANGELIST, /* CL# */ \ 111 MSIF_OS 112 113 #define VDEC_EX_V2_DEFAULT_DBG_MSG_LEVEL E_VDEC_EX_DBG_LEVEL_DBG 114 #define VDEC_EX_V2_RVD_BROKEN_BY_US 0x80000000 115 #define VDEC_EX_V2_MVD_PIC_START_FLAG 0x40000000 116 117 #define VDEC_EX_V2_BIT(_bit_) (1 << (_bit_)) 118 119 #define VDEC_EX_V2_FPA_TYPE_CHECKERBOARD_INTERLEAVING 0 120 #define VDEC_EX_V2_FPA_TYPE_COLUMN_INTERLEAVEING 1 121 #define VDEC_EX_V2_FPA_TYPE_ROW_INTERLEAVEING 2 122 #define VDEC_EX_V2_FPA_TYPE_SIDE_BY_SIDE_PACKING 3 123 #define VDEC_EX_V2_FPA_TYPE_TOP_BOTTOM_PACKING 4 124 #define VDEC_EX_V2_FPA_TYPE_TEMPORAL_INTERLEAVING_FRM 5 125 #define VDEC_EX_V2_MAX_DEC_NUM 2 126 127 #define VDEC_CAP_DYNAMIC_CMA 128 #define VDEC_CAP_DISABLE_HEVC_10BITS // MApi_VDEC_EX_PreSetControl((VDEC_StreamId *)pHandle, E_VDEC_EX_USER_CMD_VDEC_FEATURE, E_VDEC_EX_FEATURE_FORCE_MAIN_PROFILE); 129 130 #ifndef VDEC_CAP_SYSTEM_PREGET_FB_MEM_USAGE_SIZE 131 #define VDEC_CAP_SYSTEM_PREGET_FB_MEM_USAGE_SIZE 132 #endif 133 //------------------------------------------------------------------------------------------------- 134 // Type and Structure 135 //------------------------------------------------------------------------------------------------- 136 137 //------------------------------------------------------------------------------------------------- 138 // Enum for Upper layer 139 //------------------------------------------------------------------------------------------------- 140 typedef enum 141 { 142 E_VDEC_EX_V2_MAIN_STREAM = 0, 143 E_VDEC_EX_V2_SUB_STREAM, 144 } VDEC_EX_V2_Stream; 145 146 /// decoder event enumerator. 147 typedef enum 148 { 149 /// turn off all event 150 E_VDEC_E_V2_EVENT_OFF = 0x00, 151 /// display one frame/field 152 E_VDEC_EX_V2_EVENT_DISP_ONE = VDEC_EX_V2_BIT(0), 153 /// repeat one frame/field 154 E_VDEC_EX_V2_EVENT_DISP_REPEAT = VDEC_EX_V2_BIT(1), 155 /// one CC data should be displayed 156 E_VDEC_EX_V2_EVENT_DISP_WITH_CC = VDEC_EX_V2_BIT(2), 157 /// decode one frame 158 E_VDEC_EX_V2_EVENT_DEC_ONE = VDEC_EX_V2_BIT(3), 159 /// decode one I frame 160 E_VDEC_EX_V2_EVENT_DEC_I = VDEC_EX_V2_BIT(4), 161 /// decode error 162 E_VDEC_EX_V2_EVENT_DEC_ERR = VDEC_EX_V2_BIT(5), 163 /// display information is changed 164 E_VDEC_EX_V2_EVENT_DISP_INFO_CHG = VDEC_EX_V2_BIT(6), 165 /// find user data 166 E_VDEC_EX_V2_EVENT_USER_DATA_FOUND = VDEC_EX_V2_BIT(7), 167 /// display information ready after be changed 168 E_VDEC_EX_V2_EVENT_DISP_INFO_RDY = VDEC_EX_V2_BIT(8), 169 /// first frame decoded 170 E_VDEC_EX_V2_EVENT_FIRST_FRAME = VDEC_EX_V2_BIT(9), 171 /// first picture found 172 E_VDEC_EX_V2_EVENT_PIC_FOUND = VDEC_EX_V2_BIT(10), 173 /// video is ready to display (no garbage and avsync done) 174 E_VDEC_EX_V2_EVENT_VIDEO_UNMUTE = VDEC_EX_V2_BIT(11), 175 /// new sequence header found 176 E_VDEC_EX_V2_EVENT_SEQ_HDR_FOUND = VDEC_EX_V2_BIT(12), 177 /// active format description found 178 E_VDEC_EX_V2_EVENT_AFD_FOUND = VDEC_EX_V2_BIT(13), 179 // ES data invalid 180 E_VDEC_EX_V2_EVENT_ES_DATA_ERR = VDEC_EX_V2_BIT(14), 181 182 } VDEC_EX_V2_EventFlag; 183 184 //define VDEC CB type 185 typedef enum 186 { 187 E_VDEC_EX_V2_CB_MAIN = 0, 188 E_VDEC_EX_V2_CB_SUB, 189 } VDEC_EX_V2_CB_TYPE; 190 191 /// codec type enumerator 192 typedef enum 193 { 194 ///unsupported codec type 195 E_VDEC_EX_V2_CODEC_TYPE_NONE = 0, 196 ///MPEG 1/2 197 E_VDEC_EX_V2_CODEC_TYPE_MPEG2, 198 ///H263 (short video header) 199 E_VDEC_EX_V2_CODEC_TYPE_H263, 200 ///MPEG4 (default) 201 E_VDEC_EX_V2_CODEC_TYPE_MPEG4, 202 ///MPEG4 (Divx311) 203 E_VDEC_EX_V2_CODEC_TYPE_DIVX311, 204 ///MPEG4 (Divx412) 205 E_VDEC_EX_V2_CODEC_TYPE_DIVX412, 206 ///FLV 207 E_VDEC_EX_V2_CODEC_TYPE_FLV, 208 ///VC1 advanced profile (VC1) 209 E_VDEC_EX_V2_CODEC_TYPE_VC1_ADV, 210 ///VC1 main profile (RCV) 211 E_VDEC_EX_V2_CODEC_TYPE_VC1_MAIN, 212 ///Real Video version 8 213 E_VDEC_EX_V2_CODEC_TYPE_RV8, 214 ///Real Video version 9 and 10 215 E_VDEC_EX_V2_CODEC_TYPE_RV9, 216 ///H264 217 E_VDEC_EX_V2_CODEC_TYPE_H264, 218 ///AVS 219 E_VDEC_EX_V2_CODEC_TYPE_AVS, 220 ///MJPEG 221 E_VDEC_EX_V2_CODEC_TYPE_MJPEG, 222 ///MVC 223 E_VDEC_EX_V2_CODEC_TYPE_MVC, 224 ///VP8 225 E_VDEC_EX_V2_CODEC_TYPE_VP8, 226 E_VDEC_EX_V2_CODEC_TYPE_NUM 227 } VDEC_EX_V2_CodecType; 228 229 /// input source select enumerator 230 typedef enum 231 { 232 ///DTV mode 233 E_VDEC_EX_V2_SRC_MODE_DTV = 0, 234 ///TS file mode 235 E_VDEC_EX_V2_SRC_MODE_TS_FILE, 236 ///generic file mode 237 E_VDEC_EX_V2_SRC_MODE_FILE, 238 /// TS file and dual ES buffer mode 239 E_VDEC_EX_V2_SRC_MODE_TS_FILE_DUAL_ES, 240 ///generic file and dual ES buffer mode 241 E_VDEC_EX_V2_SRC_MODE_FILE_DUAL_ES, 242 } VDEC_EX_V2_SrcMode; 243 244 /// function return enumerator 245 typedef enum 246 { 247 ///failed 248 E_VDEC_EX_V2_FAIL = 0, 249 ///success 250 E_VDEC_EX_V2_OK, 251 ///invalid parameter 252 E_VDEC_EX_V2_RET_INVALID_PARAM, 253 ///access not allow 254 E_VDEC_EX_V2_RET_ILLEGAL_ACCESS, 255 ///hardware abnormal 256 E_VDEC_EX_V2_RET_HARDWARE_BREAKDOWN, 257 ///unsupported 258 E_VDEC_EX_V2_RET_UNSUPPORTED, 259 ///timeout 260 E_VDEC_EX_V2_RET_TIMEOUT, 261 ///not ready 262 E_VDEC_EX_V2_RET_NOT_READY, 263 ///not initial 264 E_VDEC_EX_V2_RET_NOT_INIT, 265 ///not exit after last initialization 266 E_VDEC_EX_V2_RET_NOT_EXIT, 267 ///not running, counter does not change 268 E_VDEC_EX_V2_RET_NOT_RUNNING, 269 ///cma error 270 E_VDEC_EX_V2_RET_CMA_ERROR, 271 ///max value 272 E_VDEC_EX_V2_RET_NUM, 273 } VDEC_EX_V2_Result; 274 275 /// Action enumerator of display commands 276 typedef enum 277 { 278 /// Action- display frame 279 E_VDEC_EX_V2_DISP_ACTION_DISPLAY = 1, 280 /// Action - release frame 281 E_VDEC_EX_V2_DISP_ACTION_RELEASE, 282 } VDEC_EX_V2_DispCmdAction; 283 284 /// Freeze picture select after flush decoder 285 typedef enum 286 { 287 /// Freeze at current display picture 288 E_VDEC_EX_V2_FREEZE_AT_CUR_PIC = 1, 289 /// freeze at the latest decode picture 290 E_VDEC_EX_V2_FREEZE_AT_LAST_PIC, 291 } VDEC_EX_V2_FreezePicSelect; 292 293 /// error code enumerator 294 typedef enum 295 { 296 E_VDEC_EX_V2_ERR_CODE_BASE = 0x01000000, 297 E_VDEC_EX_V2_ERR_CODE_NOT_SUPPORT, 298 E_VDEC_EX_V2_ERR_CODE_ILLEGAL_ACCESS, 299 E_VDEC_EX_V2_ERR_CODE_FRMRATE_NOT_SUPPORT, 300 E_VDEC_EX_V2_ERR_CODE_DIVX_PLUS_UNSUPPORTED, 301 E_VDEC_EX_V2_ERR_CODE_EXCEED_HW_CAP, 302 303 E_VDEC_EX_V2_MVD_ERR_CODE_BASE = 0x02000000, 304 E_VDEC_EX_V2_MVD_ERR_CODE_SHAPE, 305 E_VDEC_EX_V2_MVD_ERR_CODE_USED_SPRITE, 306 E_VDEC_EX_V2_MVD_ERR_CODE_NOT_8_BIT, //error_status : bits per pixel 307 E_VDEC_EX_V2_MVD_ERR_CODE_NERPRED_ENABLE, 308 E_VDEC_EX_V2_MVD_ERR_CODE_REDUCED_RES_ENABLE, 309 E_VDEC_EX_V2_MVD_ERR_CODE_SCALABILITY, 310 E_VDEC_EX_V2_MVD_ERR_CODE_OTHER, 311 E_VDEC_EX_V2_MVD_ERR_CODE_H263_ERROR, 312 E_VDEC_EX_V2_MVD_ERR_CODE_RES_NOT_SUPPORT, //error_status : none 313 E_VDEC_EX_V2_MVD_ERR_CODE_MPEG4_NOT_SUPPORT, //error_status : none 314 E_VDEC_EX_V2_MVD_ERR_CODE_VC1_NOT_SUPPORT, //error_status : none 315 E_VDEC_EX_V2_MVD_ERR_CODE_RCV_ERROR_OCCUR, 316 317 E_VDEC_EX_V2_HVD_ERR_CODE_BASE = 0x03000000, 318 E_VDEC_EX_V2_HVD_ERR_CODE_GENERAL_BASE = (0x0000|E_VDEC_EX_HVD_ERR_CODE_BASE), 319 E_VDEC_EX_V2_HVD_ERR_CODE_OUT_OF_SPEC , 320 E_VDEC_EX_V2_HVD_ERR_CODE_UNKNOW_ERR, 321 E_VDEC_EX_V2_HVD_ERR_CODE_HW_BREAK_DOWN, 322 E_VDEC_EX_V2_HVD_ERR_CODE_HW_DEC_TIMEOUT, 323 E_VDEC_EX_V2_HVD_ERR_CODE_OUT_OF_MEMORY, 324 E_VDEC_EX_V2_HVD_ERR_CODE_UNKNOWN_CODEC, 325 // AVC 326 E_VDEC_EX_V2_HVD_ERR_CODE_AVC_BASE = (0x1000|E_VDEC_EX_HVD_ERR_CODE_BASE), 327 E_VDEC_EX_V2_HVD_ERR_CODE_AVC_SPS_BROKEN, 328 E_VDEC_EX_V2_HVD_ERR_CODE_AVC_SPS_NOT_IN_SPEC, 329 E_VDEC_EX_V2_HVD_ERR_CODE_AVC_SPS_NOT_ENOUGH_FRM, // DPB size at specified level is smaller than the specified number of reference frames. This is not allowed 330 E_VDEC_EX_V2_HVD_ERR_CODE_AVC_PPS_BROKEN, // PPS is not valid 331 E_VDEC_EX_V2_HVD_ERR_CODE_AVC_REF_LIST, 332 E_VDEC_EX_V2_HVD_ERR_CODE_AVC_NO_REF, 333 E_VDEC_EX_V2_HVD_ERR_CODE_AVC_RES, // out of supported resolution 334 // AVS 335 E_VDEC_EX_V2_HVD_ERR_CODE_AVS_BASE = (0x2000|E_VDEC_EX_HVD_ERR_CODE_BASE), 336 E_VDEC_EX_V2_HVD_ERR_CODE_AVS_RES, // out of supported resolution 337 // RM 338 E_VDEC_EX_V2_HVD_ERR_CODE_RM_BASE = (0x3000|E_VDEC_EX_HVD_ERR_CODE_BASE), 339 E_VDEC_EX_V2_HVD_ERR_CODE_RM_PACKET_HEADER, 340 E_VDEC_EX_V2_HVD_ERR_CODE_RM_FRAME_HEADER, 341 E_VDEC_EX_V2_HVD_ERR_CODE_RM_SLICE_HEADER, 342 E_VDEC_EX_V2_HVD_ERR_CODE_RM_BYTE_CNT, 343 E_VDEC_EX_V2_HVD_ERR_CODE_RM_DISP_TIMEOUT, 344 E_VDEC_EX_V2_HVD_ERR_CODE_RM_NO_REF, 345 E_VDEC_EX_V2_HVD_ERR_CODE_RM_RES, // out of supported resolution 346 E_VDEC_EX_V2_HVD_ERR_CODE_RM_VLC, 347 E_VDEC_EX_V2_HVD_ERR_CODE_RM_SIZE_OUT_FB_LAYOUT, 348 349 E_VDEC_EX_V2_RVD_ERR_CODE_BASE = 0x04000000, 350 E_VDEC_EX_V2_RVD_ERR_CODE_PACKET_HEADER, ///< packet header version error 351 E_VDEC_EX_V2_RVD_ERR_CODE_FRAME_HEADER, ///< frame type error 352 E_VDEC_EX_V2_RVD_ERR_CODE_SLICE_HEADER, ///<slice header error 353 E_VDEC_EX_V2_RVD_ERR_CODE_DECODE_TIMEOUT,///< decode MB timeout 354 E_VDEC_EX_V2_RVD_ERR_CODE_OUT_OF_MEMORY, ///< frame buffer is out of memory 355 E_VDEC_EX_V2_RVD_ERR_CODE_BYTE_POS, ///< can not find in ID table 356 E_VDEC_EX_V2_RVD_ERR_CODE_DISPLAY_TIMEOUT, 357 358 E_VDEC_EX_V2_MJPEG_ERR_CODE_BASE = 0x05000000, 359 E_VDEC_EX_V2_HVD_ERR_CODE_MJPEG_RES, 360 } VDEC_EX_V2_ErrCode; 361 362 /// frame rate conversion mode enumerator 363 typedef enum 364 { 365 /// disable FRC mode. 366 E_VDEC_EX_V2_FRC_NORMAL = 0, 367 /// output rate is twice of input rate (ex. 30p to 60p) 368 E_VDEC_EX_V2_FRC_DISP_TWICE, 369 /// 3:2 pulldown mode (ex. 24p to 60i or 60p) 370 E_VDEC_EX_V2_FRC_3_2_PULLDOWN, 371 /// PAL to NTSC conversion (50i to 60i) 372 E_VDEC_EX_V2_FRC_PAL_TO_NTSC, 373 /// NTSC to PAL conversion (60i to 50i) 374 E_VDEC_EX_V2_FRC_NTSC_TO_PAL, 375 /// output rate 50P ->60P 376 E_VDEC_EX_V2_FRC_MODE_50P_60P, 377 /// output rate 60P ->50P 378 E_VDEC_EX_V2_FRC_MODE_60P_50P, 379 } VDEC_EX_V2_FrcMode; 380 381 /// trick decode mode enumerator 382 typedef enum 383 { 384 /// decode all frame 385 E_VDEC_EX_V2_TRICK_DEC_ALL = 0, 386 /// decode all except of non-reference frame 387 E_VDEC_EX_V2_TRICK_DEC_IP, 388 /// only decode I frame 389 E_VDEC_EX_V2_TRICK_DEC_I, 390 E_VDEC_EX_V2_TRICK_DEC_NUM 391 } VDEC_EX_V2_TrickDec; 392 393 /// display speed setting enumerator 394 typedef enum 395 { 396 /// default speed type 397 E_VDEC_EX_V2_SPEED_DEFAULT = 0, 398 /// fast display 399 E_VDEC_EX_V2_SPEED_FAST, 400 /// slow display 401 E_VDEC_EX_V2_SPEED_SLOW, 402 } VDEC_EX_V2_SpeedType; 403 404 /// The display speed enumerator 405 typedef enum 406 { 407 /// Normal display speed. 408 E_VDEC_EX_V2_DISP_SPEED_1X = 1, 409 /// 2X 410 E_VDEC_EX_V2_DISP_SPEED_2X = 2, 411 /// 4X 412 E_VDEC_EX_V2_DISP_SPEED_4X = 4, 413 /// 8X 414 E_VDEC_EX_V2_DISP_SPEED_8X = 8, 415 /// 16X 416 E_VDEC_EX_V2_DISP_SPEED_16X = 16, 417 /// 32X 418 E_VDEC_EX_V2_DISP_SPEED_32X = 32, 419 } VDEC_EX_V2_DispSpeed; 420 421 /// motion JPEG down scale factor enumerator 422 typedef enum 423 { 424 ///original size 425 E_VDEC_EX_V2_MJPEG_SCALE_1to1 = 0, 426 ///down scale to 1/2 427 E_VDEC_EX_V2_MJPEG_SCALE_2to1, 428 ///down scale to 1/4 429 E_VDEC_EX_V2_MJPEG_SCALE_4to1, 430 ///down scale to 1/8 431 E_VDEC_EX_V2_MJPEG_SCALE_8to1, 432 } VDEC_EX_V2_MJpegScaleFactor; 433 434 /// timestamp type of command queue 435 typedef enum 436 { 437 ///without timestamp information 438 E_VDEC_EX_V2_TIME_STAMP_NONE = 0, 439 ///PTS (Presentation Time Stamp) 440 E_VDEC_EX_V2_TIME_STAMP_PTS, 441 ///DTS (Decode Time Stamp) 442 E_VDEC_EX_V2_TIME_STAMP_DTS, 443 ///STS (Sorted Time Stamp) 444 E_VDEC_EX_V2_TIME_STAMP_STS, 445 } VDEC_EX_V2_TimeStampType; 446 447 /// The debug level of VDEC 448 typedef enum 449 { 450 /// disable all uart message. 451 E_VDEC_EX_V2_DBG_LEVEL_NONE = 0, 452 /// Only output error message 453 E_VDEC_EX_V2_DBG_LEVEL_ERR, 454 /// output general message, and above. 455 E_VDEC_EX_V2_DBG_LEVEL_INFO, 456 /// output debug message, and above. 457 E_VDEC_EX_V2_DBG_LEVEL_DBG, 458 /// output function tracing message, and above. 459 E_VDEC_EX_V2_DBG_LEVEL_TRACE, 460 /// output FW message. 461 E_VDEC_EX_V2_DBG_LEVEL_FW, 462 } VDEC_EX_V2_DbgLevel; 463 464 /// Type of FW source 465 typedef enum 466 { 467 E_VDEC_EX_V2_FW_SOURCE_NONE, 468 E_VDEC_EX_V2_FW_SOURCE_DRAM, 469 E_VDEC_EX_V2_FW_SOURCE_FLASH, 470 }VDEC_EX_V2_FWSourceType; 471 472 /// Format of CC (Closed Caption) 473 typedef enum 474 { 475 E_VDEC_EX_V2_CC_NONE = 0x00, 476 E_VDEC_EX_V2_CC_608 = 0x01, //For CC608 or 157 477 E_VDEC_EX_V2_CC_708 = 0x02, //For CC708 478 E_VDEC_EX_V2_CC_UNPACKED = 0x03, 479 } VDEC_EX_V2_CCFormat; 480 481 /// Type of CC 482 typedef enum 483 { 484 E_VDEC_EX_V2_CC_TYPE_NONE = 0, 485 E_VDEC_EX_V2_CC_TYPE_NTSC_FIELD1 = 1, 486 E_VDEC_EX_V2_CC_TYPE_NTSC_FIELD2 = 2, 487 E_VDEC_EX_V2_CC_TYPE_DTVCC = 3, 488 E_VDEC_EX_V2_CC_TYPE_NTSC_TWOFIELD = 4, 489 } VDEC_EX_V2_CCType; 490 491 typedef enum 492 { 493 E_VDEC_EX_V2_CC_GET_BUFF_START = 0x1, 494 E_VDEC_EX_V2_CC_GET_BUFF_SIZE, 495 E_VDEC_EX_V2_CC_GET_708_ENABLE 496 } VDEC_EX_V2_CCInfoCmd; 497 498 typedef enum 499 { 500 E_VDEC_EX_V2_STAGE_STOP = 0, 501 E_VDEC_EX_V2_STAGE_INIT, 502 E_VDEC_EX_V2_STAGE_PLAY, 503 E_VDEC_EX_V2_STAGE_PAUSE, 504 } VDEC_EX_V2_Stage; 505 506 typedef enum 507 { 508 /// Used before MApi_VDEC_EX_Flush(). 509 E_VDEC_EX_V2_PATTERN_FLUSH = 0, 510 /// Used after MApi_VDEC_EX_EnableLastFrameShow(). 511 E_VDEC_EX_V2_PATTERN_FILEEND, 512 }VDEC_EX_V2_PatternType; 513 514 typedef struct 515 { 516 MS_BOOL bInit; 517 MS_BOOL bIdle; 518 VDEC_EX_V2_Stage eStage; 519 } VDEC_EX_V2_Status; 520 521 typedef struct 522 { 523 MS_U32 u32Tmp; 524 } VDEC_EX_V2_Info; 525 526 typedef enum 527 { 528 E_VDEC_EX_V2_FRM_TYPE_I = 0, 529 E_VDEC_EX_V2_FRM_TYPE_P, 530 E_VDEC_EX_V2_FRM_TYPE_B, 531 E_VDEC_EX_V2_FRM_TYPE_OTHER, 532 E_VDEC_EX_V2_FRM_TYPE_NUM 533 } VDEC_EX_V2_FrameType; 534 535 typedef enum 536 { 537 ///< no field. 538 E_VDEC_EX_V2_FIELDTYPE_NONE, 539 ///< Top field only. 540 E_VDEC_EX_V2_FIELDTYPE_TOP, 541 ///< Bottom field only. 542 E_VDEC_EX_V2_FIELDTYPE_BOTTOM, 543 ///< Both fields. 544 E_VDEC_EX_V2_FIELDTYPE_BOTH, 545 E_VDEC_EX_V2_FIELDTYPE_NUM 546 } VDEC_EX_V2_FieldType; 547 548 typedef enum 549 { 550 E_VDEC_EX_V2_PATTERN_BEFORE_FRM = 0, 551 E_VDEC_EX_V2_PATTERN_AFTER_FRM, 552 E_VDEC_EX_V2_PATTERN_SKIP_DATA, 553 } VDEC_EX_V2_PatchPattern; 554 555 typedef enum 556 { 557 E_VDEC_EX_V2_PIC_STRUCTURE_RSV = 0, //reserved 558 E_VDEC_EX_V2_PIC_STRUCTURE_TOP, 559 E_VDEC_EX_V2_PIC_STRUCTURE_BOT, 560 E_VDEC_EX_V2_PIC_STRCUTURE_FRM, 561 } VDEC_EX_V2_PicStructure; 562 563 //VDEC FB reduction type 564 typedef enum 565 { 566 VDEC_EX_V2_FB_REDUCTION_NONE = 0, 567 VDEC_EX_V2_FB_REDUCTION_1_2, 568 VDEC_EX_V2_FB_REDUCTION_1_4 569 } VDEC_EX_V2_FBReductionType; 570 571 //VDEC set debug mode 572 typedef enum 573 { 574 E_VDEC_EX_V2_DBG_MODE_BYPASS_INSERT_START_CODE = 0, /// for UT 575 E_VDEC_EX_V2_DBG_MODE_BYPASS_DIVX_MC_PATCH, /// for UT 576 E_VDEC_EX_V2_DBG_MODE_NUM 577 } VDEC_EX_V2_DbgMode; 578 579 //VDEC set clock speed 580 typedef enum 581 { 582 E_VDEC_EX_V2_CLOCK_SPEED_NONE = 0, 583 E_VDEC_EX_V2_CLOCK_SPEED_HIGHEST, 584 E_VDEC_EX_V2_CLOCK_SPEED_HIGH, 585 E_VDEC_EX_V2_CLOCK_SPEED_MEDIUM, 586 E_VDEC_EX_V2_CLOCK_SPEED_LOW, 587 E_VDEC_EX_V2_CLOCK_SPEED_LOWEST, 588 E_VDEC_EX_V2_CLOCK_SPEED_DEFAULT, 589 } VDEC_EX_V2_ClockSpeed; 590 591 //VDEC FW TYPE 592 typedef enum 593 { 594 E_VDEC_EX_V2_FW_TYPE_MVD = 0, 595 E_VDEC_EX_V2_FW_TYPE_HVD, 596 } VDEC_EX_V2_FwType; 597 598 /// DecodeMode for f/w tasks 599 typedef enum 600 { 601 E_VDEC_EX_V2_DEC_MODE_DUAL_INDIE = 0, ///< Two independent tasks 602 E_VDEC_EX_V2_DEC_MODE_DUAL_3D, ///< Two dependent tasks for 3D 603 E_VDEC_EX_V2_DEC_MODE_SINGLE, ///< One task use the whole SRAM 604 E_VDEC_EX_V2_DEC_MODE_MVC = E_VDEC_EX_DEC_MODE_SINGLE, 605 } VDEC_EX_V2_DEC_MODE; 606 607 608 /// argument of DecodeMode structure for f/w tasks 609 typedef enum 610 { 611 //Group1:Set Korea3DTV mode 612 E_VDEC_EX_V2_DEC_KR3D_MODE_BASE = 0x0000, 613 E_VDEC_EX_V2_DEC_KR3D_INTERLACE_MODE = E_VDEC_EX_DEC_KR3D_MODE_BASE, 614 E_VDEC_EX_V2_DEC_KR3D_FORCE_P_MODE, 615 E_VDEC_EX_V2_DEC_KR3D_INTERLACE_TWO_PITCH, 616 E_VDEC_EX_V2_DEC_KR3D_FORCE_P_TWO_PITCH, 617 618 //Group2:Set PIP mode 619 E_VDEC_EX_V2_DEC_PIP_MODE_BASE = 0x1000, 620 E_VDEC_EX_V2_DEC_PIP_SYNC_INDIE = E_VDEC_EX_DEC_PIP_MODE_BASE, 621 E_VDEC_EX_V2_DEC_PIP_SYNC_MAIN_STC, 622 E_VDEC_EX_V2_DEC_PIP_SYNC_SWITCH 623 } VDEC_EX_V2_DEC_MODE_ARG; 624 625 typedef enum 626 { 627 E_VDEC_EX_V2_DIU_DRAM = 0, //MCU mode 628 E_VDEC_EX_V2_DIU_HVD = 1, 629 E_VDEC_EX_V2_DIU_MVD = 2, 630 E_VDEC_EX_V2_DIU_HVD_3DLR = 3, //MVC 631 E_VDEC_EX_V2_DIU_MVD_3DLR = 4, //Korea3D, WMV3D 632 E_VDEC_EX_V2_DIU_UNKNOWN = -1 633 } VDEC_EX_V2_DIU; 634 635 typedef enum 636 { 637 E_VDEC_EX_V2_CMD_GET_FREE_STREAM_ID, 638 E_VDEC_EX_V2_CMD_INIT, 639 E_VDEC_EX_V2_CMD_SET_CONTROL, 640 E_VDEC_EX_V2_CMD_GET_CONTROL, 641 E_VDEC_EX_V2_CMD_PRE_SET_CONTROL, 642 E_VDEC_EX_V2_CMD_POST_SET_CONTROL, 643 E_VDEC_EX_V2_CMD_NUM, 644 E_VDEC_EX_V2_CMD_MAX = E_VDEC_EX_V2_CMD_NUM, 645 } E_VDEC_EX_V2_IOCTL_CMD; 646 647 //VDEC user command id 648 typedef enum 649 { 650 //Group1:Set Control command================================ 651 E_VDEC_EX_V2_USER_CMD_SET_CONTROL_BASE = 0x0000, 652 E_VDEC_EX_V2_USER_CMD_REPEAT_LAST_FIELD, // Param: 1(ON), 0(OFF) 653 E_VDEC_EX_V2_USER_CMD_AVSYNC_REPEAT_TH, // Param:0x01 ~ 0xFF(repeat times), 0xFF:always repeat when av is not sync 654 E_VDEC_EX_V2_USER_CMD_DISP_ONE_FIELD, // Param: 1(ON), 0(OFF) 655 E_VDEC_EX_V2_USER_CMD_FD_MASK_DELAY_COUNT, // Param: unit is in vsync base for mute the fd_mask 656 E_VDEC_EX_V2_USER_CMD_FRC_OUTPUT, // Param: the address of VDEC_FRC_OutputParam 657 E_VDEC_EX_V2_USER_CMD_FRC_DROP_TYPE, // Param: 1(FRC_DROP_FIELD), 0(FRC_DROP_FRAME), default:0 658 E_VDEC_EX_V2_USER_CMD_FAST_DISPLAY, // Param: TRUE(Fast display), FALSE(Display until synced) 659 E_VDEC_EX_V2_USER_CMD_IGNORE_ERR_REF, // Param: TRUE(Ignore error reference), FALSE(Enable error reference handle) 660 E_VDEC_EX_V2_USER_CMD_FORCE_FOLLOW_DTV_SPEC, // Param: 1(ON), 0(OFF) 661 E_VDEC_EX_V2_USER_CMD_AVC_MIN_FRM_GAP, // Param: Set the theshold of H264 frame gap, 0xFFFFFFFF don't care frame gap 662 E_VDEC_EX_V2_USER_CMD_DISABLE_SEQ_CHG, // Param: 1(Disable), 0(Enable) 663 E_VDEC_EX_V2_USER_CMD_SET_DISP_OUTSIDE_CTRL_MODE, // Param: 1(ON) used for Openmax, 0(OFF) used for mstreamer and mm mode ,default : off 664 E_VDEC_EX_V2_USER_CMD_SET_DTV_USER_DATA_MODE, // Param: 0(Support normal DVB CC, default case), 1(Support ATSC DirectTV CC), 2,3,4(Reserved) 665 E_VDEC_EX_V2_USER_CMD_SET_SINGLE_TASK_MODE, 666 E_VDEC_EX_V2_USER_CMD_AVC_DISABLE_ANTI_VDEAD, 667 E_VDEC_EX_V2_USER_CMD_DTV_RESET_MVD_PARSER, // Param: 0(Disable), 1(Enable) 668 E_VDEC_EX_V2_USER_CMD_PVR_FLUSH_FRAME_BUFFER, 669 E_VDEC_EX_V2_USER_CMD_FORCE_INTERLACE_MODE, 670 E_VDEC_EX_V2_USER_CMD_RELEASE_FD_MASK, // Param: 1 to release fd mask when zooming or slow motion 671 E_VDEC_EX_V2_USER_CMD_NULL, // E_VDEC_EX_USER_CMD_SET_DECODE_MODE 672 E_VDEC_EX_V2_USER_CMD_SUPPORT_AVC_TO_MVC, // Param: 0(Do not support), 1(Support AVC to MVC) 673 E_VDEC_EX_V2_USER_CMD_3DLR_VIEW_EXCHANGE, // Param: 0(Disable), 1(View L/R exhange) 674 E_VDEC_EX_V2_USER_CMD_SET_VSIZE_ALIGN, // Param: 0(Disable), 1(Enable) 675 E_VDEC_EX_V2_USER_CMD_SHOW_DECODE_ORDER, // Param: 0(Disable), 1(Enable) 676 E_VDEC_EX_V2_USER_CMD_AVC_DISP_IGNORE_CROP, // Param: 0(Disable), 1(Enable) 677 E_VDEC_EX_V2_USER_CMD_SET_DISP_FINISH_MODE, 678 E_VDEC_EX_V2_USER_CMD_SET_AVSYNC_MODE, 679 E_VDEC_EX_V2_USER_CMD_SUSPEND_DYNAMIC_SCALE, // Param: 0(Disable, non-suspend DS), 1(Enable, suspend DS) 680 E_VDEC_EX_V2_USER_CMD_FORCE_AUTO_MUTE, 681 E_VDEC_EX_V2_USER_CMD_AVC_NEW_SLOW_MOTION, // Param: 0(Disable), 1(Enable) 682 E_VDEC_EX_V2_USER_CMD_PUSH_DISPQ_WITH_REF_NUM, // Param: 0(Disable), 1(Enable) 683 E_VDEC_EX_V2_USER_CMD_DS_RESV_N_BUFFER, // Param: 0(Disable), 1(Enable) 684 E_VDEC_EX_V2_USER_CMD_RM_ENABLE_PTS_TBL, // Param: 0(Disable), 1(Enable) 685 E_VDEC_EX_V2_USER_CMD_FLUSH_PTS_BUF, 686 E_VDEC_EX_V2_USER_CMD_SET_IDCT_MODE, // Param: 0(Original), 1(new IDCT) 687 E_VDEC_EX_V2_USER_CMD_DROP_ERR_FRAME, // Param: 0(Disable), 1(Enable) 688 E_VDEC_EX_V2_USER_CMD_SET_CC608_INFO_ENHANCE_MODE, 689 E_VDEC_EX_V2_USER_CMD_IGNORE_PIC_OVERRUN, // Param: 0(Disable), 1(Enable) 690 E_VDEC_EX_V2_USER_CMD_SET_SELF_SEQCHANGE, 691 E_VDEC_EX_V2_USER_CMD_AUTO_EXHAUST_ES_MODE, // Param: set the upper bound (arg[31:16]), and lower bound (arg[15:0])of ES level, Unit = 1KBytes, Auto drop display to consume ES data as soon as possible when ES level is higher than upper bound 692 E_VDEC_EX_V2_USER_CMD_CTL_SPEED_IN_DISP_ONLY, // Param: 0(Original: Dec and disp time), 1(In Disp only) 693 E_VDEC_EX_V2_USER_CMD_AVC_SUPPORT_REF_NUM_OVER_MAX_DPB_SIZE, // Param: 0(Disable), 1(Enable) 694 E_VDEC_EX_V2_USER_CMD_RETURN_INVALID_AFD, // Param: 0(Disable), 1(Enable) 695 E_VDEC_EX_V2_USER_CMD_FIELD_POLARITY_DISPLAY_ONE_FIELD,// Param : VDEC_EX_V2_Field_Polarity 696 E_VDEC_EX_V2_USER_CMD_AVC_FORCE_BROKEN_BY_US, // Param: 0(Disable), 1(Enable) 697 E_VDEC_EX_V2_USER_CMD_SHOW_FIRST_FRAME_DIRECT, // Param: 0(Disable), 1(Enable), Push first frame to display queue directly.. 698 E_VDEC_EX_V2_USER_CMD_AVC_RESIZE_DOS_DISP_PEND_BUF, // Param: size of AVC display pending buffer for display outside mode 699 E_VDEC_EX_V2_USER_CMD_SET_XC_LOW_DELAY_PARA, // Param: arg0 for diff_field_number... 700 E_VDEC_EX_V2_USER_CMD_SET_SECURE_MODE, // Param: use enum VDEC_EX_SecureMode 701 E_VDEC_EX_V2_USER_CMD_RVU_SETTING_MODE, // Param: 0(Disable), 1(drop B-frame and force IDR) 702 E_VDEC_EX_V2_USER_CMD_FRAMERATE_HANDLING, // Arg 0~60000, 0: Disable, 1000 ~ 60000: Used the arg to set frame rate when the sequence did not have frame rate info. and arg is not zero. (The frame unit is (arg/1000)fps, Exp: 30000 = 30.000 fps), others: Do not thing. 703 E_VDEC_EX_V2_USER_CMD_DUAL_NON_BLOCK_MODE, // Param: 0(Disable), 1(Enable) 704 E_VDEC_EX_V2_USER_CMD_IGNORE_PIC_STRUCT_DISPLAY, // Param: 0(Disable), 1(Enable) Ignore Pic_struct when display progressive frame. 705 E_VDEC_EX_V2_USER_CMD_INPUT_PTS_FREERUN_MODE, // Param: 0(Disable), 1(Enable) Video free run when the difference between input PTS and current STC is large than E_HVD_CMD_FREERUN_THRESHOLD + 1s; 706 E_VDEC_EX_V2_USER_CMD_ERR_CONCEAL_SLICE_1ST_MB, // Param: 0(disable), Error concealment from current/last MB position; 1(enale) Error concealment from current slice first MB.(Need enable E_HVD_CMD_ERR_CONCEAL) 707 E_VDEC_EX_V2_USER_CMD_SET_EXTERNAL_DS_BUFFER, // Param: External DS Buffer info. 708 E_VDEC_EX_V2_USER_CMD_SET_MIN_TSP_DATA_SIZE, // Param: Resize HVD_FW_AVC_ES_MIN_TSP_DATA_SIZE 709 E_VDEC_EX_V2_USER_CMD_SET_DMX_FRAMERATE, 710 E_VDEC_EX_V2_USER_CMD_SET_DMX_FRAMERATEBASE, 711 E_VDEC_EX_V2_USER_CMD_ENABLE_CC_608_EXTERNAL_BUFFER, // Param: u32_ccinfo 32bits-->([31:8]+[7:0] = addr+size), addr is kb unit, if u32_ccinfo ==0, it will turn off this feature 712 E_VDEC_EX_V2_USER_CMD_ENABLE_CC_708_EXTERNAL_BUFFER, // Param: u32_ccinfo 32bits-->([31:8]+[7:0] = addr+size), addr is kb unit, if u32_ccinfo ==0, it will turn off this feature 713 E_VDEC_EX_V2_USER_CMD_SET_TIME_INC_PREDICT_PARA, 714 E_VDEC_EX_V2_USER_CMD_ENABLE_DECODE_ENGINE_TIMEOUT, // Param: Enable/Disable decode timeout solution, timeout value unit:ms (VDEC_EX_Decode_Timeout_Param) 715 E_VDEC_EX_V2_USER_CMD_AUTO_FREE_ES, // Param: 0(Disable), 1(Enable) 716 E_VDEC_EX_V2_USER_CMD_FRAMEBUFFER_AUTO_MODE, //Param: 0(Disable),1(Enable), this cmd is used for MVD. 717 E_VDEC_EX_V2_USER_CMD_SET_SMOOTH_REWIND, //enable/disable or support smooth rewind 718 E_VDEC_EX_V2_USER_CMD_SET_ERROR_TOLERANCE, // Param: VDEC_EX_Err_Tolerance; bEnable: enable or disable; u8Tolerance: err_rate(0%~100%) 719 E_VDEC_EX_V2_USER_CMD_AUTO_DROP_DISPLAY_QUEUE, // Param: 0(Disable), N = 1~16: Drop display queue when display queue above than N frames. 720 E_VDEC_EX_V2_USER_CMD_USE_CPB_REMOVAL_DEALY, // Param: 0(Disable), 1(Enable) 721 E_VDEC_EX_V2_USER_CMD_SKIP_N_FRAME, // Param: 0:disable, N = 1~63. Skip N frame. 722 E_VDEC_EX_V2_USER_CMD_SET_PTS_US_MODE, //Param: 1(enable), 0(disable ) PTS output by micro second level, 723 E_VDEC_EX_V2_USER_CMD_AUTO_INSERT_DUMMY_DATA, //Param: 1(enable),0(disable), Enable/Disable utopia auto insert dummy pattern in SLQ/BBU mode. 724 E_VDEC_EX_V2_USER_CMD_DROP_ONE_PTS, 725 E_VDEC_EX_V2_USER_CMD_PVR_TIMESHIFT_SEAMLESS_MODE, 726 E_VDEC_EX_V2_USER_CMD_AUTO_REDUCE_ES_DATA, 727 E_VDEC_EX_V2_USER_CMD_RM_FORCE_MCU_MODE_ES, // Param: 0(Disable), 1(Enable) 728 E_VDEC_EX_V2_USER_CMD_FORCE_PROGRESSIVE_MODE, // Param: 1(enable),0(disable), Enable/Disable force progressive mode 729 E_VDEC_EX_V2_USER_CMD_SET_FRAMEBUFF2, // Param[0]=Addr and Param[1]=size for the second frame buffer 730 E_VDEC_EX_V2_USER_CMD_SET_TRICKPLAY_2X_MODE, // Param:0(vsync),1(avsync) 731 E_VDEC_EX_V2_USER_CMD_FRC_ONLY_SHOW_TOP_FIELD, // Param: 0(Disable), 1(Enable) only show top filed for FRC mode 732 E_VDEC_EX_V2_USER_CMD_DIRECT_STC_MODE, // Param: stc in ms; 0x0~0x1FFFFFFFF/90, vdec fw use this value as stc; 0xFFFFFFFF, disable ths feature 733 E_VDEC_EX_V2_USER_CMD_ENABLE_PTS_DECTECTOR, // Param: 1(ON), 0(OFF) //for LGE hotel mode, Luke 734 E_VDEC_EX_V2_USER_CMD_DISABLE_ES_FULL_STOP, 735 E_VDEC_EX_V2_USER_CMD_SET_DV_XC_SHM_ADDR, // Param: PHY Addr for communicating with XC Dolby Vision DM/Comp 736 E_VDEC_EX_V2_USER_CMD_SET_ENABLE_HDR, // Param: 0(Disable), 1(Enable) 737 #ifdef VDEC_CAP_DV_OTT_API 738 E_VDEC_EX_V2_USER_CMD_SET_DV_INFO, 739 #endif 740 E_VDEC_EX_V2_USER_CMD_DISABLE_PBFRAME_MODE, // Param: 1(Disable), 0(Enable) 741 742 743 744 E_VDEC_EX_V2_USER_CMD_EXIT, 745 E_VDEC_EX_V2_USER_CMD_RST, 746 E_VDEC_EX_V2_USER_CMD_CHECK_DISPINFO_READY, 747 E_VDEC_EX_V2_USER_CMD_SET_FRC_MODE, 748 E_VDEC_EX_V2_USER_CMD_SET_DYNSCALING_PARAMS, 749 E_VDEC_EX_V2_USER_CMD_SET_DBG_LEVEL, 750 E_VDEC_EX_V2_USER_CMD_PLAY, 751 E_VDEC_EX_V2_USER_CMD_PAUSE, 752 E_VDEC_EX_V2_USER_CMD_RESUME, 753 E_VDEC_EX_V2_USER_CMD_STEP_DISP, 754 E_VDEC_EX_V2_USER_CMD_STEP_DECODE, 755 E_VDEC_EX_V2_USER_CMD_SET_TRICK_MODE, 756 E_VDEC_EX_V2_USER_CMD_PUSH_DECQ, 757 E_VDEC_EX_V2_USER_CMD_FLUSH, 758 E_VDEC_EX_V2_USER_CMD_ENABLE_LAST_FRAME_SHOW, 759 E_VDEC_EX_V2_USER_CMD_SET_SPEED, 760 E_VDEC_EX_V2_USER_CMD_SET_FREEZE_DISP, 761 E_VDEC_EX_V2_USER_CMD_SET_BLUE_SCREEN, 762 E_VDEC_EX_V2_USER_CMD_RESET_PTS, 763 E_VDEC_EX_V2_USER_CMD_AVSYNC_ON, 764 E_VDEC_EX_V2_USER_CMD_AVSYNC_FREERUN_THRESHOLD, 765 E_VDEC_EX_V2_USER_CMD_SET_EVENT_MULTICALLBACK, 766 E_VDEC_EX_V2_USER_CMD_UNSET_EVENT_MULTICALLBACK, 767 E_VDEC_EX_V2_USER_CMD_FIRE_DEC, 768 E_VDEC_EX_V2_USER_CMD_SEEK_TO_PTS, 769 E_VDEC_EX_V2_USER_CMD_SKIP_TO_PTS, 770 E_VDEC_EX_V2_USER_CMD_DISABLE_DEBLOCKING, 771 E_VDEC_EX_V2_USER_CMD_DISABLE_QUARTER_PIXEL, 772 E_VDEC_EX_V2_USER_CMD_SET_AUTO_RM_LST_ZERO_BYTE, 773 E_VDEC_EX_V2_USER_CMD_SET_BALANCE_BW, 774 E_VDEC_EX_V2_USER_CMD_GEN_PATTERN, 775 E_VDEC_EX_V2_USER_CMD_MHEG_DECODE_IFRAME, 776 E_VDEC_EX_V2_USER_CMD_MHEG_RST_IFRAME_DEC, 777 E_VDEC_EX_V2_USER_CMD_CC_START_PARSING, 778 E_VDEC_EX_V2_USER_CMD_CC_STOP_PARSING, 779 E_VDEC_EX_V2_USER_CMD_CC_UPDATE_READ_PTR, 780 E_VDEC_EX_V2_USER_CMD_SET_BLOCK_DISPLAY, 781 E_VDEC_EX_V2_USER_CMD_ENABLE_ES_BUFF_MALLOC, 782 E_VDEC_EX_V2_USER_CMD_DISPLAY_FRAME, 783 E_VDEC_EX_V2_USER_CMD_RELEASE_FRAME, 784 E_VDEC_EX_V2_USER_CMD_CAPTURE_FRAME, 785 E_VDEC_EX_V2_USER_CMD_CC_INIT, 786 E_VDEC_EX_V2_USER_CMD_CC_SET_CFG, 787 E_VDEC_EX_V2_USER_CMD_CC_SET_BUFF_START_ADDR, 788 E_VDEC_EX_V2_USER_CMD_CC_UPDATE_WRITE_ADDR, 789 E_VDEC_EX_V2_USER_CMD_CC_UPDATE_READ_ADDR, 790 E_VDEC_EX_V2_USER_CMD_CC_DISABLE_PARSING, 791 E_VDEC_EX_V2_USER_CMD_SET_SLOW_SYNC, 792 E_VDEC_EX_V2_USER_CMD_SET_DYNAMIC_DISP_PATH, 793 E_VDEC_EX_V2_USER_CMD_SET_AVSYNC_DISP_AUTO_DROP, 794 E_VDEC_EX_V2_USER_CMD_ENABLE_QOS_INFO, 795 E_VDEC_EX_V2_USER_CMD_SET_CODEC_CONFIG, // VP9 HDR info, or other config data for video decoder 796 E_VDEC_EX_V2_USER_CMD_SET_VP94K2KCHECK, 797 E_VDEC_EX_V2_USER_CMD_ADJUST_DECODER_FREQUENCY, // VDEC_EX_Decoder_Frequency; VDEC_EX_DECODER_FREQUENCY_DOWN, VDEC_EX_DECODER_FREQUENCY_UP, VDEC_EX_DECODER_FREQUENCY_MAX, VDEC_EX_DECODER_FREQUENCY_MIN 798 E_VDEC_EX_V2_USER_CMD_PUSI_CONTROL, 799 800 E_VDEC_EX_V2_USER_CMD_MVC_SET_CMD_BASE = 0x0800, 801 E_VDEC_EX_V2_USER_CMD_MVC_BBU2_PUSH_PACKET, // Param: Packet Info. 802 E_VDEC_EX_V2_USER_CMD_MVC_BBU2_FIRE_DECCMD, // Param: Non 803 804 E_VDEC_EX_V2_USER_CMD_UT_SET_CMD_BASE = 0x0900, 805 E_VDEC_EX_V2_USER_CMD_UT_SET_DBG_MODE, // Param: for enable the specify dbg mode for UT 806 E_VDEC_EX_V2_USER_CMD_UT_CLR_DBG_MODE, // Param: for disable the specify dbg mode for UT 807 808 E_VDEC_EX_V2_USER_CMD_SET_MBX_PARAM, 809 //Group2:Get Control command================================ 810 E_VDEC_EX_V2_USER_CMD_GET_CONTROL_BASE = 0x1000, 811 E_VDEC_EX_V2_USER_CMD_GET_CHROMA_TYPE, 812 E_VDEC_EX_V2_USER_CMD_GET_REAL_FRAMERATE, // Get Real FrameRate reported by decoder 813 E_VDEC_EX_V2_USER_CMD_GET_COLOR_MATRIX, // Get color matrix coefficients reported by decoder 814 E_VDEC_EX_V2_USER_CMD_GET_MAIN_STREAM_ID, // Get activated main stream ID 815 E_VDEC_EX_V2_USER_CMD_GET_SUB_STREAM_ID, // Get activated sub stream ID 816 E_VDEC_EX_V2_USER_CMD_GET_DYNSCALE_ENABLED, 817 E_VDEC_EX_V2_USER_CMD_GET_FPA_SEI, //Get SEI info 818 E_VDEC_EX_V2_USER_CMD_GET_U64PTS, 819 E_VDEC_EX_V2_USER_CMD_GET_ORI_INTERLACE_MODE, 820 E_VDEC_EX_V2_USER_CMD_GET_MBS_ONLY_FLAG, 821 E_VDEC_EX_V2_USER_CMD_GET_CRC_VALUE, //Get frame Y/UV crc value 822 E_VDEC_EX_V2_USER_CMD_GET_BBU_Q_NUM, 823 E_VDEC_EX_V2_USER_CMD_GET_DISP_FRAME_NUM, 824 E_VDEC_EX_V2_USER_CMD_GET_FPA_SEI_EX, //Get SEI info(enhancement) 825 E_VDEC_EX_V2_USER_CMD_GET_ES_BUFFER_STATUS, //Get ES buffer over/under flow status 826 E_VDEC_EX_V2_USER_CMD_GET_CODEC_TYPE, // Get Codec type 827 E_VDEC_EX_V2_USER_CMD_GET_SHAREMEMORY_BASE, 828 E_VDEC_EX_V2_USER_CMD_GET_IS_LEAST_DISPQ_SIZE_FLAG, 829 E_VDEC_EX_V2_USER_CMD_GET_FIELD_PIC_FLAG, // Param: Get Field Pic Flag 830 E_VDEC_EX_V2_USER_CMD_GET_SUPPORT_2ND_MVOP_INTERFACE, // Param: TRUE : support, FALSE : not support 831 E_VDEC_EX_V2_USER_CMD_GET_FB_USAGE_MEM, // Get FrameBuufer Size needed by decoder 832 E_VDEC_EX_V2_USER_CMD_GET_XC_LOW_DELAY_INT_STATE, // Get xc_low_delay int state... 833 E_VDEC_EX_V2_USER_CMD_GET_VSYNC_BRIDGE_ADDR, 834 E_VDEC_EX_V2_USER_CMD_GET_FRAME_INFO_EX, 835 E_VDEC_EX_V2_USER_CMD_GET_FLUSH_PATTEN_ENTRY_NUM, 836 E_VDEC_EX_V2_USER_CMD_GET_DS_BUF_MIU_SEL, //For those chips which has 3 MIU, use this get control to get correct miu select of DS buffer 837 E_VDEC_EX_V2_USER_CMD_GET_FW_STATUS_FLAG, 838 E_VDEC_EX_V2_USER_CMD_GET_HW_MAX_PIXEL, 839 E_VDEC_EX_V2_USER_CMD_GET_FLOW_CONTROL_U64PTS_DIFF, // based on PTS table Rdptr and Wrptr, support TSP mode only 840 E_VDEC_EX_V2_USER_CMD_GET_NEXT_DISP_FRAME_INFO_EXT, //replace of E_VDEC_EX_USER_CMD_GET_FRAME_INFO_EX 841 E_VDEC_EX_V2_USER_CMD_GET_VSYNC_BRIDGE_EXT_ADDR, //get vsync bridge ext addr 842 E_VDEC_EX_V2_USER_CMD_GET_EVENT_FLAG, 843 E_VDEC_EX_V2_USER_CMD_GET_STATUS, 844 E_VDEC_EX_V2_USER_CMD_CHECK_DISPINFORDY, 845 E_VDEC_EX_V2_USER_CMD_IS_STEP_DISP_DONE, 846 E_VDEC_EX_V2_USER_CMD_IS_STEP_DECODE_DONE, 847 E_VDEC_EX_V2_USER_CMD_GET_DISP_INFO, 848 E_VDEC_EX_V2_USER_CMD_GET_SRC_MODE, 849 E_VDEC_EX_V2_USER_CMD_IS_AVSYNC_ON, 850 E_VDEC_EX_V2_USER_CMD_IS_WITH_VALID_STREAM, 851 E_VDEC_EX_V2_USER_CMD_IS_DISP_FINISH, 852 E_VDEC_EX_V2_USER_CMD_IS_IFRAME_FOUND, 853 E_VDEC_EX_V2_USER_CMD_IS_SEQ_CHG, 854 E_VDEC_EX_V2_USER_CMD_IS_REACH_SYNC, 855 E_VDEC_EX_V2_USER_CMD_IS_START_SYNC, 856 E_VDEC_EX_V2_USER_CMD_IS_FREERUN, 857 E_VDEC_EX_V2_USER_CMD_IS_WITH_LOW_DELAY, 858 E_VDEC_EX_V2_USER_CMD_IS_ALL_BUFFER_EMPTY, 859 E_VDEC_EX_V2_USER_CMD_GET_EXT_DISP_INFO, 860 E_VDEC_EX_V2_USER_CMD_GET_DEC_FRAME_INFO, 861 E_VDEC_EX_V2_USER_CMD_GET_DISP_FRAME_INFO, 862 E_VDEC_EX_V2_USER_CMD_GET_DEC_TIMECODE, 863 E_VDEC_EX_V2_USER_CMD_GET_DISP_TIMECODE, 864 E_VDEC_EX_V2_USER_CMD_GET_EVENT_INFO, 865 E_VDEC_EX_V2_USER_CMD_GET_ACTIVE_FORMAT, 866 E_VDEC_EX_V2_USER_CMD_GET_COLOUR_PRIMARIES, 867 E_VDEC_EX_V2_USER_CMD_GET_FW_VERSION, 868 E_VDEC_EX_V2_USER_CMD_GET_GOP_CNT, 869 E_VDEC_EX_V2_USER_CMD_GET_ES_WRITE_PTR, 870 E_VDEC_EX_V2_USER_CMD_GET_ES_READ_PTR, 871 E_VDEC_EX_V2_USER_CMD_GET_PTS, 872 E_VDEC_EX_V2_USER_CMD_GET_NEXT_PTS, 873 E_VDEC_EX_V2_USER_CMD_GET_VIDEO_PTS_STC_DELTA, 874 E_VDEC_EX_V2_USER_CMD_GET_ERR_CODE, 875 E_VDEC_EX_V2_USER_CMD_GET_ERR_CNT, 876 E_VDEC_EX_V2_USER_CMD_GET_BITRATE, 877 E_VDEC_EX_V2_USER_CMD_GET_FRAME_CNT, 878 E_VDEC_EX_V2_USER_CMD_GET_SKIP_CNT, 879 E_VDEC_EX_V2_USER_CMD_GET_DROP_CNT, 880 E_VDEC_EX_V2_USER_CMD_GET_DISP_CNT, 881 E_VDEC_EX_V2_USER_CMD_GET_DECQ_VACANCY, 882 E_VDEC_EX_V2_USER_CMD_IS_32_PULLDOWN, 883 E_VDEC_EX_V2_USER_CMD_IS_ALIVE, 884 E_VDEC_EX_V2_USER_CMD_IS_CC_AVAILABLE, 885 E_VDEC_EX_V2_USER_CMD_GET_CC_INFO, 886 E_VDEC_EX_V2_USER_CMD_GET_TRICK_MODE, 887 E_VDEC_EX_V2_USER_CMD_GET_ACTIVE_CODEC_TYPE, 888 E_VDEC_EX_V2_USER_CMD_GET_PATTERN_LEAST_LENGTH, 889 E_VDEC_EX_V2_USER_CMD_MHEG_IS_IFRAME_DECODING, 890 E_VDEC_EX_V2_USER_CMD_CC_GET_WRITE_PTR, 891 E_VDEC_EX_V2_USER_CMD_CC_GET_READ_PTR, 892 E_VDEC_EX_V2_USER_CMD_CC_GET_IS_OVERFLOW, 893 E_VDEC_EX_V2_USER_CMD_GET_HW_KEY, 894 E_VDEC_EX_V2_USER_CMD_GET_ES_BUFF_VACANCY, 895 E_VDEC_EX_V2_USER_CMD_GET_ES_BUFF, 896 E_VDEC_EX_V2_USER_CMD_GET_NEXT_DISP_FRAME, 897 E_VDEC_EX_V2_USER_CMD_CC_GET_INFO, 898 E_VDEC_EX_V2_USER_CMD_CC_GET_IS_RST_DONE, 899 E_VDEC_EX_V2_USER_CMD_CC_GET_IS_BUFF_OVERFLOW, 900 E_VDEC_EX_V2_USER_CMD_CC_GET_WRITE_ADDR, 901 E_VDEC_EX_V2_USER_CMD_CC_GET_READ_ADDR, 902 E_VDEC_EX_V2_USER_CMD_GETLIBVER, 903 E_VDEC_EX_V2_USER_CMD_GETINFO, 904 E_VDEC_EX_V2_USER_CMD_CHECKCAPS, 905 E_VDEC_EX_V2_USER_CMD_IS_FRAME_RDY, 906 E_VDEC_EX_V2_USER_CMD_GET_DCV_SEI, 907 E_VDEC_EX_V2_USER_CMD_GET_VUI_DISP_INFO, 908 E_VDEC_EX_V2_USER_CMD_GET_CODEC_CAP, 909 E_VDEC_EX_V2_USER_CMD_GET_PRE_PAS_U64PTS, 910 E_VDEC_EX_V2_USER_CMD_GET_PVRSEAMLESS_INFO, 911 E_VDEC_EX_V2_USER_CMD_GET_CLLI_SEI, //Content light level Info 912 E_VDEC_EX_V2_USER_CMD_GET_SEQ_CHANGE_INFO, // Get the reason why seq changes 913 E_VDEC_EX_V2_USER_CMD_GET_DISP_QUEUE_EMPTY, 914 E_VDEC_EX_V2_USER_CMD_GET_NOT_SUPPORT_INFO, 915 E_VDEC_EX_V2_USER_CMD_GET_BUFFER_INFO, // Param: VDEC_EX_BufferInfo 916 E_VDEC_EX_V2_USER_CMD_GET_MIN_TSP_DATA_SIZE, 917 E_VDEC_EX_V2_USER_CMD_GET_NEXT_DISP_FRAME_QOS_INFO, 918 E_VDEC_EX_V2_USER_CMD_GET_SEQ_INFO, 919 E_VDEC_EX_V2_USER_CMD_GET_EXTEND_DISP_INFO, 920 E_VDEC_EX_V2_USER_CMD_GET_CODEC_PROFILE_CAP, 921 922 E_VDEC_EX_V2_USER_CMD_MVC_GET_CMD_BASE = 0x1800, 923 E_VDEC_EX_V2_USER_CMD_GET_MVC_SUB_FRAME_DISP_INFO, // Param: VDEC_FrameInfo pointer. 924 E_VDEC_EX_V2_USER_CMD_GET_MVC_BBU2_DECQ_VACANCY, // Param: BBU2 Dec Q Vacancy. 925 E_VDEC_EX_V2_USER_CMD_GET_MVC_ES2_READ_PTR, // Param: ES2 read pointer. 926 E_VDEC_EX_V2_USER_CMD_GET_MVC_ES2_WRITE_PTR, // Param: ES2 Write pointer. 927 E_VDEC_EX_V2_USER_CMD_GET_ES_QUANTITY, // Param: Get ES buffer Level. 928 E_VDEC_EX_V2_USER_CMD_GET_ES2_QUANTITY, // Param: Get ES2 buffer Level. 929 930 E_VDEC_EX_V2_USER_CMD_GET_SECURE_MODE, 931 //Group3:Preset Control command====================== 932 //Group3-1:Common system Preset Control command 933 E_VDEC_EX_V2_USER_CMD_SYSTEM_PRESET_CONTROL_BASE = 0x2000, 934 E_VDEC_EX_V2_USER_CMD_SYSTEM_PRESET_VPU_CLOCK, //Param: VDEC_EX_ClockSpeed 935 936 //Group3-2:HVD System Preset Control command 937 E_VDEC_EX_V2_USER_CMD_SYSTEM_PRESET_HVD_BASE = 0x2100, 938 E_VDEC_EX_V2_USER_CMD_SYSTEM_PRESET_HVD_CLOCK, //Param: VDEC_EX_ClockSpeed 939 940 //Group3-3:MVD System Preset Control command 941 E_VDEC_EX_V2_USER_CMD_SYSTEM_PRESET_MVD_BASE = 0x2200, 942 E_VDEC_EX_V2_USER_CMD_SYSTEM_PRESET_MVD_CLOCK, //Param: VDEC_EX_ClockSpeed 943 E_VDEC_EX_V2_USER_CMD_VPU_SECURITY_MODE, //Param: 0:disable,1:enable 944 E_VDEC_EX_V2_USER_CMD_PRESET_DECODE_MODE, 945 E_VDEC_EX_V2_USER_CMD_PRESET_ENABLETURBOMODE, 946 E_VDEC_EX_V2_USER_CMD_PRESETSINGLEDECODE, 947 E_VDEC_EX_V2_USER_CMD_PREGETSTATUS, 948 E_VDEC_EX_V2_USER_CMD_SETPOWERSTATE, 949 950 951 //Group3-4:Preset Control command============================= 952 E_VDEC_EX_V2_USER_CMD_PRESET_CONTROL_BASE = 0x2300, 953 E_VDEC_EX_V2_USER_CMD_HVD_ONE_PENDING_BUFFER_MODE, //Param: 0(Disable), 1(Enable), use only one pending buffer instead of two for HVD 954 E_VDEC_EX_V2_USER_CMD_MVD_HWBUFFER_REMAPPING_MODE, //Param: 0(Disable), 1(Enable),Allcate HW buffer to start of frame buffer 955 E_VDEC_EX_V2_USER_CMD_SET_SHAREMEMORY_BASE, 956 E_VDEC_EX_V2_USER_CMD_HVD_COL_BBU_MODE, //Param: HVD use colocated BBU mode, 0: disable, 1: enable /*johnny.ko*/ 957 E_VDEC_EX_V2_USER_CMD_HVD_IAPGN_BUF_SHARE_BW_MODE, //Param: HVD IAP GN Buffer address, 0xFFFFFFFF means disable 958 /***/E_VDEC_EX_V2_USER_CMD_DTV_DEBUG_MODE, 959 E_VDEC_EX_V2_USER_CMD_HVD_TS_IN_BBU_MODE, 960 E_VDEC_EX_V2_USER_CMD_AUTO_ARRANGE_FRAMEBUFFER_USAGE, //Param: 0:disable,1:enable, address:PA,size:unit is byte 961 E_VDEC_EX_V2_USER_CMD_THUMBNAIL_MODE, //Param: 0(Disable), 1(Enable), use small frame buffer to decdoe thumbnail 962 E_VDEC_EX_V2_USER_CMD_FORCE_8BIT_DEC_MODE, //Param: force 8bit decode mode, 0: disable, 1: enable 963 E_VDEC_EX_V2_USER_CMD_DV_SINGLE_LAYER_MODE, //Param: Dolby vision single layer mode, 0: disable, 1: enable 964 E_VDEC_EX_V2_USER_CMD_MFCODEC_MODE, 965 E_VDEC_EX_V2_USER_CMD_VDEC_FEATURE, //AP control VDEC features 966 E_VDEC_EX_V2_USER_CMD_DYNAMIC_CMA_MODE, //enable dynamic cma features 967 E_VDEC_EX_V2_USER_CMD_CONNECT_INPUT_TSP, //Param: VDEC_EX_INPUT_TSP, 0(Disable), 1(TSP 0) 968 E_VDEC_EX_V2_USER_CMD_CONNECT_DISPLAY_PATH, //Param: 0(display by DIP), 1(MVOP MAIN), 2(MVOP SUB) 969 E_VDEC_EX_V2_USER_CMD_SET_DISPLAY_MODE, //Param: 0(MCU MODE), 1(HARDWIRE) 970 E_VDEC_EX_V2_USER_CMD_BITSTREAMBUFFER_MONOPOLY, //Param: TRUE : support, FALSE : not support 971 E_VDEC_EX_V2_USER_CMD_FRAMEBUFFER_MONOPOLY, //Param: TRUE : support, FALSE : not support 972 E_VDEC_EX_V2_USER_CMD_SPECIFY_TASK_SPEC, //Param: VDEC_EX_TASK_SPEC 973 E_VDEC_EX_V2_USER_CMD_SET_TOTALRANGE_BITSTREAMBUFFER, //Param: VDEC_EX_TotalBufRange 974 E_VDEC_EX_V2_USER_CMD_SET_TOTALRANGE_FRAMEBUFFER1, //Param: VDEC_EX_TotalBufRange 975 E_VDEC_EX_V2_USER_CMD_SET_TOTALRANGE_FRAMEBUFFER2, //Param: VDEC_EX_TotalBufRange 976 E_VDEC_EX_V2_USER_CMD_PRESET_STC, //Param: STC index 977 E_VDEC_EX_V2_USER_CMD_CAL_FRAMERATE, 978 E_VDEC_EX_V2_USER_CMD_SET_BUFFER_INFO, //Param: VDEC_EX_BufferInfo 979 E_VDEC_EX_V2_USER_CMD_HDR10_UPDATE_PERFRAME, 980 E_VDEC_EX_V2_USER_CMD_SET_CUSTOMER_MODE, //Param: 0:disable,1:enable. For specific customer behavior 981 982 //Group4:Postset Control command====================== 983 E_VDEC_EX_V2_USER_CMD_SYSTEM_POSTSET_CONTROL_BASE = 0x3000, 984 E_VDEC_EX_V2_USER_CMD_SYSTEM_POSTSET_CLEAR_PROCESS_RELATED, 985 986 //Group5:System PreGet Control command====================== 987 //Group5-1:Common system Preget Control command 988 E_VDEC_EX_V2_USER_CMD_SYSTEM_PREGET_CONTROL_BASE = 0x4000, 989 E_VDEC_EX_V2_USER_CMD_SYSTEM_PREGET_FB_MEMORY_USAGE_SIZE, 990 #ifdef VDEC_CAP_SYSTEM_PREGET_API 991 #ifdef VDEC_CAP_DV_OTT_API 992 E_VDEC_EX_V2_USER_CMD_SYSTEM_PREGET_DV_SUPPORT_PROFILE, 993 E_VDEC_EX_V2_USER_CMD_SYSTEM_PREGET_DV_SUPPORT_LEVEL, 994 #endif 995 #endif 996 997 } VDEC_EX_V2_User_Cmd; 998 //------------------------------------------------------------------------------------------------- 999 // Structure for Upper layer 1000 //------------------------------------------------------------------------------------------------- 1001 typedef struct DLL_PACKED 1002 { 1003 MS_U32 u32Version; 1004 MS_U32 u32Id; 1005 } VDEC_EX_V2_StreamId; 1006 1007 typedef struct DLL_PACKED 1008 { 1009 VDEC_EX_V2_User_Cmd eUserCmd; 1010 VDEC_EX_V2_StreamId* StreamID; 1011 void* pRet; 1012 void* param[8]; // at most 8 param 1013 }VDEC_EX_V2_IO_Param; 1014 1015 typedef struct 1016 { 1017 VDEC_EX_V2_Stream eStream; 1018 VDEC_EX_V2_CodecType eCodecType; 1019 } VDEC_EX_V2_CodecInfo; 1020 1021 /// Configurations of f/w decode mode 1022 typedef struct 1023 { 1024 VDEC_EX_V2_DEC_MODE eDecMod; 1025 VDEC_EX_V2_CodecInfo pstCodecInfo[VDEC_EX_V2_MAX_DEC_NUM]; 1026 MS_U8 u8CodecCnt; 1027 MS_U8 u8ArgSize; 1028 MS_U32 u32Arg; //ref VDEC_EX_DEC_MODE_ARG enum 1029 } VDEC_EX_V2_DecModCfg; 1030 1031 typedef struct 1032 { 1033 MS_BOOL bEnable; // 0 : disable , 1:enable 1034 MS_U8 u8DisplayTop; // 0: display top, 1: display bottom 1035 }VDEC_EX_V2_Field_Polarity; 1036 1037 typedef struct 1038 { 1039 MS_U32 u32version; 1040 MS_U32 u32size; 1041 } VDEC_EX_V2_VerCtl; 1042 1043 /// Data structure of CC Configuration 1044 typedef struct 1045 { 1046 VDEC_EX_V2_CCFormat eFormat; 1047 VDEC_EX_V2_CCType eType; 1048 MS_VIRT u32BufStAdd; 1049 MS_U32 u32BufSize; 1050 } VDEC_EX_V2_CCCfg; 1051 1052 /// information for display setting 1053 typedef struct 1054 { 1055 ///bitstream horizontal size 1056 MS_U16 u16HorSize; 1057 ///bitstream vertical size 1058 MS_U16 u16VerSize; 1059 ///frame rate 1060 MS_U32 u32FrameRate; 1061 ///interlace flag 1062 MS_U8 u8Interlace; 1063 ///active frame code 1064 MS_U8 u8AFD; 1065 ///Sample aspect rate width 1066 MS_U16 u16SarWidth; 1067 ///Sample aspect rate height 1068 MS_U16 u16SarHeight; 1069 ///right cropping 1070 MS_U16 u16CropRight; 1071 ///left cropping 1072 MS_U16 u16CropLeft; 1073 ///bottom cropping 1074 MS_U16 u16CropBottom; 1075 ///top cropping 1076 MS_U16 u16CropTop; 1077 ///pitch 1078 MS_U16 u16Pitch; 1079 ///interval of PTS 1080 MS_U16 u16PTSInterval; 1081 ///MPEG1 flag 1082 MS_U8 u8MPEG1; 1083 ///play mode (fixme) 1084 MS_U8 u8PlayMode; 1085 ///FRC mode 1086 MS_U8 u8FrcMode; 1087 ///aspect ratio code 1088 MS_U8 u8AspectRate; 1089 ///if FALSE, set VOP as mono mode (only for H264) 1090 MS_BOOL bWithChroma; 1091 /// if true, color space is xvYCC (Y from 16 to 235 and Cb , Cr from 16 to 240). 1092 /// if false, color space is BT.601/709 (Y from 0 to 255 and Cb , Cr from 0 to 255). 1093 /// only MPEG might be with BT.601/709 1094 MS_BOOL bColorInXVYCC; 1095 ///Dynamic scaling buffer address 1096 MS_VIRT u32DynScalingAddr; 1097 ///Dynamic scaling buffer size 1098 MS_U32 u32DynScalingSize; 1099 ///Dynamic scaling depth 1100 MS_U8 u8DynScalingDepth; 1101 ///Dynamic scaling DS buffer on miu1 or miu0 1102 MS_BOOL bEnableMIUSel; 1103 ///Display width 1104 MS_U32 u32AspectWidth; 1105 ///Display height 1106 MS_U32 u32AspectHeight; 1107 } VDEC_EX_V2_DispInfo; 1108 1109 /// system configuration 1110 typedef struct 1111 { 1112 ///FW binary start address 1113 MS_PHY u32FWBinaryAddr; 1114 ///FW binary size 1115 MS_U32 u32FWBinarySize; 1116 ///FW code buffer start address 1117 MS_PHY u32CodeBufAddr; 1118 ///FW code buffer size 1119 MS_U32 u32CodeBufSize; 1120 ///frame buffer start address 1121 MS_PHY u32FrameBufAddr; 1122 ///frame buffer size 1123 MS_U32 u32FrameBufSize; 1124 ///bitstream buffer start address 1125 MS_PHY u32BitstreamBufAddr; 1126 ///bitstream buffer size 1127 MS_U32 u32BitstreamBufSize; 1128 ///driver process buffer start address 1129 MS_PHY u32DrvProcBufAddr; 1130 ///driver process buffer size 1131 MS_U32 u32DrvProcBufSize; 1132 ///vlc table Binary address (RM only) 1133 MS_PHY u32VlcBinarySrcAddr; 1134 ///vld table Binary size 1135 MS_U32 u32VlcTabBinarySize; 1136 ///debug level setting 1137 VDEC_EX_V2_DbgLevel eDbgMsgLevel; 1138 ///debug level setting 1139 VDEC_EX_V2_FWSourceType eFWSourceType; 1140 } VDEC_EX_V2_SysCfg; 1141 1142 /// video information 1143 typedef struct 1144 { 1145 ///input source mode 1146 VDEC_EX_V2_SrcMode eSrcMode; 1147 /// timestamp type of command queue 1148 VDEC_EX_V2_TimeStampType eTimeStampType; 1149 ///MJPEG scale factor 1150 VDEC_EX_V2_MJpegScaleFactor eMJpegScaleFactor; 1151 /// should be TRUE when codec type is H264 and container is MKV and MP4(MOV) 1152 MS_BOOL bWithoutNalStCode; 1153 /// needness when CodecType is MJPEG and divx311 1154 //MS_U16 u16FrameRate; 1155 MS_U32 u32FrameRate; 1156 MS_U32 u32FrameRateBase; 1157 /// if divx311; use u16Width[0]; only need other elements when RV8 1158 MS_U16 u16Width[8]; 1159 /// if divx311; use u16Height[0]; only need other elements when RV8 1160 MS_U16 u16Height[8]; 1161 /// video number sizes (for RM) 1162 MS_U16 u16NumSizes; 1163 } VDEC_EX_V2_VideoInfo; 1164 1165 /// frame information 1166 typedef struct 1167 { 1168 /// frame buffer base + the start offset of current displayed luma data. Unit: byte. 1169 MS_PHY u32LumaAddr; 1170 /// frame buffer base + the start offset of current displayed chroma data. Unit: byte. 1171 MS_PHY u32ChromaAddr; 1172 /// Time stamp(DTS, PTS) of current displayed frame. Unit: ms (todo: 90khz) 1173 MS_U32 u32TimeStamp; 1174 /// low part of ID number 1175 MS_U32 u32ID_L; 1176 /// high part of ID number 1177 MS_U32 u32ID_H; 1178 /// pitch 1179 MS_U16 u16Pitch; 1180 /// width 1181 MS_U16 u16Width; 1182 /// hight 1183 MS_U16 u16Height; 1184 ///< Frame type: I, P, B frame 1185 VDEC_EX_V2_FrameType eFrameType; 1186 ///< Field type: Top, Bottom, Both 1187 VDEC_EX_V2_FieldType eFieldType; 1188 } VDEC_EX_V2_FrameInfo; 1189 1190 typedef struct 1191 { 1192 VDEC_EX_V2_FrameInfo sFrameInfo; 1193 1194 MS_PHY u32LumaAddr_2bit; 1195 MS_PHY u32ChromaAddr_2bit; 1196 MS_U8 u8LumaBitdepth; 1197 MS_U8 u8ChromaBitdepth; 1198 MS_U16 u16Pitch_2bit; 1199 1200 MS_U8 u8Reserved[64]; 1201 } VDEC_EX_V2_FrameInfoEX; 1202 1203 //Extension of frame info(VDEC_EX_FrameInfoEX) 1204 typedef struct 1205 { 1206 VDEC_EX_V2_VerCtl stVerCtl; /// version : 0, 1207 VDEC_EX_V2_FrameInfo sFrameInfo; 1208 MS_PHY u32LumaAddr_2bit; 1209 MS_PHY u32ChromaAddr_2bit; 1210 MS_PHY u32LumaAddrI; 1211 MS_PHY u32LumaAddrI_2bit; 1212 MS_PHY u32ChromaAddrI; 1213 MS_PHY u32ChromaAddrI_2bit; 1214 MS_U32 u32MFCodecInfo; 1215 MS_U32 u32LumaMFCbitlen; 1216 MS_U32 u32ChromaMFCbitlen; 1217 MS_U16 u16Pitch_2bit; 1218 MS_U8 u8LumaBitdepth; 1219 MS_U8 u8ChromaBitdepth; 1220 ////HVD_MasteringDisplayColourVolume// 1221 MS_U32 maxLuminance; 1222 MS_U32 minLuminance; 1223 MS_U16 primaries[3][2]; 1224 MS_U16 whitePoint[2]; 1225 MS_U8 Frm_Info_Ext_avail; ///bit[1]: SEI_Enabled, bit[0]: colur_description_present_flag 1226 ////colour_description//////////// 1227 MS_U8 colour_primaries; // u(8) 1228 MS_U8 transfer_characteristics; // u(8) 1229 MS_U8 matrix_coefficients; // u(8) 1230 } VDEC_EX_V2_FrameInfoExt; 1231 1232 typedef struct 1233 { 1234 MS_BOOL bUsed; 1235 MS_BOOL bColourVolumeSEIEnabled; 1236 MS_U32 u32MaxLuminance; 1237 MS_U32 u32MinLuminance; 1238 MS_U16 u16Primaries[3][2]; 1239 MS_U16 u16WhitePoint[2]; 1240 }VDEC_EX_V2_DisplayColourVolume_SEI; 1241 1242 typedef struct 1243 { 1244 VDEC_EX_V2_FrameInfoExt sFrameInfoExt; 1245 ////HVD_MasteringDisplayColourVolume// 1246 VDEC_EX_V2_DisplayColourVolume_SEI sDisplay_colour_volume; 1247 MS_U8 u8Frm_Info_Ext_avail; ///bit[1]: SEI_Enabled, bit[0]: colur_description_present_flag 1248 ////colour_description//////////// 1249 MS_U8 u8Colour_primaries; // u(8) 1250 MS_U8 u8Transfer_characteristics; // u(8) 1251 MS_U8 u8Matrix_coefficients; // u(8) 1252 } VDEC_EX_V2_FrameInfoExt_v2; 1253 1254 /// Extension display information 1255 typedef struct 1256 { 1257 /// vertical size from sequene_display_extension 1258 MS_U16 u16VSize; 1259 /// horizontal size from sequene_display_extension 1260 MS_U16 u16HSize; 1261 /// vertical offset from picture_display_extension 1262 MS_S16 s16VOffset; 1263 /// horizontal offset from picture_display_extension 1264 MS_S16 s16HOffset; 1265 } VDEC_EX_V2_ExtDispInfo; 1266 1267 /// display frame information 1268 typedef struct 1269 { 1270 ///< frame information 1271 VDEC_EX_V2_FrameInfo stFrmInfo; 1272 ///< firmware private data 1273 MS_U32 u32PriData; 1274 ///< index used by apiVDEC to manage VDEC_DispQ[][] 1275 MS_U32 u32Idx; 1276 } VDEC_EX_V2_DispFrame; 1277 1278 /// time code structure 1279 typedef struct 1280 { 1281 /// time_code_hours 1282 MS_U8 u8TimeCodeHr; 1283 /// time_code_minutes 1284 MS_U8 u8TimeCodeMin; 1285 /// time_code_seconds 1286 MS_U8 u8TimeCodeSec; 1287 /// time_code_pictures 1288 MS_U8 u8TimeCodePic; 1289 /// drop_frame_flag 1290 MS_U8 u8DropFrmFlag; 1291 /// reserved fields for 4-byte alignment 1292 MS_U8 u8Reserved[3]; 1293 } VDEC_EX_V2_TimeCode; 1294 1295 /// vdec frame buffer reduction 1296 typedef struct 1297 { 1298 VDEC_EX_V2_FBReductionType eLumaFBReduction; 1299 VDEC_EX_V2_FBReductionType eChromaFBReduction; 1300 MS_BOOL bEnableAutoMode; /// 0: Disable, 1: Enable 1301 } VDEC_EX_V2_FBReduction; 1302 1303 /// Initial parameter 1304 typedef struct 1305 { 1306 /// init param version : 0 1307 MS_U32 u32Version; 1308 /// codec type 1309 VDEC_EX_V2_CodecType eCodecType; 1310 /// system configuration 1311 VDEC_EX_V2_SysCfg SysConfig; 1312 /// video information from container 1313 VDEC_EX_V2_VideoInfo VideoInfo; 1314 /// dynamic scaling control bit 1315 MS_BOOL EnableDynaScale; 1316 /// switch for display decode error frame or not 1317 MS_BOOL bDisableDropErrFrame; 1318 /// switch for error concealment 1319 MS_BOOL bDisableErrConceal; 1320 /// enable repeat last field when repeat happened at interlace stream 1321 MS_BOOL bRepeatLastField; 1322 /// threshold to judge error frame 1323 MS_U8 u8ErrThreshold; 1324 /// dynamic scaling virtual box Width 1325 MS_U32 u32DSVirtualBoxWidth; 1326 /// dynamic scaling virtual box Height 1327 MS_U32 u32DSVirtualBoxHeight; 1328 /// vdec frame buffer reduction setting 1329 VDEC_EX_V2_FBReduction stFBReduction; 1330 } VDEC_EX_V2_InitParam; 1331 1332 /// Decode Command 1333 typedef struct 1334 { 1335 /// ID (high 4-bytes) 1336 MS_U32 u32ID_H; 1337 /// ID (low 4-bytes) 1338 MS_U32 u32ID_L; 1339 /// start address of payload 1340 MS_VIRT u32StAddr; 1341 /// size of payload 1342 MS_U32 u32Size; 1343 /// timestamp of payload 1344 MS_U32 u32Timestamp; 1345 } VDEC_EX_V2_DecCmd; 1346 1347 /// Display Command 1348 typedef struct 1349 { 1350 /// ID (high 4-bytes) 1351 MS_U32 u32ID_H; 1352 /// ID (low 4-bytes) 1353 MS_U32 u32ID_L; 1354 /// action of command 1355 VDEC_EX_V2_DispCmdAction eAction; 1356 } VDEC_EX_V2_DispCmd; 1357 1358 typedef struct 1359 { 1360 MS_U32 u32Version; 1361 /// top, bottom or frame 1362 VDEC_EX_V2_PicStructure u8PicStructure; 1363 MS_U8 u8TopFieldFirst; 1364 MS_U16 u16TempRef; 1365 MS_U32 u32Pts; 1366 /// address of cc data 1367 MS_U32 u32UserDataBuf; 1368 /// size of cc data 1369 MS_U32 u32UserDataSize; 1370 ///< Frame type: I, P, B frame 1371 VDEC_EX_V2_FrameType eFrameType; 1372 } VDEC_EX_V2_CC_Info; 1373 1374 ///CC input parameters for mstar proprietary CC library 1375 typedef struct 1376 { 1377 MS_U32 u32Ver; ///version of this structure 1378 MS_U32 u32Val; 1379 } VDEC_EX_V2_CC_InputPara; 1380 1381 typedef struct 1382 { 1383 MS_U32 u32OutputFrameRate; ///< output frame rate, unit:vsync count 1384 MS_U8 u8Interlace; ///< output scan:0:progress, 1:interlace 1385 } VDEC_EX_V2_FRC_OutputParam; 1386 1387 1388 typedef void (*VDEC_EX_V2_EventCb)(MS_U32 eFlag, void *param); 1389 1390 typedef struct 1391 { 1392 MS_U8 u8Frm_packing_arr_cnl_flag; 1393 MS_U8 u8Frm_packing_arr_type; 1394 MS_U8 u8content_interpretation_type; 1395 MS_U8 u1Quincunx_sampling_flag; 1396 1397 MS_U8 u1Spatial_flipping_flag; 1398 MS_U8 u1Frame0_flipping_flag; 1399 MS_U8 u1Field_views_flag; 1400 MS_U8 u1Current_frame_is_frame0_flag; 1401 1402 MS_U8 u1Frame0_self_contained_flag; 1403 MS_U8 u1Frame1_self_contained_flag; 1404 MS_U8 u4Frame0_grid_position_x; 1405 MS_U8 u4Frame0_grid_position_y; 1406 1407 MS_U8 u4Frame1_grid_position_x; 1408 MS_U8 u4Frame1_grid_position_y; 1409 MS_U8 u8Reserved01; 1410 MS_U8 u8Reserved02; 1411 }VDEC_EX_V2_Frame_packing_SEI; 1412 1413 typedef struct 1414 { 1415 VDEC_EX_V2_VerCtl stVerCtl; /// version : 0, 1416 /// size : sizeof(VDEC_EX_Frame_packing_SEI_EX) 1417 MS_BOOL bIsCropInfo; 1418 MS_BOOL bValid; 1419 MS_BOOL bUsed; 1420 MS_U8 u8Frm_packing_arr_cnl_flag; 1421 MS_U8 u8Frm_packing_arr_type; 1422 MS_U8 u8content_interpretation_type; 1423 MS_U8 u1Quincunx_sampling_flag; 1424 MS_U8 u1Spatial_flipping_flag; 1425 MS_U8 u1Frame0_flipping_flag; 1426 MS_U8 u1Field_views_flag; 1427 MS_U8 u1Current_frame_is_frame0_flag; 1428 MS_U8 u1Frame0_self_contained_flag; 1429 MS_U8 u1Frame1_self_contained_flag; 1430 MS_U8 u4Frame0_grid_position_x; 1431 MS_U8 u4Frame0_grid_position_y; 1432 MS_U8 u4Frame1_grid_position_x; 1433 MS_U8 u4Frame1_grid_position_y; 1434 MS_U32 u32DataBuff; 1435 MS_U32 u32DataSize; 1436 MS_U32 left; 1437 MS_U32 right; 1438 MS_U32 top; 1439 MS_U32 bottom; 1440 } VDEC_EX_V2_Frame_packing_SEI_EX; 1441 1442 typedef struct 1443 { 1444 MS_BOOL bAspect_ratio_info_present_flag; // u(1) 1445 MS_U8 u8Aspect_ratio_idc; // u(8) 1446 MS_U16 u16Sar_width; // u(16) 1447 MS_U16 u16Sar_height; // u(16) 1448 MS_BOOL bOverscan_info_present_flag; // u(1) 1449 MS_BOOL bOverscan_appropriate_flag; // u(1) 1450 MS_BOOL bVideo_signal_type_present_flag; // u(1) 1451 MS_U8 u8Video_format; // u(3) 1452 MS_BOOL bVideo_full_range_flag; // u(1) 1453 MS_BOOL bColour_description_present_flag; // u(1) 1454 MS_U8 u8Colour_primaries; // u(8) 1455 MS_U8 u8Transfer_characteristics; // u(8) 1456 MS_U8 u8Matrix_coefficients; // u(8) 1457 MS_BOOL bChroma_location_info_present_flag; // u(1) 1458 MS_U8 u8Chroma_sample_loc_type_top_field; // ue(v) 0~5 1459 MS_U8 u8Chroma_sample_loc_type_bottom_field; // ue(v) 0~5 1460 MS_BOOL bTiming_info_present_flag; // u(1) 1461 MS_BOOL bFixed_frame_rate_flag; // u(1) 1462 MS_U32 u32Num_units_in_tick; // u(32) 1463 MS_U32 u32Time_scale; // u(32) 1464 } VDEC_EX_V2_AVC_VUI_DISP_INFO; 1465 1466 //CRC value 1467 typedef struct 1468 { 1469 MS_U32 u32HorSize; 1470 MS_U32 u32VerSize; 1471 MS_U32 u32Strip; 1472 MS_VIRT u32LumaStartAddr; 1473 MS_VIRT u32ChromaStartAddr; 1474 }VDEC_EX_V2_CrcIn; 1475 1476 typedef struct 1477 { 1478 MS_U32 u32LumaCRC; 1479 MS_U32 u32ChromaCRC; 1480 }VDEC_EX_V2_CrcOut; 1481 1482 typedef struct 1483 { 1484 VDEC_EX_V2_CrcIn stCrcIn; 1485 VDEC_EX_V2_CrcOut stCrcOut; 1486 }VDEC_EX_V2_CrcValue; 1487 1488 typedef struct 1489 { 1490 VDEC_EX_V2_CodecType eCodecType; 1491 MS_PHY u32DataAddr; 1492 MS_U32 u32MemUsageSize; 1493 MS_U16 u16DataSize; 1494 } VDEC_EX_V2_FbMemUsage_Param; 1495 1496 //------------------------------------------------------------------------------------------------- 1497 // Function pointer for Upper layer 1498 //------------------------------------------------------------------------------------------------- 1499 1500 //------------------------------------------------------------------------------------------------- 1501 // API for Upper layer 1502 //------------------------------------------------------------------------------------------------- 1503 1504 void VDEC_EX_V2_RegisterToUtopia(FUtopiaOpen ModuleType); 1505 MS_U32 VDEC_EX_V2_Open(void** ppInstance, const void* const pAttribute); 1506 MS_U32 VDEC_EX_V2_Close(void* pInstance); 1507 MS_U32 VDEC_EX_V2_IOctl(void* pInstance, MS_U32 u32Cmd, void* pArgs); 1508 MS_U32 VDEC_EXStr(MS_U32 u32PowerState, void* pModule); 1509 1510 1511 #ifdef __cplusplus 1512 } 1513 #endif 1514 1515 #endif 1516 #undef _VDEC_EX_V2_H_ 1517 #endif //_VDEC_EX_V2_H_ 1518