1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. 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If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 79 #ifndef _LPLL_EXT_TBL_H_ 80 #define _LPLL_EXT_TBL_H_ 81 82 #define LPLL_EXT_REG_NUM 17 83 84 typedef enum 85 { 86 E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_115to150MHz, //0 87 E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_57to115MHz, //1 88 E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_25to57MHz, //2 89 90 E_PNL_SUPPORTED_LPLL_EXT_VBY1_4CH_10BIT_150to340MHz, //3 91 92 E_PNL_SUPPORTED_LPLL_EXT_VBY1_2CH_10BIT_75to150MHz, //4 93 94 E_PNL_SUPPORTED_LPLL_EXT_VBY1_1CH_10BIT_37_5to75MHz, //5 95 96 E_PNL_SUPPORTED_LPLL_EXT_VBY1_4CH_8BIT_220to340MHz, //6 97 E_PNL_SUPPORTED_LPLL_EXT_VBY1_4CH_8BIT_150to220MHz, //7 98 99 E_PNL_SUPPORTED_LPLL_EXT_VBY1_2CH_8BIT_110to150MHz, //8 100 E_PNL_SUPPORTED_LPLL_EXT_VBY1_2CH_8BIT_75to110MHz, //9 101 102 E_PNL_SUPPORTED_LPLL_EXT_VBY1_1CH_8BIT_55to75MHz, //10 103 E_PNL_SUPPORTED_LPLL_EXT_VBY1_1CH_8BIT_37_5to55MHz, //11 104 105 E_PNL_SUPPORTED_LPLL_EXT_MAX, //12 106 } E_PNL_SUPPORTED_LPLL_EXT_TYPE; 107 108 typedef struct 109 { 110 MS_U8 address; 111 MS_U16 value; 112 MS_U16 mask; 113 }TBLStruct_Ext,*pTBLStruct_Ext; 114 115 TBLStruct_Ext LPLLSettingTBL_Ext[E_PNL_SUPPORTED_LPLL_EXT_MAX][LPLL_EXT_REG_NUM]= 116 { 117 { //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_115to150MHz NO.0 118 //Address,Value,Mask 119 {0x40,0x0000,0x8000},//reg_lpll_ext_pd 120 {0x40,0x0001,0x0007},//reg_lpll_ext_ictrl 121 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 122 {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst 123 {0x41,0x0300,0x0F00},//reg_lpll_ext_loop_div_sec 124 {0x42,0x0000,0x0003},//reg_lpll_ext_scalar_div_fst 125 {0x42,0x0070,0x00F0},//reg_lpll_ext_scalar_div_sec 126 {0x43,0x0000,0x0007},//reg_lpll_ext_skew_div 127 {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div 128 {0x43,0x0010,0x0010},//reg_lpll_ext_skew_en_fixclk 129 {0x40,0x0000,0x0800},//reg_lpll_ext_dual_lp_en 130 {0x40,0x0000,0x0100},//reg_lpll_ext_sdiv2p5_en 131 {0x40,0x2000,0x2000},//reg_lpll_ext_en_mini 132 {0x40,0x0000,0x0400},//reg_lpll_ext_en_fifo 133 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 134 {0x40,0x0000,0x1000},//reg_lpll_ext_fifo_div5_en 135 {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en 136 }, 137 138 { //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_57to115MHz NO.1 139 //Address,Value,Mask 140 {0x40,0x0000,0x8000},//reg_lpll_ext_pd 141 {0x40,0x0001,0x0007},//reg_lpll_ext_ictrl 142 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 143 {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst 144 {0x41,0x0300,0x0F00},//reg_lpll_ext_loop_div_sec 145 {0x42,0x0001,0x0003},//reg_lpll_ext_scalar_div_fst 146 {0x42,0x0070,0x00F0},//reg_lpll_ext_scalar_div_sec 147 {0x43,0x0001,0x0007},//reg_lpll_ext_skew_div 148 {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div 149 {0x43,0x0010,0x0010},//reg_lpll_ext_skew_en_fixclk 150 {0x40,0x0000,0x0800},//reg_lpll_ext_dual_lp_en 151 {0x40,0x0000,0x0100},//reg_lpll_ext_sdiv2p5_en 152 {0x40,0x2000,0x2000},//reg_lpll_ext_en_mini 153 {0x40,0x0000,0x0400},//reg_lpll_ext_en_fifo 154 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 155 {0x40,0x0000,0x1000},//reg_lpll_ext_fifo_div5_en 156 {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en 157 }, 158 159 { //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_25to57MHz NO.2 160 //Address,Value,Mask 161 {0x40,0x0000,0x8000},//reg_lpll_ext_pd 162 {0x40,0x0001,0x0007},//reg_lpll_ext_ictrl 163 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 164 {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst 165 {0x41,0x0300,0x0F00},//reg_lpll_ext_loop_div_sec 166 {0x42,0x0002,0x0003},//reg_lpll_ext_scalar_div_fst 167 {0x42,0x0070,0x00F0},//reg_lpll_ext_scalar_div_sec 168 {0x43,0x0002,0x0007},//reg_lpll_ext_skew_div 169 {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div 170 {0x43,0x0010,0x0010},//reg_lpll_ext_skew_en_fixclk 171 {0x40,0x0000,0x0800},//reg_lpll_ext_dual_lp_en 172 {0x40,0x0000,0x0100},//reg_lpll_ext_sdiv2p5_en 173 {0x40,0x2000,0x2000},//reg_lpll_ext_en_mini 174 {0x40,0x0000,0x0400},//reg_lpll_ext_en_fifo 175 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 176 {0x40,0x0000,0x1000},//reg_lpll_ext_fifo_div5_en 177 {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en 178 }, 179 180 { //E_PNL_SUPPORTED_LPLL_EXT_VBY1_4CH_10BIT_150to340MHz NO.3 181 //Address,Value,Mask 182 {0x40,0x0000,0x8000},//reg_lpll_ext_pd 183 {0x40,0x0002,0x0007},//reg_lpll_ext_ictrl 184 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 185 {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst 186 {0x41,0x0500,0x0F00},//reg_lpll_ext_loop_div_sec 187 {0x42,0x0002,0x0003},//reg_lpll_ext_scalar_div_fst 188 {0x42,0x0000,0x00F0},//reg_lpll_ext_scalar_div_sec 189 {0x43,0x0000,0x0007},//reg_lpll_ext_skew_div 190 {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div 191 {0x43,0x0000,0x0010},//reg_lpll_ext_skew_en_fixclk 192 {0x40,0x0800,0x0800},//reg_lpll_ext_dual_lp_en 193 {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en 194 {0x40,0x0000,0x2000},//reg_lpll_ext_en_mini 195 {0x40,0x0400,0x0400},//reg_lpll_ext_en_fifo 196 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 197 {0x40,0x1000,0x1000},//reg_lpll_ext_fifo_div5_en 198 {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en 199 }, 200 201 { //E_PNL_SUPPORTED_LPLL_EXT_VBY1_2CH_10BIT_75to150MHz NO.4 202 //Address,Value,Mask 203 {0x40,0x0000,0x8000},//reg_lpll_ext_pd 204 {0x40,0x0002,0x0007},//reg_lpll_ext_ictrl 205 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 206 {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst 207 {0x41,0x0500,0x0F00},//reg_lpll_ext_loop_div_sec 208 {0x42,0x0002,0x0003},//reg_lpll_ext_scalar_div_fst 209 {0x42,0x0020,0x00F0},//reg_lpll_ext_scalar_div_sec 210 {0x43,0x0000,0x0007},//reg_lpll_ext_skew_div 211 {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div 212 {0x43,0x0000,0x0010},//reg_lpll_ext_skew_en_fixclk 213 {0x40,0x0800,0x0800},//reg_lpll_ext_dual_lp_en 214 {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en 215 {0x40,0x0000,0x2000},//reg_lpll_ext_en_mini 216 {0x40,0x0400,0x0400},//reg_lpll_ext_en_fifo 217 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 218 {0x40,0x1000,0x1000},//reg_lpll_ext_fifo_div5_en 219 {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en 220 }, 221 222 { //E_PNL_SUPPORTED_LPLL_EXT_VBY1_1CH_10BIT_37_5to75MHz NO.5 223 //Address,Value,Mask 224 {0x40,0x0000,0x8000},//reg_lpll_ext_pd 225 {0x40,0x0002,0x0007},//reg_lpll_ext_ictrl 226 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 227 {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst 228 {0x41,0x0500,0x0F00},//reg_lpll_ext_loop_div_sec 229 {0x42,0x0003,0x0003},//reg_lpll_ext_scalar_div_fst 230 {0x42,0x0020,0x00F0},//reg_lpll_ext_scalar_div_sec 231 {0x43,0x0000,0x0007},//reg_lpll_ext_skew_div 232 {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div 233 {0x43,0x0000,0x0010},//reg_lpll_ext_skew_en_fixclk 234 {0x40,0x0800,0x0800},//reg_lpll_ext_dual_lp_en 235 {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en 236 {0x40,0x0000,0x2000},//reg_lpll_ext_en_mini 237 {0x40,0x0400,0x0400},//reg_lpll_ext_en_fifo 238 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 239 {0x40,0x1000,0x1000},//reg_lpll_ext_fifo_div5_en 240 {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en 241 }, 242 243 { //E_PNL_SUPPORTED_LPLL_EXT_VBY1_4CH_8BIT_220to340MHz NO.6 244 //Address,Value,Mask 245 {0x40,0x0000,0x8000},//reg_lpll_ext_pd 246 {0x40,0x0002,0x0007},//reg_lpll_ext_ictrl 247 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 248 {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst 249 {0x41,0x0500,0x0F00},//reg_lpll_ext_loop_div_sec 250 {0x42,0x0000,0x0003},//reg_lpll_ext_scalar_div_fst 251 {0x42,0x0030,0x00F0},//reg_lpll_ext_scalar_div_sec 252 {0x43,0x0000,0x0007},//reg_lpll_ext_skew_div 253 {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div 254 {0x43,0x0000,0x0010},//reg_lpll_ext_skew_en_fixclk 255 {0x40,0x0800,0x0800},//reg_lpll_ext_dual_lp_en 256 {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en 257 {0x40,0x0000,0x2000},//reg_lpll_ext_en_mini 258 {0x40,0x0400,0x0400},//reg_lpll_ext_en_fifo 259 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 260 {0x40,0x1000,0x1000},//reg_lpll_ext_fifo_div5_en 261 {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en 262 }, 263 264 { //E_PNL_SUPPORTED_LPLL_EXT_VBY1_4CH_8BIT_150to220MHz NO.7 265 //Address,Value,Mask 266 {0x40,0x0000,0x8000},//reg_lpll_ext_pd 267 {0x40,0x0002,0x0007},//reg_lpll_ext_ictrl 268 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 269 {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst 270 {0x41,0x0500,0x0F00},//reg_lpll_ext_loop_div_sec 271 {0x42,0x0001,0x0003},//reg_lpll_ext_scalar_div_fst 272 {0x42,0x0030,0x00F0},//reg_lpll_ext_scalar_div_sec 273 {0x43,0x0000,0x0007},//reg_lpll_ext_skew_div 274 {0x42,0x0400,0x0700},//reg_lpll_ext_fifo_div 275 {0x43,0x0000,0x0010},//reg_lpll_ext_skew_en_fixclk 276 {0x40,0x0800,0x0800},//reg_lpll_ext_dual_lp_en 277 {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en 278 {0x40,0x0000,0x2000},//reg_lpll_ext_en_mini 279 {0x40,0x0400,0x0400},//reg_lpll_ext_en_fifo 280 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 281 {0x40,0x1000,0x1000},//reg_lpll_ext_fifo_div5_en 282 {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en 283 }, 284 285 { //E_PNL_SUPPORTED_LPLL_EXT_VBY1_2CH_8BIT_110to150MHz NO.8 286 //Address,Value,Mask 287 {0x40,0x0000,0x8000},//reg_lpll_ext_pd 288 {0x40,0x0002,0x0007},//reg_lpll_ext_ictrl 289 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 290 {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst 291 {0x41,0x0500,0x0F00},//reg_lpll_ext_loop_div_sec 292 {0x42,0x0001,0x0003},//reg_lpll_ext_scalar_div_fst 293 {0x42,0x0030,0x00F0},//reg_lpll_ext_scalar_div_sec 294 {0x43,0x0000,0x0007},//reg_lpll_ext_skew_div 295 {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div 296 {0x43,0x0000,0x0010},//reg_lpll_ext_skew_en_fixclk 297 {0x40,0x0800,0x0800},//reg_lpll_ext_dual_lp_en 298 {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en 299 {0x40,0x0000,0x2000},//reg_lpll_ext_en_mini 300 {0x40,0x0400,0x0400},//reg_lpll_ext_en_fifo 301 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 302 {0x40,0x1000,0x1000},//reg_lpll_ext_fifo_div5_en 303 {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en 304 }, 305 306 { //E_PNL_SUPPORTED_LPLL_EXT_VBY1_2CH_8BIT_75to110MHz NO.9 307 //Address,Value,Mask 308 {0x40,0x0000,0x8000},//reg_lpll_ext_pd 309 {0x40,0x0002,0x0007},//reg_lpll_ext_ictrl 310 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 311 {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst 312 {0x41,0x0500,0x0F00},//reg_lpll_ext_loop_div_sec 313 {0x42,0x0002,0x0003},//reg_lpll_ext_scalar_div_fst 314 {0x42,0x0030,0x00F0},//reg_lpll_ext_scalar_div_sec 315 {0x43,0x0001,0x0007},//reg_lpll_ext_skew_div 316 {0x42,0x0400,0x0700},//reg_lpll_ext_fifo_div 317 {0x43,0x0000,0x0010},//reg_lpll_ext_skew_en_fixclk 318 {0x40,0x0800,0x0800},//reg_lpll_ext_dual_lp_en 319 {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en 320 {0x40,0x0000,0x2000},//reg_lpll_ext_en_mini 321 {0x40,0x0400,0x0400},//reg_lpll_ext_en_fifo 322 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 323 {0x40,0x1000,0x1000},//reg_lpll_ext_fifo_div5_en 324 {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en 325 }, 326 327 { //E_PNL_SUPPORTED_LPLL_EXT_VBY1_1CH_8BIT_55to75MHz NO.10 328 //Address,Value,Mask 329 {0x40,0x0000,0x8000},//reg_lpll_ext_pd 330 {0x40,0x0002,0x0007},//reg_lpll_ext_ictrl 331 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 332 {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst 333 {0x41,0x0500,0x0F00},//reg_lpll_ext_loop_div_sec 334 {0x42,0x0002,0x0003},//reg_lpll_ext_scalar_div_fst 335 {0x42,0x0030,0x00F0},//reg_lpll_ext_scalar_div_sec 336 {0x43,0x0000,0x0007},//reg_lpll_ext_skew_div 337 {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div 338 {0x43,0x0000,0x0010},//reg_lpll_ext_skew_en_fixclk 339 {0x40,0x0800,0x0800},//reg_lpll_ext_dual_lp_en 340 {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en 341 {0x40,0x0000,0x2000},//reg_lpll_ext_en_mini 342 {0x40,0x0400,0x0400},//reg_lpll_ext_en_fifo 343 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 344 {0x40,0x1000,0x1000},//reg_lpll_ext_fifo_div5_en 345 {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en 346 }, 347 348 { //E_PNL_SUPPORTED_LPLL_EXT_VBY1_1CH_8BIT_37_5to55MHz NO.11 349 //Address,Value,Mask 350 {0x40,0x0000,0x8000},//reg_lpll_ext_pd 351 {0x40,0x0002,0x0007},//reg_lpll_ext_ictrl 352 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 353 {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst 354 {0x41,0x0500,0x0F00},//reg_lpll_ext_loop_div_sec 355 {0x42,0x0003,0x0003},//reg_lpll_ext_scalar_div_fst 356 {0x42,0x0030,0x00F0},//reg_lpll_ext_scalar_div_sec 357 {0x43,0x0001,0x0007},//reg_lpll_ext_skew_div 358 {0x42,0x0400,0x0700},//reg_lpll_ext_fifo_div 359 {0x43,0x0000,0x0010},//reg_lpll_ext_skew_en_fixclk 360 {0x40,0x0800,0x0800},//reg_lpll_ext_dual_lp_en 361 {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en 362 {0x40,0x0000,0x2000},//reg_lpll_ext_en_mini 363 {0x40,0x0400,0x0400},//reg_lpll_ext_en_fifo 364 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 365 {0x40,0x1000,0x1000},//reg_lpll_ext_fifo_div5_en 366 {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en 367 }, 368 369 }; 370 MS_U16 u16EXT_LoopGain[E_PNL_SUPPORTED_LPLL_EXT_MAX]= 371 { 372 12, //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_115to150MHz NO.0 373 6, //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_57to115MHz NO.1 374 3, //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_25to57MHz NO.2 375 2, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_4CH_10BIT_150to340MHz NO.3 376 1, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_2CH_10BIT_75to150MHz NO.4 377 1, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_1CH_10BIT_37_5to75MHz NO.5 378 8, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_4CH_8BIT_220to340MHz NO.6 379 4, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_4CH_8BIT_150to220MHz NO.7 380 4, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_2CH_8BIT_110to150MHz NO.8 381 2, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_2CH_8BIT_75to110MHz NO.9 382 2, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_1CH_8BIT_55to75MHz NO.10 383 1, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_1CH_8BIT_37_5to55MHz NO.11 384 }; 385 MS_U16 u16EXT_LoopDiv[E_PNL_SUPPORTED_LPLL_EXT_MAX]= 386 { 387 7, //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_115to150MHz NO.0 388 7, //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_57to115MHz NO.1 389 7, //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_25to57MHz NO.2 390 1, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_4CH_10BIT_150to340MHz NO.3 391 1, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_2CH_10BIT_75to150MHz NO.4 392 2, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_1CH_10BIT_37_5to75MHz NO.5 393 3, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_4CH_8BIT_220to340MHz NO.6 394 3, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_4CH_8BIT_150to220MHz NO.7 395 3, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_2CH_8BIT_110to150MHz NO.8 396 3, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_2CH_8BIT_75to110MHz NO.9 397 3, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_1CH_8BIT_55to75MHz NO.10 398 3, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_1CH_8BIT_37_5to55MHz NO.11 399 }; 400 401 #endif //_LPLL_TBL_H_ 402