1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. 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If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 79 #ifndef _LPLL_TBL_H_ 80 #define _LPLL_TBL_H_ 81 82 #define LPLL_REG_NUM 41 83 84 typedef enum 85 { 86 E_PNL_SUPPORTED_LPLL_TTL_100to150MHz, //0 87 E_PNL_SUPPORTED_LPLL_TTL_50to100MHz, //1 88 E_PNL_SUPPORTED_LPLL_TTL_25to50MHz, //2 89 E_PNL_SUPPORTED_LPLL_TTL_25to25MHz, //3 90 91 E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to80MHz, //4 92 E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to50MHz, //5 93 94 E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to75MHz, //6 95 E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to50MHz, //7 96 E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to25MHz, //8 97 98 E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_100to150MHz, //9 99 E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to100MHz, //10 100 E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to50MHz, //11 101 102 E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_100to150MHz, //12 103 E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_50to100MHz, //13 104 E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to50MHz, //14 105 E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to25MHz, //15 106 107 E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_16PAIR_V17_150to300MHz, //16 108 E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_16PAIR_V17_150to150MHz, //17 109 110 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_16PAIR_V17_200to300MHz, //18 111 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_16PAIR_V17_200to200MHz, //19 112 113 E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12PAIR_V17_150to300MHz, //20 114 E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12PAIR_V17_150to150MHz, //21 115 116 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12PAIR_V17_150to300MHz, //22 117 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12PAIR_V17_150to150MHz, //23 118 119 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_EPI3G_V17_180to300MHz, //24 120 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_EPI3G_V17_150to180MHz, //25 121 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_EPI3G_V17_150to150MHz, //26 122 123 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_EPI3G_V17_240to300MHz, //27 124 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_EPI3G_V17_150to240MHz, //28 125 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_EPI3G_V17_150to150MHz, //29 126 127 E_PNL_SUPPORTED_LPLL_CMPI_24_10BIT_12PAIR_X1_150to300MHz, //30 128 E_PNL_SUPPORTED_LPLL_CMPI_24_10BIT_12PAIR_X1_150to150MHz, //31 129 130 E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_12PAIR_X1_150to300MHz, //32 131 E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_12PAIR_X1_150to150MHz, //33 132 133 E_PNL_SUPPORTED_LPLL_USI_T_10BIT_12PAIR_150to300MHz, //34 134 E_PNL_SUPPORTED_LPLL_USI_T_10BIT_12PAIR_150to150MHz, //35 135 136 E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12PAIR_150to300MHz, //36 137 E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12PAIR_150to150MHz, //37 138 139 E_PNL_SUPPORTED_LPLL_ISP_10BIT_12PAIR_150to300MHz, //38 140 E_PNL_SUPPORTED_LPLL_ISP_10BIT_12PAIR_150to150MHz, //39 141 142 E_PNL_SUPPORTED_LPLL_ISP_8BIT_12PAIR_150to300MHz, //40 143 E_PNL_SUPPORTED_LPLL_ISP_8BIT_12PAIR_150to150MHz, //41 144 145 E_PNL_SUPPORTED_LPLL_ISP_10BIT_8PAIR_199_2to300MHz, //42 146 E_PNL_SUPPORTED_LPLL_ISP_10BIT_8PAIR_150to199_2MHz, //43 147 E_PNL_SUPPORTED_LPLL_ISP_10BIT_8PAIR_150to150MHz, //44 148 149 E_PNL_SUPPORTED_LPLL_ISP_8BIT_8PAIR_249to300MHz, //45 150 E_PNL_SUPPORTED_LPLL_ISP_8BIT_8PAIR_150to249MHz, //46 151 E_PNL_SUPPORTED_LPLL_ISP_8BIT_8PAIR_150to150MHz, //47 152 153 E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_150to300MHz, //48 154 E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_150to150MHz, //49 155 156 E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to150MHz, //50 157 E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to75MHz, //51 158 159 E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_37_5to75MHz, //52 160 E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_37_5to37_5MHz, //53 161 162 E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_200to300MHz, //54 163 E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_150to200MHz, //55 164 E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_150to150MHz, //56 165 166 E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_100to150MHz, //57 167 E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to100MHz, //58 168 E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to75MHz, //59 169 170 E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_50to75MHz, //60 171 E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_37_5to50MHz, //61 172 E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_37_5to37_5MHz, //62 173 174 E_PNL_SUPPORTED_LPLL_MAX, //63 175 } E_PNL_SUPPORTED_LPLL_TYPE; 176 177 typedef struct 178 { 179 MS_U8 address; 180 MS_U16 value; 181 MS_U16 mask; 182 }TBLStruct,*pTBLStruct; 183 184 TBLStruct LPLLSettingTBL[E_PNL_SUPPORTED_LPLL_MAX][LPLL_REG_NUM]= 185 { 186 { //E_PNL_SUPPORTED_LPLL_TTL_100to150MHz NO.0 187 //Address,Value,Mask 188 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 189 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 190 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 191 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 192 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 193 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 194 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 195 {0x02,0x0200,0x0F00},//reg_lpll1_output_div_second[11:8] 196 {0x35,0x7000,0x7000},//reg_lpll1_skew_div 197 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 198 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 199 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 200 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 201 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 202 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 203 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 204 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 205 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 206 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 207 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 208 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 209 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 210 {0x33,0x0020,0x0020},//reg_lpll2_pd 211 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 212 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 213 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 214 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 215 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 216 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 217 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 218 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 219 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 220 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 221 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 222 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 223 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 224 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 225 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 226 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 227 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 228 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 229 }, 230 231 { //E_PNL_SUPPORTED_LPLL_TTL_50to100MHz NO.1 232 //Address,Value,Mask 233 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 234 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 235 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 236 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 237 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 238 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 239 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 240 {0x02,0x0400,0x0F00},//reg_lpll1_output_div_second[11:8] 241 {0x35,0x7000,0x7000},//reg_lpll1_skew_div 242 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 243 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 244 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 245 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 246 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 247 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 248 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 249 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 250 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 251 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 252 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 253 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 254 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 255 {0x33,0x0020,0x0020},//reg_lpll2_pd 256 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 257 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 258 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 259 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 260 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 261 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 262 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 263 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 264 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 265 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 266 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 267 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 268 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 269 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 270 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 271 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 272 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 273 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 274 }, 275 276 { //E_PNL_SUPPORTED_LPLL_TTL_25to50MHz NO.2 277 //Address,Value,Mask 278 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 279 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 280 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 281 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 282 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 283 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 284 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 285 {0x02,0x0800,0x0F00},//reg_lpll1_output_div_second[11:8] 286 {0x35,0x7000,0x7000},//reg_lpll1_skew_div 287 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 288 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 289 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 290 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 291 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 292 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 293 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 294 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 295 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 296 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 297 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 298 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 299 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 300 {0x33,0x0020,0x0020},//reg_lpll2_pd 301 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 302 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 303 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 304 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 305 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 306 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 307 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 308 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 309 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 310 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 311 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 312 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 313 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 314 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 315 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 316 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 317 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 318 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 319 }, 320 321 { //E_PNL_SUPPORTED_LPLL_TTL_25to25MHz NO.3 322 //Address,Value,Mask 323 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 324 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 325 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 326 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 327 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 328 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 329 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 330 {0x02,0x0800,0x0F00},//reg_lpll1_output_div_second[11:8] 331 {0x35,0x7000,0x7000},//reg_lpll1_skew_div 332 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 333 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 334 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 335 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 336 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 337 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 338 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 339 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 340 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 341 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 342 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 343 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 344 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 345 {0x33,0x0020,0x0020},//reg_lpll2_pd 346 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 347 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 348 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 349 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 350 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 351 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 352 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 353 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 354 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 355 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 356 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 357 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 358 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 359 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 360 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 361 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 362 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 363 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 364 }, 365 366 { //E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to80MHz NO.4 367 //Address,Value,Mask 368 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 369 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 370 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 371 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 372 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 373 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 374 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 375 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 376 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 377 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 378 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 379 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 380 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 381 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 382 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 383 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 384 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 385 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 386 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 387 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 388 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 389 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 390 {0x33,0x0020,0x0020},//reg_lpll2_pd 391 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 392 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 393 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 394 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 395 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 396 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 397 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 398 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 399 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 400 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 401 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 402 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 403 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 404 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 405 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 406 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 407 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 408 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 409 }, 410 411 { //E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to50MHz NO.5 412 //Address,Value,Mask 413 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 414 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 415 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 416 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 417 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 418 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 419 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 420 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 421 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 422 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 423 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 424 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 425 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 426 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 427 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 428 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 429 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 430 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 431 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 432 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 433 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 434 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 435 {0x33,0x0020,0x0020},//reg_lpll2_pd 436 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 437 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 438 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 439 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 440 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 441 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 442 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 443 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 444 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 445 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 446 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 447 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 448 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 449 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 450 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 451 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 452 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 453 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 454 }, 455 456 { //E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to75MHz NO.6 457 //Address,Value,Mask 458 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 459 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 460 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 461 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 462 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 463 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 464 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 465 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 466 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 467 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 468 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 469 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 470 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 471 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 472 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 473 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 474 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 475 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 476 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 477 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 478 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 479 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 480 {0x33,0x0020,0x0020},//reg_lpll2_pd 481 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 482 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 483 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 484 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 485 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 486 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 487 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 488 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 489 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 490 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 491 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 492 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 493 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 494 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 495 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 496 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 497 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 498 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 499 }, 500 501 { //E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to50MHz NO.7 502 //Address,Value,Mask 503 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 504 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 505 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 506 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 507 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 508 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 509 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 510 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 511 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 512 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 513 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 514 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 515 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 516 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 517 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 518 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 519 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 520 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 521 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 522 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 523 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 524 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 525 {0x33,0x0020,0x0020},//reg_lpll2_pd 526 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 527 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 528 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 529 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 530 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 531 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 532 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 533 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 534 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 535 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 536 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 537 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 538 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 539 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 540 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 541 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 542 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 543 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 544 }, 545 546 { //E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to25MHz NO.8 547 //Address,Value,Mask 548 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 549 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 550 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 551 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 552 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 553 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 554 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 555 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 556 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 557 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 558 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 559 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 560 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 561 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 562 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 563 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 564 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 565 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 566 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 567 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 568 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 569 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 570 {0x33,0x0020,0x0020},//reg_lpll2_pd 571 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 572 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 573 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 574 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 575 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 576 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 577 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 578 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 579 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 580 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 581 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 582 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 583 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 584 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 585 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 586 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 587 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 588 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 589 }, 590 591 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_100to150MHz NO.9 592 //Address,Value,Mask 593 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 594 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 595 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 596 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 597 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 598 {0x02,0x0000,0x3000},//reg_lpll1_output_div_second[13:12] 599 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 600 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 601 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 602 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 603 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 604 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 605 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 606 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 607 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 608 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 609 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 610 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 611 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 612 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 613 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 614 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 615 {0x33,0x0020,0x0020},//reg_lpll2_pd 616 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 617 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 618 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 619 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 620 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 621 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 622 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 623 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 624 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 625 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 626 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 627 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 628 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 629 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 630 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 631 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 632 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 633 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 634 }, 635 636 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to100MHz NO.10 637 //Address,Value,Mask 638 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 639 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 640 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 641 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 642 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 643 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 644 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 645 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 646 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 647 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 648 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 649 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 650 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 651 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 652 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 653 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 654 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 655 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 656 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 657 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 658 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 659 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 660 {0x33,0x0020,0x0020},//reg_lpll2_pd 661 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 662 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 663 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 664 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 665 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 666 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 667 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 668 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 669 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 670 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 671 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 672 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 673 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 674 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 675 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 676 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 677 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 678 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 679 }, 680 681 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to50MHz NO.11 682 //Address,Value,Mask 683 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 684 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 685 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 686 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 687 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 688 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 689 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 690 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 691 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 692 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 693 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 694 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 695 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 696 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 697 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 698 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 699 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 700 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 701 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 702 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 703 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 704 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 705 {0x33,0x0020,0x0020},//reg_lpll2_pd 706 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 707 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 708 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 709 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 710 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 711 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 712 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 713 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 714 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 715 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 716 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 717 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 718 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 719 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 720 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 721 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 722 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 723 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 724 }, 725 726 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_100to150MHz NO.12 727 //Address,Value,Mask 728 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 729 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 730 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 731 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 732 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 733 {0x02,0x0000,0x3000},//reg_lpll1_output_div_second[13:12] 734 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 735 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 736 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 737 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 738 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 739 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 740 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 741 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 742 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 743 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 744 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 745 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 746 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 747 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 748 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 749 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 750 {0x33,0x0020,0x0020},//reg_lpll2_pd 751 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 752 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 753 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 754 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 755 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 756 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 757 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 758 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 759 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 760 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 761 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 762 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 763 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 764 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 765 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 766 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 767 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 768 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 769 }, 770 771 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_50to100MHz NO.13 772 //Address,Value,Mask 773 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 774 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 775 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 776 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 777 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 778 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 779 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 780 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 781 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 782 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 783 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 784 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 785 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 786 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 787 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 788 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 789 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 790 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 791 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 792 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 793 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 794 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 795 {0x33,0x0020,0x0020},//reg_lpll2_pd 796 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 797 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 798 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 799 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 800 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 801 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 802 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 803 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 804 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 805 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 806 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 807 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 808 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 809 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 810 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 811 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 812 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 813 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 814 }, 815 816 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to50MHz NO.14 817 //Address,Value,Mask 818 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 819 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 820 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 821 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 822 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 823 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 824 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 825 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 826 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 827 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 828 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 829 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 830 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 831 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 832 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 833 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 834 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 835 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 836 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 837 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 838 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 839 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 840 {0x33,0x0020,0x0020},//reg_lpll2_pd 841 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 842 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 843 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 844 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 845 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 846 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 847 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 848 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 849 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 850 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 851 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 852 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 853 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 854 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 855 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 856 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 857 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 858 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 859 }, 860 861 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to25MHz NO.15 862 //Address,Value,Mask 863 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 864 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 865 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 866 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 867 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 868 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 869 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 870 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 871 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 872 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 873 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 874 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 875 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 876 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 877 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 878 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 879 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 880 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 881 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 882 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 883 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 884 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 885 {0x33,0x0020,0x0020},//reg_lpll2_pd 886 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 887 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 888 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 889 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 890 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 891 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 892 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 893 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 894 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 895 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 896 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 897 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 898 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 899 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 900 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 901 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 902 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 903 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 904 }, 905 906 { //E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_16PAIR_V17_150to300MHz NO.16 907 //Address,Value,Mask 908 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 909 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 910 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 911 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 912 {0x01,0x0900,0x1F00},//reg_lpll1_loop_div_second 913 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 914 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 915 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 916 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 917 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 918 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 919 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 920 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 921 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 922 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 923 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 924 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 925 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 926 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 927 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 928 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 929 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 930 {0x33,0x0000,0x0020},//reg_lpll2_pd 931 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 932 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 933 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 934 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 935 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 936 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 937 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 938 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 939 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 940 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 941 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 942 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 943 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 944 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 945 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 946 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 947 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 948 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 949 }, 950 951 { //E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_16PAIR_V17_150to150MHz NO.17 952 //Address,Value,Mask 953 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 954 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 955 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 956 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 957 {0x01,0x0900,0x1F00},//reg_lpll1_loop_div_second 958 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 959 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 960 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 961 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 962 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 963 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 964 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 965 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 966 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 967 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 968 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 969 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 970 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 971 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 972 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 973 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 974 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 975 {0x33,0x0000,0x0020},//reg_lpll2_pd 976 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 977 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 978 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 979 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 980 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 981 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 982 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 983 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 984 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 985 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 986 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 987 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 988 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 989 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 990 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 991 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 992 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 993 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 994 }, 995 996 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_16PAIR_V17_200to300MHz NO.18 997 //Address,Value,Mask 998 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 999 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1000 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1001 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1002 {0x01,0x0700,0x1F00},//reg_lpll1_loop_div_second 1003 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1004 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1005 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1006 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1007 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1008 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1009 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1010 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1011 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1012 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1013 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1014 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1015 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1016 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1017 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1018 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1019 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1020 {0x33,0x0000,0x0020},//reg_lpll2_pd 1021 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1022 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1023 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1024 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1025 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1026 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1027 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1028 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1029 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1030 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1031 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1032 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1033 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1034 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1035 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1036 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1037 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1038 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1039 }, 1040 1041 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_16PAIR_V17_200to200MHz NO.19 1042 //Address,Value,Mask 1043 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1044 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1045 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1046 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1047 {0x01,0x0700,0x1F00},//reg_lpll1_loop_div_second 1048 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1049 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1050 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1051 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1052 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1053 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1054 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1055 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1056 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1057 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1058 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1059 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1060 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1061 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1062 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1063 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1064 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1065 {0x33,0x0000,0x0020},//reg_lpll2_pd 1066 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1067 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1068 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1069 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1070 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1071 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1072 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1073 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1074 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1075 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1076 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1077 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1078 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1079 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1080 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1081 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1082 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1083 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1084 }, 1085 1086 { //E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12PAIR_V17_150to300MHz NO.20 1087 //Address,Value,Mask 1088 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1089 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1090 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1091 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1092 {0x01,0x0900,0x1F00},//reg_lpll1_loop_div_second 1093 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1094 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1095 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1096 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1097 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1098 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1099 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1100 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1101 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1102 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1103 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1104 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1105 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1106 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1107 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1108 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1109 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1110 {0x33,0x0000,0x0020},//reg_lpll2_pd 1111 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1112 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1113 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1114 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1115 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1116 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1117 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1118 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1119 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1120 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1121 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1122 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1123 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1124 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1125 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1126 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1127 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1128 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1129 }, 1130 1131 { //E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12PAIR_V17_150to150MHz NO.21 1132 //Address,Value,Mask 1133 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1134 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1135 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1136 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1137 {0x01,0x0900,0x1F00},//reg_lpll1_loop_div_second 1138 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1139 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1140 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1141 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1142 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1143 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1144 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1145 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1146 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1147 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1148 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1149 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1150 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1151 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1152 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1153 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1154 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1155 {0x33,0x0000,0x0020},//reg_lpll2_pd 1156 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1157 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1158 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1159 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1160 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1161 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1162 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1163 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1164 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1165 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1166 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1167 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1168 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1169 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1170 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1171 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1172 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1173 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1174 }, 1175 1176 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12PAIR_V17_150to300MHz NO.22 1177 //Address,Value,Mask 1178 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1179 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1180 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1181 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1182 {0x01,0x0700,0x1F00},//reg_lpll1_loop_div_second 1183 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1184 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1185 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1186 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1187 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1188 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1189 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1190 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1191 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1192 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1193 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1194 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1195 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1196 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1197 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1198 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1199 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1200 {0x33,0x0000,0x0020},//reg_lpll2_pd 1201 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1202 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1203 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1204 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1205 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1206 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1207 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1208 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1209 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1210 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1211 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1212 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1213 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1214 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1215 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1216 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1217 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1218 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1219 }, 1220 1221 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12PAIR_V17_150to150MHz NO.23 1222 //Address,Value,Mask 1223 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1224 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1225 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1226 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1227 {0x01,0x0700,0x1F00},//reg_lpll1_loop_div_second 1228 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1229 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1230 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1231 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1232 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1233 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1234 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1235 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1236 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1237 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1238 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1239 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1240 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1241 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1242 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1243 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1244 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1245 {0x33,0x0000,0x0020},//reg_lpll2_pd 1246 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1247 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1248 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1249 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1250 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1251 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1252 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1253 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1254 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1255 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1256 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1257 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1258 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1259 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1260 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1261 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1262 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1263 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1264 }, 1265 1266 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_EPI3G_V17_180to300MHz NO.24 1267 //Address,Value,Mask 1268 {0x03,0x0014,0x001C},//reg_lpll1_ibias_ictrl 1269 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1270 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1271 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1272 {0x01,0x0700,0x1F00},//reg_lpll1_loop_div_second 1273 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1274 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1275 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1276 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1277 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1278 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1279 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1280 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1281 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1282 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1283 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1284 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1285 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1286 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1287 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1288 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1289 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1290 {0x33,0x0000,0x0020},//reg_lpll2_pd 1291 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1292 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1293 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1294 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1295 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1296 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1297 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1298 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1299 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1300 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1301 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1302 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1303 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1304 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1305 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1306 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1307 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1308 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1309 }, 1310 1311 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_EPI3G_V17_150to180MHz NO.25 1312 //Address,Value,Mask 1313 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 1314 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1315 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1316 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1317 {0x01,0x0700,0x1F00},//reg_lpll1_loop_div_second 1318 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1319 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1320 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1321 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1322 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1323 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1324 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1325 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1326 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1327 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1328 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1329 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1330 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1331 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1332 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1333 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1334 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1335 {0x33,0x0000,0x0020},//reg_lpll2_pd 1336 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1337 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1338 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1339 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1340 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1341 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1342 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1343 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1344 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1345 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1346 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1347 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1348 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1349 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1350 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1351 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1352 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1353 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1354 }, 1355 1356 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_EPI3G_V17_150to150MHz NO.26 1357 //Address,Value,Mask 1358 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 1359 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1360 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1361 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1362 {0x01,0x0700,0x1F00},//reg_lpll1_loop_div_second 1363 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1364 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1365 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1366 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1367 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1368 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1369 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1370 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1371 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1372 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1373 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1374 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1375 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1376 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1377 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1378 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1379 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1380 {0x33,0x0000,0x0020},//reg_lpll2_pd 1381 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1382 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1383 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1384 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1385 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1386 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1387 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1388 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1389 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1390 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1391 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1392 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1393 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1394 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1395 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1396 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1397 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1398 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1399 }, 1400 1401 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_EPI3G_V17_240to300MHz NO.27 1402 //Address,Value,Mask 1403 {0x03,0x0008,0x001C},//reg_lpll1_ibias_ictrl 1404 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1405 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1406 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1407 {0x01,0x0700,0x1F00},//reg_lpll1_loop_div_second 1408 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1409 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1410 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1411 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1412 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1413 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1414 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1415 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1416 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1417 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1418 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1419 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1420 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1421 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1422 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1423 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1424 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1425 {0x33,0x0000,0x0020},//reg_lpll2_pd 1426 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1427 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1428 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1429 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1430 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1431 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1432 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1433 {0x39,0x0800,0x0800},//reg_lpll2_test[11] 1434 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1435 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1436 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1437 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1438 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1439 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1440 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1441 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1442 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1443 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1444 }, 1445 1446 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_EPI3G_V17_150to240MHz NO.28 1447 //Address,Value,Mask 1448 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1449 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1450 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1451 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1452 {0x01,0x0700,0x1F00},//reg_lpll1_loop_div_second 1453 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1454 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1455 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1456 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1457 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1458 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1459 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1460 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1461 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1462 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1463 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1464 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1465 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1466 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1467 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1468 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1469 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1470 {0x33,0x0000,0x0020},//reg_lpll2_pd 1471 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1472 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1473 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1474 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1475 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1476 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1477 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1478 {0x39,0x0800,0x0800},//reg_lpll2_test[11] 1479 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1480 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1481 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1482 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1483 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1484 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1485 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1486 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1487 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1488 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1489 }, 1490 1491 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_EPI3G_V17_150to150MHz NO.29 1492 //Address,Value,Mask 1493 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1494 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1495 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1496 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1497 {0x01,0x0700,0x1F00},//reg_lpll1_loop_div_second 1498 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1499 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1500 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1501 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1502 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1503 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1504 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1505 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1506 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1507 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1508 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1509 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1510 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1511 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1512 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1513 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1514 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1515 {0x33,0x0000,0x0020},//reg_lpll2_pd 1516 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1517 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1518 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1519 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1520 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1521 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1522 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1523 {0x39,0x0800,0x0800},//reg_lpll2_test[11] 1524 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1525 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1526 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1527 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1528 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1529 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1530 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1531 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1532 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1533 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1534 }, 1535 1536 { //E_PNL_SUPPORTED_LPLL_CMPI_24_10BIT_12PAIR_X1_150to300MHz NO.30 1537 //Address,Value,Mask 1538 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1539 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1540 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1541 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1542 {0x01,0x0900,0x1F00},//reg_lpll1_loop_div_second 1543 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1544 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1545 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1546 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1547 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1548 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1549 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1550 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1551 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1552 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1553 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1554 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1555 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1556 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1557 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1558 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1559 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1560 {0x33,0x0000,0x0020},//reg_lpll2_pd 1561 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1562 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1563 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1564 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1565 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1566 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1567 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1568 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1569 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1570 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1571 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1572 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1573 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1574 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1575 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1576 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1577 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1578 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1579 }, 1580 1581 { //E_PNL_SUPPORTED_LPLL_CMPI_24_10BIT_12PAIR_X1_150to150MHz NO.31 1582 //Address,Value,Mask 1583 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1584 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1585 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1586 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1587 {0x01,0x0900,0x1F00},//reg_lpll1_loop_div_second 1588 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1589 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1590 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1591 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1592 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1593 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1594 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1595 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1596 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1597 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1598 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1599 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1600 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1601 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1602 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1603 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1604 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1605 {0x33,0x0000,0x0020},//reg_lpll2_pd 1606 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1607 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1608 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1609 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1610 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1611 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1612 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1613 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1614 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1615 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1616 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1617 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1618 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1619 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1620 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1621 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1622 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1623 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1624 }, 1625 1626 { //E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_12PAIR_X1_150to300MHz NO.32 1627 //Address,Value,Mask 1628 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1629 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1630 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1631 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1632 {0x01,0x0900,0x1F00},//reg_lpll1_loop_div_second 1633 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1634 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1635 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1636 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1637 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1638 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1639 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1640 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1641 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1642 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1643 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1644 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1645 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1646 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1647 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1648 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1649 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1650 {0x33,0x0000,0x0020},//reg_lpll2_pd 1651 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1652 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1653 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1654 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1655 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1656 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1657 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1658 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1659 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1660 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1661 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1662 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1663 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1664 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1665 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1666 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1667 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1668 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1669 }, 1670 1671 { //E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_12PAIR_X1_150to150MHz NO.33 1672 //Address,Value,Mask 1673 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1674 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1675 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1676 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1677 {0x01,0x0900,0x1F00},//reg_lpll1_loop_div_second 1678 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1679 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1680 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1681 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1682 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1683 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1684 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1685 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1686 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1687 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1688 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1689 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1690 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1691 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1692 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1693 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1694 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1695 {0x33,0x0000,0x0020},//reg_lpll2_pd 1696 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1697 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1698 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1699 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1700 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1701 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1702 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1703 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1704 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1705 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1706 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1707 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1708 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1709 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1710 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1711 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1712 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1713 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1714 }, 1715 1716 { //E_PNL_SUPPORTED_LPLL_USI_T_10BIT_12PAIR_150to300MHz NO.34 1717 //Address,Value,Mask 1718 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1719 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1720 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1721 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1722 {0x01,0x0400,0x1F00},//reg_lpll1_loop_div_second 1723 {0x02,0x0000,0x3000},//reg_lpll1_output_div_second[13:12] 1724 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1725 {0x02,0x0500,0x0F00},//reg_lpll1_output_div_second[11:8] 1726 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1727 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1728 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 1729 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1730 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1731 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1732 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1733 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1734 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1735 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1736 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 1737 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1738 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1739 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1740 {0x33,0x0000,0x0020},//reg_lpll2_pd 1741 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1742 {0x33,0x0004,0x0004},//reg_lpll2_ibias_ictrl 1743 {0x30,0x0005,0x001F},//reg_lpll2_input_div_first 1744 {0x31,0x0001,0x0003},//reg_lpll2_loop_div_first 1745 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1746 {0x31,0x0900,0x1F00},//reg_lpll2_loop_div_second 1747 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1748 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1749 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1750 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1751 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1752 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1753 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1754 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1755 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1756 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1757 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1758 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1759 }, 1760 1761 { //E_PNL_SUPPORTED_LPLL_USI_T_10BIT_12PAIR_150to150MHz NO.35 1762 //Address,Value,Mask 1763 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1764 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1765 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1766 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1767 {0x01,0x0400,0x1F00},//reg_lpll1_loop_div_second 1768 {0x02,0x0000,0x3000},//reg_lpll1_output_div_second[13:12] 1769 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1770 {0x02,0x0500,0x0F00},//reg_lpll1_output_div_second[11:8] 1771 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1772 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1773 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 1774 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1775 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1776 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1777 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1778 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1779 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1780 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1781 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 1782 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1783 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1784 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1785 {0x33,0x0000,0x0020},//reg_lpll2_pd 1786 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1787 {0x33,0x0004,0x0004},//reg_lpll2_ibias_ictrl 1788 {0x30,0x0005,0x001F},//reg_lpll2_input_div_first 1789 {0x31,0x0001,0x0003},//reg_lpll2_loop_div_first 1790 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1791 {0x31,0x0900,0x1F00},//reg_lpll2_loop_div_second 1792 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1793 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1794 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1795 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1796 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1797 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1798 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1799 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1800 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1801 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1802 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1803 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1804 }, 1805 1806 { //E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12PAIR_150to300MHz NO.36 1807 //Address,Value,Mask 1808 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1809 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1810 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1811 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1812 {0x01,0x0500,0x1F00},//reg_lpll1_loop_div_second 1813 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1814 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1815 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1816 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1817 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1818 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 1819 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1820 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1821 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1822 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1823 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1824 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1825 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1826 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1827 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1828 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1829 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1830 {0x33,0x0000,0x0020},//reg_lpll2_pd 1831 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1832 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1833 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1834 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1835 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1836 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1837 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1838 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1839 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1840 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1841 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1842 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1843 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1844 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1845 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1846 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1847 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1848 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1849 }, 1850 1851 { //E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12PAIR_150to150MHz NO.37 1852 //Address,Value,Mask 1853 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1854 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1855 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1856 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1857 {0x01,0x0500,0x1F00},//reg_lpll1_loop_div_second 1858 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1859 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1860 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1861 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1862 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1863 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 1864 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1865 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1866 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1867 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1868 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1869 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1870 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1871 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1872 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1873 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1874 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1875 {0x33,0x0000,0x0020},//reg_lpll2_pd 1876 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1877 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1878 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1879 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1880 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1881 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1882 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1883 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1884 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1885 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1886 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1887 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1888 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1889 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1890 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1891 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1892 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1893 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1894 }, 1895 1896 { //E_PNL_SUPPORTED_LPLL_ISP_10BIT_12PAIR_150to300MHz NO.38 1897 //Address,Value,Mask 1898 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1899 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1900 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1901 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1902 {0x01,0x0900,0x1F00},//reg_lpll1_loop_div_second 1903 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1904 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1905 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1906 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1907 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 1908 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1909 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1910 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1911 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1912 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1913 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1914 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1915 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1916 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1917 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1918 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1919 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1920 {0x33,0x0000,0x0020},//reg_lpll2_pd 1921 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1922 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1923 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1924 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1925 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1926 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1927 {0x32,0x0005,0x000F},//reg_lpll2_output_div_first 1928 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1929 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1930 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1931 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1932 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1933 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1934 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1935 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1936 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1937 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1938 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1939 }, 1940 1941 { //E_PNL_SUPPORTED_LPLL_ISP_10BIT_12PAIR_150to150MHz NO.39 1942 //Address,Value,Mask 1943 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1944 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1945 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1946 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1947 {0x01,0x0900,0x1F00},//reg_lpll1_loop_div_second 1948 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1949 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1950 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1951 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1952 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 1953 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1954 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1955 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1956 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1957 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1958 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1959 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1960 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1961 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1962 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1963 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1964 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1965 {0x33,0x0000,0x0020},//reg_lpll2_pd 1966 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1967 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1968 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1969 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1970 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1971 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1972 {0x32,0x0005,0x000F},//reg_lpll2_output_div_first 1973 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1974 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1975 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1976 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1977 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1978 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1979 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1980 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1981 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1982 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1983 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1984 }, 1985 1986 { //E_PNL_SUPPORTED_LPLL_ISP_8BIT_12PAIR_150to300MHz NO.40 1987 //Address,Value,Mask 1988 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1989 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1990 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1991 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1992 {0x01,0x0900,0x1F00},//reg_lpll1_loop_div_second 1993 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1994 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1995 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1996 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1997 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1998 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1999 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2000 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2001 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2002 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2003 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2004 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2005 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2006 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 2007 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2008 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2009 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2010 {0x33,0x0000,0x0020},//reg_lpll2_pd 2011 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2012 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2013 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2014 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 2015 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2016 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2017 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 2018 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2019 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2020 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 2021 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2022 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2023 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2024 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2025 {0x38,0x0200,0x0200},//reg_lpll1_scalar2fifo_en 2026 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2027 {0x38,0x0100,0x0100},//reg_lpll1_scalar2fifo_div2 2028 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2029 }, 2030 2031 { //E_PNL_SUPPORTED_LPLL_ISP_8BIT_12PAIR_150to150MHz NO.41 2032 //Address,Value,Mask 2033 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2034 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2035 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 2036 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2037 {0x01,0x0900,0x1F00},//reg_lpll1_loop_div_second 2038 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2039 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2040 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 2041 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2042 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2043 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2044 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2045 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2046 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2047 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2048 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2049 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2050 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2051 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 2052 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2053 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2054 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2055 {0x33,0x0000,0x0020},//reg_lpll2_pd 2056 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2057 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2058 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2059 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 2060 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2061 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2062 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 2063 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2064 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2065 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 2066 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2067 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2068 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2069 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2070 {0x38,0x0200,0x0200},//reg_lpll1_scalar2fifo_en 2071 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2072 {0x38,0x0100,0x0100},//reg_lpll1_scalar2fifo_div2 2073 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2074 }, 2075 2076 { //E_PNL_SUPPORTED_LPLL_ISP_10BIT_8PAIR_199_2to300MHz NO.42 2077 //Address,Value,Mask 2078 {0x03,0x0010,0x001C},//reg_lpll1_ibias_ictrl 2079 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2080 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 2081 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2082 {0x01,0x0F00,0x1F00},//reg_lpll1_loop_div_second 2083 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2084 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2085 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 2086 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2087 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 2088 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2089 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2090 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2091 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 2092 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2093 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 2094 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2095 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2096 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 2097 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2098 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2099 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2100 {0x33,0x0000,0x0020},//reg_lpll2_pd 2101 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2102 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2103 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2104 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 2105 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2106 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2107 {0x32,0x000E,0x000F},//reg_lpll2_output_div_first 2108 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2109 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2110 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 2111 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2112 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2113 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2114 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2115 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2116 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2117 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2118 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2119 }, 2120 2121 { //E_PNL_SUPPORTED_LPLL_ISP_10BIT_8PAIR_150to199_2MHz NO.43 2122 //Address,Value,Mask 2123 {0x03,0x0008,0x001C},//reg_lpll1_ibias_ictrl 2124 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2125 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 2126 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2127 {0x01,0x0F00,0x1F00},//reg_lpll1_loop_div_second 2128 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2129 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2130 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 2131 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2132 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 2133 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2134 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2135 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2136 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2137 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2138 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2139 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2140 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2141 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 2142 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2143 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2144 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2145 {0x33,0x0000,0x0020},//reg_lpll2_pd 2146 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2147 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2148 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2149 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 2150 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2151 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2152 {0x32,0x000E,0x000F},//reg_lpll2_output_div_first 2153 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2154 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2155 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 2156 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2157 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2158 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2159 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2160 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2161 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2162 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2163 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2164 }, 2165 2166 { //E_PNL_SUPPORTED_LPLL_ISP_10BIT_8PAIR_150to150MHz NO.44 2167 //Address,Value,Mask 2168 {0x03,0x0008,0x001C},//reg_lpll1_ibias_ictrl 2169 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2170 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 2171 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2172 {0x01,0x0F00,0x1F00},//reg_lpll1_loop_div_second 2173 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2174 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2175 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 2176 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2177 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 2178 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2179 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2180 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2181 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2182 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2183 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2184 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2185 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2186 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 2187 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2188 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2189 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2190 {0x33,0x0000,0x0020},//reg_lpll2_pd 2191 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2192 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2193 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2194 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 2195 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2196 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2197 {0x32,0x000E,0x000F},//reg_lpll2_output_div_first 2198 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2199 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2200 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 2201 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2202 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2203 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2204 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2205 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2206 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2207 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2208 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2209 }, 2210 2211 { //E_PNL_SUPPORTED_LPLL_ISP_8BIT_8PAIR_249to300MHz NO.45 2212 //Address,Value,Mask 2213 {0x03,0x0008,0x001C},//reg_lpll1_ibias_ictrl 2214 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2215 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 2216 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2217 {0x01,0x0900,0x1F00},//reg_lpll1_loop_div_second 2218 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2219 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2220 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 2221 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2222 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 2223 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2224 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2225 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2226 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 2227 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2228 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 2229 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2230 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2231 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 2232 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2233 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2234 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2235 {0x33,0x0000,0x0020},//reg_lpll2_pd 2236 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2237 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2238 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2239 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 2240 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2241 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2242 {0x32,0x0008,0x000F},//reg_lpll2_output_div_first 2243 {0x39,0x0800,0x0800},//reg_lpll2_test[11] 2244 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2245 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 2246 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2247 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2248 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2249 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2250 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2251 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2252 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2253 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2254 }, 2255 2256 { //E_PNL_SUPPORTED_LPLL_ISP_8BIT_8PAIR_150to249MHz NO.46 2257 //Address,Value,Mask 2258 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2259 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2260 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 2261 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2262 {0x01,0x0900,0x1F00},//reg_lpll1_loop_div_second 2263 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2264 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2265 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 2266 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2267 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 2268 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2269 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2270 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2271 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2272 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2273 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2274 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2275 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2276 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 2277 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2278 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2279 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2280 {0x33,0x0000,0x0020},//reg_lpll2_pd 2281 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2282 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2283 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2284 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 2285 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2286 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2287 {0x32,0x000E,0x000F},//reg_lpll2_output_div_first 2288 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2289 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2290 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2291 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2292 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 2293 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2294 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2295 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2296 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2297 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2298 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2299 }, 2300 2301 { //E_PNL_SUPPORTED_LPLL_ISP_8BIT_8PAIR_150to150MHz NO.47 2302 //Address,Value,Mask 2303 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2304 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2305 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 2306 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2307 {0x01,0x0900,0x1F00},//reg_lpll1_loop_div_second 2308 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2309 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2310 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 2311 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2312 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 2313 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2314 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2315 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2316 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2317 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2318 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2319 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2320 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2321 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 2322 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2323 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2324 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2325 {0x33,0x0000,0x0020},//reg_lpll2_pd 2326 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2327 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2328 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2329 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 2330 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2331 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2332 {0x32,0x000E,0x000F},//reg_lpll2_output_div_first 2333 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2334 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2335 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2336 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2337 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 2338 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2339 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2340 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2341 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2342 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2343 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2344 }, 2345 2346 { //E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_150to300MHz NO.48 2347 //Address,Value,Mask 2348 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 2349 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2350 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 2351 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2352 {0x01,0x0400,0x1F00},//reg_lpll1_loop_div_second 2353 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2354 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2355 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 2356 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2357 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2358 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 2359 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 2360 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2361 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 2362 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 2363 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 2364 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2365 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2366 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 2367 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2368 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2369 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2370 {0x33,0x0020,0x0020},//reg_lpll2_pd 2371 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2372 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2373 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2374 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 2375 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2376 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2377 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 2378 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2379 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2380 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2381 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2382 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2383 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 2384 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2385 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2386 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2387 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2388 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2389 }, 2390 2391 { //E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_150to150MHz NO.49 2392 //Address,Value,Mask 2393 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 2394 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2395 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 2396 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2397 {0x01,0x0400,0x1F00},//reg_lpll1_loop_div_second 2398 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2399 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2400 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 2401 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2402 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2403 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 2404 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 2405 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2406 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 2407 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 2408 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 2409 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2410 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2411 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 2412 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2413 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2414 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2415 {0x33,0x0020,0x0020},//reg_lpll2_pd 2416 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2417 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2418 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2419 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 2420 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2421 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2422 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 2423 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2424 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2425 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2426 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2427 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2428 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 2429 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2430 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2431 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2432 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2433 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2434 }, 2435 2436 { //E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to150MHz NO.50 2437 //Address,Value,Mask 2438 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 2439 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2440 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 2441 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2442 {0x01,0x0400,0x1F00},//reg_lpll1_loop_div_second 2443 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2444 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2445 {0x02,0x0200,0x0F00},//reg_lpll1_output_div_second[11:8] 2446 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2447 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2448 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 2449 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 2450 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2451 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 2452 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 2453 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 2454 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2455 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2456 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 2457 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2458 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2459 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2460 {0x33,0x0020,0x0020},//reg_lpll2_pd 2461 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2462 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2463 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2464 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 2465 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2466 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2467 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 2468 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2469 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2470 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2471 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2472 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2473 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 2474 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2475 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2476 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2477 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2478 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2479 }, 2480 2481 { //E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to75MHz NO.51 2482 //Address,Value,Mask 2483 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 2484 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2485 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 2486 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2487 {0x01,0x0400,0x1F00},//reg_lpll1_loop_div_second 2488 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2489 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2490 {0x02,0x0200,0x0F00},//reg_lpll1_output_div_second[11:8] 2491 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2492 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2493 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 2494 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 2495 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2496 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 2497 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 2498 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 2499 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2500 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2501 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 2502 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2503 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2504 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2505 {0x33,0x0020,0x0020},//reg_lpll2_pd 2506 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2507 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2508 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2509 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 2510 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2511 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2512 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 2513 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2514 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2515 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2516 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2517 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2518 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 2519 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2520 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2521 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2522 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2523 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2524 }, 2525 2526 { //E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_37_5to75MHz NO.52 2527 //Address,Value,Mask 2528 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 2529 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2530 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 2531 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2532 {0x01,0x0400,0x1F00},//reg_lpll1_loop_div_second 2533 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[13:12] 2534 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2535 {0x02,0x0200,0x0F00},//reg_lpll1_output_div_second[11:8] 2536 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2537 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2538 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 2539 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 2540 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2541 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 2542 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 2543 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 2544 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2545 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2546 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 2547 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2548 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2549 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2550 {0x33,0x0020,0x0020},//reg_lpll2_pd 2551 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2552 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2553 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2554 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 2555 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2556 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2557 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 2558 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2559 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2560 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2561 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2562 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2563 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 2564 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2565 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2566 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2567 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2568 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2569 }, 2570 2571 { //E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_37_5to37_5MHz NO.53 2572 //Address,Value,Mask 2573 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 2574 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2575 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 2576 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2577 {0x01,0x0400,0x1F00},//reg_lpll1_loop_div_second 2578 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[13:12] 2579 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2580 {0x02,0x0200,0x0F00},//reg_lpll1_output_div_second[11:8] 2581 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2582 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2583 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 2584 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 2585 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2586 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 2587 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 2588 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 2589 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2590 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2591 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 2592 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2593 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2594 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2595 {0x33,0x0020,0x0020},//reg_lpll2_pd 2596 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2597 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2598 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2599 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 2600 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2601 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2602 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 2603 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2604 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2605 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2606 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2607 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2608 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 2609 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2610 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2611 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2612 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2613 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2614 }, 2615 2616 { //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_200to300MHz NO.54 2617 //Address,Value,Mask 2618 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 2619 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2620 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 2621 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2622 {0x01,0x0400,0x1F00},//reg_lpll1_loop_div_second 2623 {0x02,0x0000,0x3000},//reg_lpll1_output_div_second[13:12] 2624 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2625 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 2626 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2627 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2628 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 2629 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 2630 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2631 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 2632 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 2633 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 2634 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2635 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2636 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 2637 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2638 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2639 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2640 {0x33,0x0020,0x0020},//reg_lpll2_pd 2641 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2642 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2643 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2644 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 2645 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2646 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2647 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 2648 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2649 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2650 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2651 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2652 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2653 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 2654 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2655 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2656 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2657 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2658 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2659 }, 2660 2661 { //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_150to200MHz NO.55 2662 //Address,Value,Mask 2663 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 2664 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2665 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 2666 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2667 {0x01,0x0400,0x1F00},//reg_lpll1_loop_div_second 2668 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 2669 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2670 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 2671 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 2672 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 2673 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 2674 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 2675 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2676 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 2677 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 2678 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 2679 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2680 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2681 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 2682 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2683 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2684 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2685 {0x33,0x0020,0x0020},//reg_lpll2_pd 2686 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2687 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2688 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2689 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 2690 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2691 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2692 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 2693 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2694 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2695 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2696 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2697 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2698 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 2699 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2700 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2701 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2702 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2703 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2704 }, 2705 2706 { //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_150to150MHz NO.56 2707 //Address,Value,Mask 2708 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 2709 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2710 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 2711 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2712 {0x01,0x0400,0x1F00},//reg_lpll1_loop_div_second 2713 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 2714 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2715 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 2716 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 2717 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 2718 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 2719 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 2720 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2721 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 2722 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 2723 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 2724 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2725 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2726 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 2727 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2728 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2729 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2730 {0x33,0x0020,0x0020},//reg_lpll2_pd 2731 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2732 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2733 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2734 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 2735 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2736 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2737 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 2738 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2739 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2740 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2741 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2742 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2743 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 2744 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2745 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2746 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2747 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2748 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2749 }, 2750 2751 { //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_100to150MHz NO.57 2752 //Address,Value,Mask 2753 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 2754 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2755 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 2756 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2757 {0x01,0x0400,0x1F00},//reg_lpll1_loop_div_second 2758 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 2759 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2760 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 2761 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2762 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2763 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 2764 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 2765 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2766 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 2767 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 2768 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 2769 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2770 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2771 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 2772 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2773 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2774 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2775 {0x33,0x0020,0x0020},//reg_lpll2_pd 2776 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2777 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2778 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2779 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 2780 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2781 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2782 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 2783 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2784 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2785 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2786 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2787 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2788 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 2789 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2790 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2791 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2792 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2793 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2794 }, 2795 2796 { //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to100MHz NO.58 2797 //Address,Value,Mask 2798 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 2799 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2800 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 2801 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2802 {0x01,0x0400,0x1F00},//reg_lpll1_loop_div_second 2803 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2804 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2805 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 2806 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 2807 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 2808 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 2809 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 2810 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2811 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 2812 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 2813 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 2814 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2815 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2816 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 2817 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2818 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2819 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2820 {0x33,0x0020,0x0020},//reg_lpll2_pd 2821 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2822 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2823 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2824 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 2825 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2826 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2827 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 2828 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2829 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2830 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2831 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2832 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2833 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 2834 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2835 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2836 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2837 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2838 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2839 }, 2840 2841 { //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to75MHz NO.59 2842 //Address,Value,Mask 2843 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 2844 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2845 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 2846 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2847 {0x01,0x0400,0x1F00},//reg_lpll1_loop_div_second 2848 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2849 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2850 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 2851 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 2852 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 2853 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 2854 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 2855 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2856 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 2857 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 2858 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 2859 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2860 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2861 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 2862 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2863 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2864 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2865 {0x33,0x0020,0x0020},//reg_lpll2_pd 2866 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2867 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2868 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2869 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 2870 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2871 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2872 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 2873 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2874 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2875 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2876 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2877 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2878 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 2879 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2880 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2881 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2882 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2883 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2884 }, 2885 2886 { //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_50to75MHz NO.60 2887 //Address,Value,Mask 2888 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 2889 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2890 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 2891 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2892 {0x01,0x0400,0x1F00},//reg_lpll1_loop_div_second 2893 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2894 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2895 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 2896 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2897 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2898 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 2899 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 2900 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2901 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 2902 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 2903 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 2904 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2905 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2906 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 2907 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2908 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2909 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2910 {0x33,0x0020,0x0020},//reg_lpll2_pd 2911 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2912 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2913 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2914 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 2915 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2916 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2917 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 2918 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2919 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2920 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2921 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2922 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2923 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 2924 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2925 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2926 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2927 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2928 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2929 }, 2930 2931 { //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_37_5to50MHz NO.61 2932 //Address,Value,Mask 2933 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 2934 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2935 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 2936 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2937 {0x01,0x0400,0x1F00},//reg_lpll1_loop_div_second 2938 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[13:12] 2939 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2940 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 2941 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 2942 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 2943 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 2944 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 2945 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2946 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 2947 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 2948 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 2949 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2950 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2951 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 2952 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2953 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2954 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2955 {0x33,0x0020,0x0020},//reg_lpll2_pd 2956 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2957 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2958 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2959 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 2960 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2961 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2962 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 2963 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2964 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2965 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2966 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2967 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2968 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 2969 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2970 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2971 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2972 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2973 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2974 }, 2975 2976 { //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_37_5to37_5MHz NO.62 2977 //Address,Value,Mask 2978 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 2979 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2980 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 2981 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2982 {0x01,0x0400,0x1F00},//reg_lpll1_loop_div_second 2983 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[13:12] 2984 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2985 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 2986 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 2987 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 2988 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 2989 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 2990 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2991 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 2992 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 2993 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 2994 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2995 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2996 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 2997 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2998 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2999 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 3000 {0x33,0x0020,0x0020},//reg_lpll2_pd 3001 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 3002 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 3003 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 3004 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 3005 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 3006 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 3007 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 3008 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 3009 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 3010 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 3011 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 3012 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 3013 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 3014 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 3015 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 3016 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 3017 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 3018 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 3019 }, 3020 3021 }; 3022 MS_U16 u16LoopGain[E_PNL_SUPPORTED_LPLL_MAX]= 3023 { 3024 12, //E_PNL_SUPPORTED_LPLL_TTL_100to150MHz NO.0 3025 12, //E_PNL_SUPPORTED_LPLL_TTL_50to100MHz NO.1 3026 12, //E_PNL_SUPPORTED_LPLL_TTL_25to50MHz NO.2 3027 12, //E_PNL_SUPPORTED_LPLL_TTL_25to25MHz NO.3 3028 12, //E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to80MHz NO.4 3029 12, //E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to50MHz NO.5 3030 12, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to75MHz NO.6 3031 12, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to50MHz NO.7 3032 12, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to25MHz NO.8 3033 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_100to150MHz NO.9 3034 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to100MHz NO.10 3035 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to50MHz NO.11 3036 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_100to150MHz NO.12 3037 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_50to100MHz NO.13 3038 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to50MHz NO.14 3039 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to25MHz NO.15 3040 8, //E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_16PAIR_V17_150to300MHz NO.16 3041 8, //E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_16PAIR_V17_150to150MHz NO.17 3042 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_16PAIR_V17_200to300MHz NO.18 3043 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_16PAIR_V17_200to200MHz NO.19 3044 8, //E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12PAIR_V17_150to300MHz NO.20 3045 8, //E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12PAIR_V17_150to150MHz NO.21 3046 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12PAIR_V17_150to300MHz NO.22 3047 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12PAIR_V17_150to150MHz NO.23 3048 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_EPI3G_V17_180to300MHz NO.24 3049 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_EPI3G_V17_150to180MHz NO.25 3050 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_EPI3G_V17_150to150MHz NO.26 3051 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_EPI3G_V17_240to300MHz NO.27 3052 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_EPI3G_V17_150to240MHz NO.28 3053 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_EPI3G_V17_150to150MHz NO.29 3054 8, //E_PNL_SUPPORTED_LPLL_CMPI_24_10BIT_12PAIR_X1_150to300MHz NO.30 3055 8, //E_PNL_SUPPORTED_LPLL_CMPI_24_10BIT_12PAIR_X1_150to150MHz NO.31 3056 8, //E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_12PAIR_X1_150to300MHz NO.32 3057 8, //E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_12PAIR_X1_150to150MHz NO.33 3058 72, //E_PNL_SUPPORTED_LPLL_USI_T_10BIT_12PAIR_150to300MHz NO.34 3059 72, //E_PNL_SUPPORTED_LPLL_USI_T_10BIT_12PAIR_150to150MHz NO.35 3060 8, //E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12PAIR_150to300MHz NO.36 3061 8, //E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12PAIR_150to150MHz NO.37 3062 8, //E_PNL_SUPPORTED_LPLL_ISP_10BIT_12PAIR_150to300MHz NO.38 3063 8, //E_PNL_SUPPORTED_LPLL_ISP_10BIT_12PAIR_150to150MHz NO.39 3064 8, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_12PAIR_150to300MHz NO.40 3065 8, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_12PAIR_150to150MHz NO.41 3066 16, //E_PNL_SUPPORTED_LPLL_ISP_10BIT_8PAIR_199_2to300MHz NO.42 3067 16, //E_PNL_SUPPORTED_LPLL_ISP_10BIT_8PAIR_150to199_2MHz NO.43 3068 16, //E_PNL_SUPPORTED_LPLL_ISP_10BIT_8PAIR_150to150MHz NO.44 3069 8, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_8PAIR_249to300MHz NO.45 3070 16, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_8PAIR_150to249MHz NO.46 3071 16, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_8PAIR_150to150MHz NO.47 3072 32, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_150to300MHz NO.48 3073 32, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_150to150MHz NO.49 3074 32, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to150MHz NO.50 3075 32, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to75MHz NO.51 3076 32, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_37_5to75MHz NO.52 3077 32, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_37_5to37_5MHz NO.53 3078 64, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_200to300MHz NO.54 3079 32, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_150to200MHz NO.55 3080 32, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_150to150MHz NO.56 3081 32, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_100to150MHz NO.57 3082 32, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to100MHz NO.58 3083 32, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to75MHz NO.59 3084 32, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_50to75MHz NO.60 3085 32, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_37_5to50MHz NO.61 3086 32, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_37_5to37_5MHz NO.62 3087 }; 3088 MS_U16 u16LoopDiv[E_PNL_SUPPORTED_LPLL_MAX]= 3089 { 3090 8, //E_PNL_SUPPORTED_LPLL_TTL_100to150MHz NO.0 3091 16, //E_PNL_SUPPORTED_LPLL_TTL_50to100MHz NO.1 3092 32, //E_PNL_SUPPORTED_LPLL_TTL_25to50MHz NO.2 3093 32, //E_PNL_SUPPORTED_LPLL_TTL_25to25MHz NO.3 3094 14, //E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to80MHz NO.4 3095 14, //E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to50MHz NO.5 3096 14, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to75MHz NO.6 3097 28, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to50MHz NO.7 3098 28, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to25MHz NO.8 3099 7, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_100to150MHz NO.9 3100 14, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to100MHz NO.10 3101 14, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to50MHz NO.11 3102 7, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_100to150MHz NO.12 3103 14, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_50to100MHz NO.13 3104 28, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to50MHz NO.14 3105 28, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to25MHz NO.15 3106 4, //E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_16PAIR_V17_150to300MHz NO.16 3107 4, //E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_16PAIR_V17_150to150MHz NO.17 3108 4, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_16PAIR_V17_200to300MHz NO.18 3109 4, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_16PAIR_V17_200to200MHz NO.19 3110 4, //E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12PAIR_V17_150to300MHz NO.20 3111 4, //E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12PAIR_V17_150to150MHz NO.21 3112 4, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12PAIR_V17_150to300MHz NO.22 3113 4, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12PAIR_V17_150to150MHz NO.23 3114 4, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_EPI3G_V17_180to300MHz NO.24 3115 4, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_EPI3G_V17_150to180MHz NO.25 3116 4, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_EPI3G_V17_150to150MHz NO.26 3117 4, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_EPI3G_V17_240to300MHz NO.27 3118 4, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_EPI3G_V17_150to240MHz NO.28 3119 4, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_EPI3G_V17_150to150MHz NO.29 3120 4, //E_PNL_SUPPORTED_LPLL_CMPI_24_10BIT_12PAIR_X1_150to300MHz NO.30 3121 4, //E_PNL_SUPPORTED_LPLL_CMPI_24_10BIT_12PAIR_X1_150to150MHz NO.31 3122 4, //E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_12PAIR_X1_150to300MHz NO.32 3123 4, //E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_12PAIR_X1_150to150MHz NO.33 3124 25, //E_PNL_SUPPORTED_LPLL_USI_T_10BIT_12PAIR_150to300MHz NO.34 3125 25, //E_PNL_SUPPORTED_LPLL_USI_T_10BIT_12PAIR_150to150MHz NO.35 3126 4, //E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12PAIR_150to300MHz NO.36 3127 4, //E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12PAIR_150to150MHz NO.37 3128 5, //E_PNL_SUPPORTED_LPLL_ISP_10BIT_12PAIR_150to300MHz NO.38 3129 5, //E_PNL_SUPPORTED_LPLL_ISP_10BIT_12PAIR_150to150MHz NO.39 3130 4, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_12PAIR_150to300MHz NO.40 3131 4, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_12PAIR_150to150MHz NO.41 3132 9, //E_PNL_SUPPORTED_LPLL_ISP_10BIT_8PAIR_199_2to300MHz NO.42 3133 9, //E_PNL_SUPPORTED_LPLL_ISP_10BIT_8PAIR_150to199_2MHz NO.43 3134 9, //E_PNL_SUPPORTED_LPLL_ISP_10BIT_8PAIR_150to150MHz NO.44 3135 3, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_8PAIR_249to300MHz NO.45 3136 9, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_8PAIR_150to249MHz NO.46 3137 9, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_8PAIR_150to150MHz NO.47 3138 10, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_150to300MHz NO.48 3139 10, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_150to150MHz NO.49 3140 20, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to150MHz NO.50 3141 20, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to75MHz NO.51 3142 40, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_37_5to75MHz NO.52 3143 40, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_37_5to37_5MHz NO.53 3144 15, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_200to300MHz NO.54 3145 15, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_150to200MHz NO.55 3146 15, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_150to150MHz NO.56 3147 15, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_100to150MHz NO.57 3148 30, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to100MHz NO.58 3149 30, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to75MHz NO.59 3150 30, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_50to75MHz NO.60 3151 60, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_37_5to50MHz NO.61 3152 60, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_37_5to37_5MHz NO.62 3153 }; 3154 3155 #endif //_LPLL_TBL_H_ 3156