1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. 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If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 79 #ifndef _LPLL_EXT_TBL_H_ 80 #define _LPLL_EXT_TBL_H_ 81 82 #define LPLL_EXT_REG_NUM 31 83 84 typedef enum 85 { 86 E_PNL_SUPPORTED_LPLL_EXT_VBY1_10BIT_4LANE_150to340MHz, //0 87 E_PNL_SUPPORTED_LPLL_EXT_VBY1_10BIT_4LANE_150to150MHz, //1 88 89 E_PNL_SUPPORTED_LPLL_EXT_VBY1_10BIT_2LANE_75to150MHz, //2 90 E_PNL_SUPPORTED_LPLL_EXT_VBY1_10BIT_2LANE_75to75MHz, //3 91 92 E_PNL_SUPPORTED_LPLL_EXT_VBY1_10BIT_1LANE_37_5to75MHz, //4 93 E_PNL_SUPPORTED_LPLL_EXT_VBY1_10BIT_1LANE_37_5to37_5MHz, //5 94 95 E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_4LANE_200to340MHz, //6 96 E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_4LANE_150to200MHz, //7 97 E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_4LANE_150to150MHz, //8 98 99 E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_2LANE_100to150MHz, //9 100 E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_2LANE_75to100MHz, //10 101 E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_2LANE_75to75MHz, //11 102 103 E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_1LANE_50to75MHz, //12 104 E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_1LANE_37_5to50MHz, //13 105 E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_1LANE_37_5to37_5MHz, //14 106 107 E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_100to150MHz, //15 108 E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_50to100MHz, //16 109 E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_25to50MHz, //17 110 E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_25to25MHz, //18 111 112 E_PNL_SUPPORTED_LPLL_EXT_MAX, //19 113 } E_PNL_SUPPORTED_LPLL_EXT_TYPE; 114 115 typedef struct 116 { 117 MS_U8 address; 118 MS_U16 value; 119 MS_U16 mask; 120 }TBLStruct_Ext,*pTBLStruct_Ext; 121 122 TBLStruct_Ext LPLLSettingTBL_Ext[E_PNL_SUPPORTED_LPLL_EXT_MAX][LPLL_EXT_REG_NUM]= 123 { 124 { //E_PNL_SUPPORTED_LPLL_EXT_VBY1_10BIT_4LANE_150to340MHz NO.0 125 //Address,Value,Mask 126 {0x59,0x0000,0x2000},//reg_lpll1_nossc_pd 127 {0x40,0x0003,0x0007},//reg_lpll_ext_ictrl 128 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 129 {0x41,0x0030,0x0030},//reg_lpll_ext_loop_div_fst 130 {0x41,0x0400,0x0F00},//reg_lpll_ext_loop_div_sec 131 {0x42,0x0002,0x0003},//reg_lpll_ext_scalar_div_fst 132 {0x42,0x0000,0x00F0},//reg_lpll_ext_scalar_div_sec 133 {0x43,0x0000,0x0007},//reg_lpll_ext_skew_div 134 {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div 135 {0x40,0x1000,0x1000},//reg_lpll_ext_fifo_div5_en 136 {0x5A,0x0000,0x0040},//reg_lpll_ext_en_fix_clk 137 {0x40,0x0800,0x0800},//reg_lpll_ext_dual_lp_en 138 {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en 139 {0x40,0x0000,0x2000},//reg_lpll_ext_en_mini 140 {0x40,0x0400,0x0400},//reg_lpll1_ext_en_fifo 141 {0x4A,0x0000,0x8000},//reg_lpll_ext_test[15] 142 {0x4B,0x0000,0x0001},//reg_lpll_ext_test[16] 143 {0x4B,0x0000,0x0040},//reg_lpll_ext_test[22] 144 {0x59,0x4000,0x4000},//reg_lpll2_ext_nossc_pd 145 {0x58,0x0000,0x4000},//reg_lpll2_ext_ibias_ictrl 146 {0x58,0x0000,0x001F},//reg_lpll2_ext_input_div_first 147 {0x58,0x0000,0x0060},//reg_lpll2_ext_loop_div_first 148 {0x58,0x0000,0x1F00},//reg_lpll2_ext_loop_div_second 149 {0x5A,0x0000,0x000F},//reg_lpll2_ext_output_div_first 150 {0x59,0x0000,0x0800},//reg_lpll2_ext_test[11] 151 {0x59,0x0000,0x1000},//reg_lpll2_ext_test[12] 152 {0x59,0x0000,0x0100},//reg_lpll2_ext_test[8] 153 {0x5A,0x0000,0x2000},//reg_lpll_ext_2ndpll_clk_sel 154 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 155 {0x5A,0x0000,0x0200},//reg_lpll_ext_scalar2fifo_en 156 {0x5A,0x0000,0x0100},//reg_lpll_scalar2fifo_div2 157 }, 158 159 { //E_PNL_SUPPORTED_LPLL_EXT_VBY1_10BIT_4LANE_150to150MHz NO.1 160 //Address,Value,Mask 161 {0x59,0x0000,0x2000},//reg_lpll1_nossc_pd 162 {0x40,0x0003,0x0007},//reg_lpll_ext_ictrl 163 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 164 {0x41,0x0030,0x0030},//reg_lpll_ext_loop_div_fst 165 {0x41,0x0400,0x0F00},//reg_lpll_ext_loop_div_sec 166 {0x42,0x0002,0x0003},//reg_lpll_ext_scalar_div_fst 167 {0x42,0x0000,0x00F0},//reg_lpll_ext_scalar_div_sec 168 {0x43,0x0000,0x0007},//reg_lpll_ext_skew_div 169 {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div 170 {0x40,0x1000,0x1000},//reg_lpll_ext_fifo_div5_en 171 {0x5A,0x0000,0x0040},//reg_lpll_ext_en_fix_clk 172 {0x40,0x0800,0x0800},//reg_lpll_ext_dual_lp_en 173 {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en 174 {0x40,0x0000,0x2000},//reg_lpll_ext_en_mini 175 {0x40,0x0400,0x0400},//reg_lpll1_ext_en_fifo 176 {0x4A,0x0000,0x8000},//reg_lpll_ext_test[15] 177 {0x4B,0x0000,0x0001},//reg_lpll_ext_test[16] 178 {0x4B,0x0000,0x0040},//reg_lpll_ext_test[22] 179 {0x59,0x4000,0x4000},//reg_lpll2_ext_nossc_pd 180 {0x58,0x0000,0x4000},//reg_lpll2_ext_ibias_ictrl 181 {0x58,0x0000,0x001F},//reg_lpll2_ext_input_div_first 182 {0x58,0x0000,0x0060},//reg_lpll2_ext_loop_div_first 183 {0x58,0x0000,0x1F00},//reg_lpll2_ext_loop_div_second 184 {0x5A,0x0000,0x000F},//reg_lpll2_ext_output_div_first 185 {0x59,0x0000,0x0800},//reg_lpll2_ext_test[11] 186 {0x59,0x0000,0x1000},//reg_lpll2_ext_test[12] 187 {0x59,0x0000,0x0100},//reg_lpll2_ext_test[8] 188 {0x5A,0x0000,0x2000},//reg_lpll_ext_2ndpll_clk_sel 189 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 190 {0x5A,0x0000,0x0200},//reg_lpll_ext_scalar2fifo_en 191 {0x5A,0x0000,0x0100},//reg_lpll_scalar2fifo_div2 192 }, 193 194 { //E_PNL_SUPPORTED_LPLL_EXT_VBY1_10BIT_2LANE_75to150MHz NO.2 195 //Address,Value,Mask 196 {0x59,0x0000,0x2000},//reg_lpll1_nossc_pd 197 {0x40,0x0003,0x0007},//reg_lpll_ext_ictrl 198 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 199 {0x41,0x0030,0x0030},//reg_lpll_ext_loop_div_fst 200 {0x41,0x0400,0x0F00},//reg_lpll_ext_loop_div_sec 201 {0x42,0x0003,0x0003},//reg_lpll_ext_scalar_div_fst 202 {0x42,0x0000,0x00F0},//reg_lpll_ext_scalar_div_sec 203 {0x43,0x0000,0x0007},//reg_lpll_ext_skew_div 204 {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div 205 {0x40,0x1000,0x1000},//reg_lpll_ext_fifo_div5_en 206 {0x5A,0x0000,0x0040},//reg_lpll_ext_en_fix_clk 207 {0x40,0x0800,0x0800},//reg_lpll_ext_dual_lp_en 208 {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en 209 {0x40,0x0000,0x2000},//reg_lpll_ext_en_mini 210 {0x40,0x0400,0x0400},//reg_lpll1_ext_en_fifo 211 {0x4A,0x0000,0x8000},//reg_lpll_ext_test[15] 212 {0x4B,0x0000,0x0001},//reg_lpll_ext_test[16] 213 {0x4B,0x0000,0x0040},//reg_lpll_ext_test[22] 214 {0x59,0x4000,0x4000},//reg_lpll2_ext_nossc_pd 215 {0x58,0x0000,0x4000},//reg_lpll2_ext_ibias_ictrl 216 {0x58,0x0000,0x001F},//reg_lpll2_ext_input_div_first 217 {0x58,0x0000,0x0060},//reg_lpll2_ext_loop_div_first 218 {0x58,0x0000,0x1F00},//reg_lpll2_ext_loop_div_second 219 {0x5A,0x0000,0x000F},//reg_lpll2_ext_output_div_first 220 {0x59,0x0000,0x0800},//reg_lpll2_ext_test[11] 221 {0x59,0x0000,0x1000},//reg_lpll2_ext_test[12] 222 {0x59,0x0000,0x0100},//reg_lpll2_ext_test[8] 223 {0x5A,0x0000,0x2000},//reg_lpll_ext_2ndpll_clk_sel 224 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 225 {0x5A,0x0000,0x0200},//reg_lpll_ext_scalar2fifo_en 226 {0x5A,0x0000,0x0100},//reg_lpll_scalar2fifo_div2 227 }, 228 229 { //E_PNL_SUPPORTED_LPLL_EXT_VBY1_10BIT_2LANE_75to75MHz NO.3 230 //Address,Value,Mask 231 {0x59,0x0000,0x2000},//reg_lpll1_nossc_pd 232 {0x40,0x0003,0x0007},//reg_lpll_ext_ictrl 233 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 234 {0x41,0x0030,0x0030},//reg_lpll_ext_loop_div_fst 235 {0x41,0x0400,0x0F00},//reg_lpll_ext_loop_div_sec 236 {0x42,0x0003,0x0003},//reg_lpll_ext_scalar_div_fst 237 {0x42,0x0000,0x00F0},//reg_lpll_ext_scalar_div_sec 238 {0x43,0x0000,0x0007},//reg_lpll_ext_skew_div 239 {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div 240 {0x40,0x1000,0x1000},//reg_lpll_ext_fifo_div5_en 241 {0x5A,0x0000,0x0040},//reg_lpll_ext_en_fix_clk 242 {0x40,0x0800,0x0800},//reg_lpll_ext_dual_lp_en 243 {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en 244 {0x40,0x0000,0x2000},//reg_lpll_ext_en_mini 245 {0x40,0x0400,0x0400},//reg_lpll1_ext_en_fifo 246 {0x4A,0x0000,0x8000},//reg_lpll_ext_test[15] 247 {0x4B,0x0000,0x0001},//reg_lpll_ext_test[16] 248 {0x4B,0x0000,0x0040},//reg_lpll_ext_test[22] 249 {0x59,0x4000,0x4000},//reg_lpll2_ext_nossc_pd 250 {0x58,0x0000,0x4000},//reg_lpll2_ext_ibias_ictrl 251 {0x58,0x0000,0x001F},//reg_lpll2_ext_input_div_first 252 {0x58,0x0000,0x0060},//reg_lpll2_ext_loop_div_first 253 {0x58,0x0000,0x1F00},//reg_lpll2_ext_loop_div_second 254 {0x5A,0x0000,0x000F},//reg_lpll2_ext_output_div_first 255 {0x59,0x0000,0x0800},//reg_lpll2_ext_test[11] 256 {0x59,0x0000,0x1000},//reg_lpll2_ext_test[12] 257 {0x59,0x0000,0x0100},//reg_lpll2_ext_test[8] 258 {0x5A,0x0000,0x2000},//reg_lpll_ext_2ndpll_clk_sel 259 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 260 {0x5A,0x0000,0x0200},//reg_lpll_ext_scalar2fifo_en 261 {0x5A,0x0000,0x0100},//reg_lpll_scalar2fifo_div2 262 }, 263 264 { //E_PNL_SUPPORTED_LPLL_EXT_VBY1_10BIT_1LANE_37_5to75MHz NO.4 265 //Address,Value,Mask 266 {0x59,0x0000,0x2000},//reg_lpll1_nossc_pd 267 {0x40,0x0003,0x0007},//reg_lpll_ext_ictrl 268 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 269 {0x41,0x0030,0x0030},//reg_lpll_ext_loop_div_fst 270 {0x41,0x0400,0x0F00},//reg_lpll_ext_loop_div_sec 271 {0x42,0x0003,0x0003},//reg_lpll_ext_scalar_div_fst 272 {0x42,0x0020,0x00F0},//reg_lpll_ext_scalar_div_sec 273 {0x43,0x0000,0x0007},//reg_lpll_ext_skew_div 274 {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div 275 {0x40,0x1000,0x1000},//reg_lpll_ext_fifo_div5_en 276 {0x5A,0x0000,0x0040},//reg_lpll_ext_en_fix_clk 277 {0x40,0x0800,0x0800},//reg_lpll_ext_dual_lp_en 278 {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en 279 {0x40,0x0000,0x2000},//reg_lpll_ext_en_mini 280 {0x40,0x0400,0x0400},//reg_lpll1_ext_en_fifo 281 {0x4A,0x0000,0x8000},//reg_lpll_ext_test[15] 282 {0x4B,0x0000,0x0001},//reg_lpll_ext_test[16] 283 {0x4B,0x0000,0x0040},//reg_lpll_ext_test[22] 284 {0x59,0x4000,0x4000},//reg_lpll2_ext_nossc_pd 285 {0x58,0x0000,0x4000},//reg_lpll2_ext_ibias_ictrl 286 {0x58,0x0000,0x001F},//reg_lpll2_ext_input_div_first 287 {0x58,0x0000,0x0060},//reg_lpll2_ext_loop_div_first 288 {0x58,0x0000,0x1F00},//reg_lpll2_ext_loop_div_second 289 {0x5A,0x0000,0x000F},//reg_lpll2_ext_output_div_first 290 {0x59,0x0000,0x0800},//reg_lpll2_ext_test[11] 291 {0x59,0x0000,0x1000},//reg_lpll2_ext_test[12] 292 {0x59,0x0000,0x0100},//reg_lpll2_ext_test[8] 293 {0x5A,0x0000,0x2000},//reg_lpll_ext_2ndpll_clk_sel 294 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 295 {0x5A,0x0000,0x0200},//reg_lpll_ext_scalar2fifo_en 296 {0x5A,0x0000,0x0100},//reg_lpll_scalar2fifo_div2 297 }, 298 299 { //E_PNL_SUPPORTED_LPLL_EXT_VBY1_10BIT_1LANE_37_5to37_5MHz NO.5 300 //Address,Value,Mask 301 {0x59,0x0000,0x2000},//reg_lpll1_nossc_pd 302 {0x40,0x0003,0x0007},//reg_lpll_ext_ictrl 303 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 304 {0x41,0x0030,0x0030},//reg_lpll_ext_loop_div_fst 305 {0x41,0x0400,0x0F00},//reg_lpll_ext_loop_div_sec 306 {0x42,0x0003,0x0003},//reg_lpll_ext_scalar_div_fst 307 {0x42,0x0020,0x00F0},//reg_lpll_ext_scalar_div_sec 308 {0x43,0x0000,0x0007},//reg_lpll_ext_skew_div 309 {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div 310 {0x40,0x1000,0x1000},//reg_lpll_ext_fifo_div5_en 311 {0x5A,0x0000,0x0040},//reg_lpll_ext_en_fix_clk 312 {0x40,0x0800,0x0800},//reg_lpll_ext_dual_lp_en 313 {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en 314 {0x40,0x0000,0x2000},//reg_lpll_ext_en_mini 315 {0x40,0x0400,0x0400},//reg_lpll1_ext_en_fifo 316 {0x4A,0x0000,0x8000},//reg_lpll_ext_test[15] 317 {0x4B,0x0000,0x0001},//reg_lpll_ext_test[16] 318 {0x4B,0x0000,0x0040},//reg_lpll_ext_test[22] 319 {0x59,0x4000,0x4000},//reg_lpll2_ext_nossc_pd 320 {0x58,0x0000,0x4000},//reg_lpll2_ext_ibias_ictrl 321 {0x58,0x0000,0x001F},//reg_lpll2_ext_input_div_first 322 {0x58,0x0000,0x0060},//reg_lpll2_ext_loop_div_first 323 {0x58,0x0000,0x1F00},//reg_lpll2_ext_loop_div_second 324 {0x5A,0x0000,0x000F},//reg_lpll2_ext_output_div_first 325 {0x59,0x0000,0x0800},//reg_lpll2_ext_test[11] 326 {0x59,0x0000,0x1000},//reg_lpll2_ext_test[12] 327 {0x59,0x0000,0x0100},//reg_lpll2_ext_test[8] 328 {0x5A,0x0000,0x2000},//reg_lpll_ext_2ndpll_clk_sel 329 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 330 {0x5A,0x0000,0x0200},//reg_lpll_ext_scalar2fifo_en 331 {0x5A,0x0000,0x0100},//reg_lpll_scalar2fifo_div2 332 }, 333 334 { //E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_4LANE_200to340MHz NO.6 335 //Address,Value,Mask 336 {0x59,0x0000,0x2000},//reg_lpll1_nossc_pd 337 {0x40,0x0003,0x0007},//reg_lpll_ext_ictrl 338 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 339 {0x41,0x0030,0x0030},//reg_lpll_ext_loop_div_fst 340 {0x41,0x0400,0x0F00},//reg_lpll_ext_loop_div_sec 341 {0x42,0x0000,0x0003},//reg_lpll_ext_scalar_div_fst 342 {0x42,0x0030,0x00F0},//reg_lpll_ext_scalar_div_sec 343 {0x43,0x0000,0x0007},//reg_lpll_ext_skew_div 344 {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div 345 {0x40,0x1000,0x1000},//reg_lpll_ext_fifo_div5_en 346 {0x5A,0x0000,0x0040},//reg_lpll_ext_en_fix_clk 347 {0x40,0x0800,0x0800},//reg_lpll_ext_dual_lp_en 348 {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en 349 {0x40,0x0000,0x2000},//reg_lpll_ext_en_mini 350 {0x40,0x0400,0x0400},//reg_lpll1_ext_en_fifo 351 {0x4A,0x0000,0x8000},//reg_lpll_ext_test[15] 352 {0x4B,0x0000,0x0001},//reg_lpll_ext_test[16] 353 {0x4B,0x0000,0x0040},//reg_lpll_ext_test[22] 354 {0x59,0x4000,0x4000},//reg_lpll2_ext_nossc_pd 355 {0x58,0x0000,0x4000},//reg_lpll2_ext_ibias_ictrl 356 {0x58,0x0000,0x001F},//reg_lpll2_ext_input_div_first 357 {0x58,0x0000,0x0060},//reg_lpll2_ext_loop_div_first 358 {0x58,0x0000,0x1F00},//reg_lpll2_ext_loop_div_second 359 {0x5A,0x0000,0x000F},//reg_lpll2_ext_output_div_first 360 {0x59,0x0000,0x0800},//reg_lpll2_ext_test[11] 361 {0x59,0x0000,0x1000},//reg_lpll2_ext_test[12] 362 {0x59,0x0000,0x0100},//reg_lpll2_ext_test[8] 363 {0x5A,0x0000,0x2000},//reg_lpll_ext_2ndpll_clk_sel 364 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 365 {0x5A,0x0000,0x0200},//reg_lpll_ext_scalar2fifo_en 366 {0x5A,0x0000,0x0100},//reg_lpll_scalar2fifo_div2 367 }, 368 369 { //E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_4LANE_150to200MHz NO.7 370 //Address,Value,Mask 371 {0x59,0x0000,0x2000},//reg_lpll1_nossc_pd 372 {0x40,0x0003,0x0007},//reg_lpll_ext_ictrl 373 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 374 {0x41,0x0030,0x0030},//reg_lpll_ext_loop_div_fst 375 {0x41,0x0400,0x0F00},//reg_lpll_ext_loop_div_sec 376 {0x42,0x0001,0x0003},//reg_lpll_ext_scalar_div_fst 377 {0x42,0x0030,0x00F0},//reg_lpll_ext_scalar_div_sec 378 {0x43,0x0001,0x0007},//reg_lpll_ext_skew_div 379 {0x42,0x0400,0x0700},//reg_lpll_ext_fifo_div 380 {0x40,0x1000,0x1000},//reg_lpll_ext_fifo_div5_en 381 {0x5A,0x0000,0x0040},//reg_lpll_ext_en_fix_clk 382 {0x40,0x0800,0x0800},//reg_lpll_ext_dual_lp_en 383 {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en 384 {0x40,0x0000,0x2000},//reg_lpll_ext_en_mini 385 {0x40,0x0400,0x0400},//reg_lpll1_ext_en_fifo 386 {0x4A,0x0000,0x8000},//reg_lpll_ext_test[15] 387 {0x4B,0x0000,0x0001},//reg_lpll_ext_test[16] 388 {0x4B,0x0000,0x0040},//reg_lpll_ext_test[22] 389 {0x59,0x4000,0x4000},//reg_lpll2_ext_nossc_pd 390 {0x58,0x0000,0x4000},//reg_lpll2_ext_ibias_ictrl 391 {0x58,0x0000,0x001F},//reg_lpll2_ext_input_div_first 392 {0x58,0x0000,0x0060},//reg_lpll2_ext_loop_div_first 393 {0x58,0x0000,0x1F00},//reg_lpll2_ext_loop_div_second 394 {0x5A,0x0000,0x000F},//reg_lpll2_ext_output_div_first 395 {0x59,0x0000,0x0800},//reg_lpll2_ext_test[11] 396 {0x59,0x0000,0x1000},//reg_lpll2_ext_test[12] 397 {0x59,0x0000,0x0100},//reg_lpll2_ext_test[8] 398 {0x5A,0x0000,0x2000},//reg_lpll_ext_2ndpll_clk_sel 399 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 400 {0x5A,0x0000,0x0200},//reg_lpll_ext_scalar2fifo_en 401 {0x5A,0x0000,0x0100},//reg_lpll_scalar2fifo_div2 402 }, 403 404 { //E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_4LANE_150to150MHz NO.8 405 //Address,Value,Mask 406 {0x59,0x0000,0x2000},//reg_lpll1_nossc_pd 407 {0x40,0x0003,0x0007},//reg_lpll_ext_ictrl 408 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 409 {0x41,0x0030,0x0030},//reg_lpll_ext_loop_div_fst 410 {0x41,0x0400,0x0F00},//reg_lpll_ext_loop_div_sec 411 {0x42,0x0001,0x0003},//reg_lpll_ext_scalar_div_fst 412 {0x42,0x0030,0x00F0},//reg_lpll_ext_scalar_div_sec 413 {0x43,0x0001,0x0007},//reg_lpll_ext_skew_div 414 {0x42,0x0400,0x0700},//reg_lpll_ext_fifo_div 415 {0x40,0x1000,0x1000},//reg_lpll_ext_fifo_div5_en 416 {0x5A,0x0000,0x0040},//reg_lpll_ext_en_fix_clk 417 {0x40,0x0800,0x0800},//reg_lpll_ext_dual_lp_en 418 {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en 419 {0x40,0x0000,0x2000},//reg_lpll_ext_en_mini 420 {0x40,0x0400,0x0400},//reg_lpll1_ext_en_fifo 421 {0x4A,0x0000,0x8000},//reg_lpll_ext_test[15] 422 {0x4B,0x0000,0x0001},//reg_lpll_ext_test[16] 423 {0x4B,0x0000,0x0040},//reg_lpll_ext_test[22] 424 {0x59,0x4000,0x4000},//reg_lpll2_ext_nossc_pd 425 {0x58,0x0000,0x4000},//reg_lpll2_ext_ibias_ictrl 426 {0x58,0x0000,0x001F},//reg_lpll2_ext_input_div_first 427 {0x58,0x0000,0x0060},//reg_lpll2_ext_loop_div_first 428 {0x58,0x0000,0x1F00},//reg_lpll2_ext_loop_div_second 429 {0x5A,0x0000,0x000F},//reg_lpll2_ext_output_div_first 430 {0x59,0x0000,0x0800},//reg_lpll2_ext_test[11] 431 {0x59,0x0000,0x1000},//reg_lpll2_ext_test[12] 432 {0x59,0x0000,0x0100},//reg_lpll2_ext_test[8] 433 {0x5A,0x0000,0x2000},//reg_lpll_ext_2ndpll_clk_sel 434 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 435 {0x5A,0x0000,0x0200},//reg_lpll_ext_scalar2fifo_en 436 {0x5A,0x0000,0x0100},//reg_lpll_scalar2fifo_div2 437 }, 438 439 { //E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_2LANE_100to150MHz NO.9 440 //Address,Value,Mask 441 {0x59,0x0000,0x2000},//reg_lpll1_nossc_pd 442 {0x40,0x0003,0x0007},//reg_lpll_ext_ictrl 443 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 444 {0x41,0x0030,0x0030},//reg_lpll_ext_loop_div_fst 445 {0x41,0x0400,0x0F00},//reg_lpll_ext_loop_div_sec 446 {0x42,0x0001,0x0003},//reg_lpll_ext_scalar_div_fst 447 {0x42,0x0030,0x00F0},//reg_lpll_ext_scalar_div_sec 448 {0x43,0x0000,0x0007},//reg_lpll_ext_skew_div 449 {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div 450 {0x40,0x1000,0x1000},//reg_lpll_ext_fifo_div5_en 451 {0x5A,0x0000,0x0040},//reg_lpll_ext_en_fix_clk 452 {0x40,0x0800,0x0800},//reg_lpll_ext_dual_lp_en 453 {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en 454 {0x40,0x0000,0x2000},//reg_lpll_ext_en_mini 455 {0x40,0x0400,0x0400},//reg_lpll1_ext_en_fifo 456 {0x4A,0x0000,0x8000},//reg_lpll_ext_test[15] 457 {0x4B,0x0000,0x0001},//reg_lpll_ext_test[16] 458 {0x4B,0x0000,0x0040},//reg_lpll_ext_test[22] 459 {0x59,0x4000,0x4000},//reg_lpll2_ext_nossc_pd 460 {0x58,0x0000,0x4000},//reg_lpll2_ext_ibias_ictrl 461 {0x58,0x0000,0x001F},//reg_lpll2_ext_input_div_first 462 {0x58,0x0000,0x0060},//reg_lpll2_ext_loop_div_first 463 {0x58,0x0000,0x1F00},//reg_lpll2_ext_loop_div_second 464 {0x5A,0x0000,0x000F},//reg_lpll2_ext_output_div_first 465 {0x59,0x0000,0x0800},//reg_lpll2_ext_test[11] 466 {0x59,0x0000,0x1000},//reg_lpll2_ext_test[12] 467 {0x59,0x0000,0x0100},//reg_lpll2_ext_test[8] 468 {0x5A,0x0000,0x2000},//reg_lpll_ext_2ndpll_clk_sel 469 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 470 {0x5A,0x0000,0x0200},//reg_lpll_ext_scalar2fifo_en 471 {0x5A,0x0000,0x0100},//reg_lpll_scalar2fifo_div2 472 }, 473 474 { //E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_2LANE_75to100MHz NO.10 475 //Address,Value,Mask 476 {0x59,0x0000,0x2000},//reg_lpll1_nossc_pd 477 {0x40,0x0003,0x0007},//reg_lpll_ext_ictrl 478 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 479 {0x41,0x0030,0x0030},//reg_lpll_ext_loop_div_fst 480 {0x41,0x0400,0x0F00},//reg_lpll_ext_loop_div_sec 481 {0x42,0x0002,0x0003},//reg_lpll_ext_scalar_div_fst 482 {0x42,0x0030,0x00F0},//reg_lpll_ext_scalar_div_sec 483 {0x43,0x0001,0x0007},//reg_lpll_ext_skew_div 484 {0x42,0x0400,0x0700},//reg_lpll_ext_fifo_div 485 {0x40,0x1000,0x1000},//reg_lpll_ext_fifo_div5_en 486 {0x5A,0x0000,0x0040},//reg_lpll_ext_en_fix_clk 487 {0x40,0x0800,0x0800},//reg_lpll_ext_dual_lp_en 488 {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en 489 {0x40,0x0000,0x2000},//reg_lpll_ext_en_mini 490 {0x40,0x0400,0x0400},//reg_lpll1_ext_en_fifo 491 {0x4A,0x0000,0x8000},//reg_lpll_ext_test[15] 492 {0x4B,0x0000,0x0001},//reg_lpll_ext_test[16] 493 {0x4B,0x0000,0x0040},//reg_lpll_ext_test[22] 494 {0x59,0x4000,0x4000},//reg_lpll2_ext_nossc_pd 495 {0x58,0x0000,0x4000},//reg_lpll2_ext_ibias_ictrl 496 {0x58,0x0000,0x001F},//reg_lpll2_ext_input_div_first 497 {0x58,0x0000,0x0060},//reg_lpll2_ext_loop_div_first 498 {0x58,0x0000,0x1F00},//reg_lpll2_ext_loop_div_second 499 {0x5A,0x0000,0x000F},//reg_lpll2_ext_output_div_first 500 {0x59,0x0000,0x0800},//reg_lpll2_ext_test[11] 501 {0x59,0x0000,0x1000},//reg_lpll2_ext_test[12] 502 {0x59,0x0000,0x0100},//reg_lpll2_ext_test[8] 503 {0x5A,0x0000,0x2000},//reg_lpll_ext_2ndpll_clk_sel 504 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 505 {0x5A,0x0000,0x0200},//reg_lpll_ext_scalar2fifo_en 506 {0x5A,0x0000,0x0100},//reg_lpll_scalar2fifo_div2 507 }, 508 509 { //E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_2LANE_75to75MHz NO.11 510 //Address,Value,Mask 511 {0x59,0x0000,0x2000},//reg_lpll1_nossc_pd 512 {0x40,0x0003,0x0007},//reg_lpll_ext_ictrl 513 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 514 {0x41,0x0030,0x0030},//reg_lpll_ext_loop_div_fst 515 {0x41,0x0400,0x0F00},//reg_lpll_ext_loop_div_sec 516 {0x42,0x0002,0x0003},//reg_lpll_ext_scalar_div_fst 517 {0x42,0x0030,0x00F0},//reg_lpll_ext_scalar_div_sec 518 {0x43,0x0001,0x0007},//reg_lpll_ext_skew_div 519 {0x42,0x0400,0x0700},//reg_lpll_ext_fifo_div 520 {0x40,0x1000,0x1000},//reg_lpll_ext_fifo_div5_en 521 {0x5A,0x0000,0x0040},//reg_lpll_ext_en_fix_clk 522 {0x40,0x0800,0x0800},//reg_lpll_ext_dual_lp_en 523 {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en 524 {0x40,0x0000,0x2000},//reg_lpll_ext_en_mini 525 {0x40,0x0400,0x0400},//reg_lpll1_ext_en_fifo 526 {0x4A,0x0000,0x8000},//reg_lpll_ext_test[15] 527 {0x4B,0x0000,0x0001},//reg_lpll_ext_test[16] 528 {0x4B,0x0000,0x0040},//reg_lpll_ext_test[22] 529 {0x59,0x4000,0x4000},//reg_lpll2_ext_nossc_pd 530 {0x58,0x0000,0x4000},//reg_lpll2_ext_ibias_ictrl 531 {0x58,0x0000,0x001F},//reg_lpll2_ext_input_div_first 532 {0x58,0x0000,0x0060},//reg_lpll2_ext_loop_div_first 533 {0x58,0x0000,0x1F00},//reg_lpll2_ext_loop_div_second 534 {0x5A,0x0000,0x000F},//reg_lpll2_ext_output_div_first 535 {0x59,0x0000,0x0800},//reg_lpll2_ext_test[11] 536 {0x59,0x0000,0x1000},//reg_lpll2_ext_test[12] 537 {0x59,0x0000,0x0100},//reg_lpll2_ext_test[8] 538 {0x5A,0x0000,0x2000},//reg_lpll_ext_2ndpll_clk_sel 539 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 540 {0x5A,0x0000,0x0200},//reg_lpll_ext_scalar2fifo_en 541 {0x5A,0x0000,0x0100},//reg_lpll_scalar2fifo_div2 542 }, 543 544 { //E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_1LANE_50to75MHz NO.12 545 //Address,Value,Mask 546 {0x59,0x0000,0x2000},//reg_lpll1_nossc_pd 547 {0x40,0x0003,0x0007},//reg_lpll_ext_ictrl 548 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 549 {0x41,0x0030,0x0030},//reg_lpll_ext_loop_div_fst 550 {0x41,0x0400,0x0F00},//reg_lpll_ext_loop_div_sec 551 {0x42,0x0002,0x0003},//reg_lpll_ext_scalar_div_fst 552 {0x42,0x0030,0x00F0},//reg_lpll_ext_scalar_div_sec 553 {0x43,0x0000,0x0007},//reg_lpll_ext_skew_div 554 {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div 555 {0x40,0x1000,0x1000},//reg_lpll_ext_fifo_div5_en 556 {0x5A,0x0000,0x0040},//reg_lpll_ext_en_fix_clk 557 {0x40,0x0800,0x0800},//reg_lpll_ext_dual_lp_en 558 {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en 559 {0x40,0x0000,0x2000},//reg_lpll_ext_en_mini 560 {0x40,0x0400,0x0400},//reg_lpll1_ext_en_fifo 561 {0x4A,0x0000,0x8000},//reg_lpll_ext_test[15] 562 {0x4B,0x0000,0x0001},//reg_lpll_ext_test[16] 563 {0x4B,0x0000,0x0040},//reg_lpll_ext_test[22] 564 {0x59,0x4000,0x4000},//reg_lpll2_ext_nossc_pd 565 {0x58,0x0000,0x4000},//reg_lpll2_ext_ibias_ictrl 566 {0x58,0x0000,0x001F},//reg_lpll2_ext_input_div_first 567 {0x58,0x0000,0x0060},//reg_lpll2_ext_loop_div_first 568 {0x58,0x0000,0x1F00},//reg_lpll2_ext_loop_div_second 569 {0x5A,0x0000,0x000F},//reg_lpll2_ext_output_div_first 570 {0x59,0x0000,0x0800},//reg_lpll2_ext_test[11] 571 {0x59,0x0000,0x1000},//reg_lpll2_ext_test[12] 572 {0x59,0x0000,0x0100},//reg_lpll2_ext_test[8] 573 {0x5A,0x0000,0x2000},//reg_lpll_ext_2ndpll_clk_sel 574 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 575 {0x5A,0x0000,0x0200},//reg_lpll_ext_scalar2fifo_en 576 {0x5A,0x0000,0x0100},//reg_lpll_scalar2fifo_div2 577 }, 578 579 { //E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_1LANE_37_5to50MHz NO.13 580 //Address,Value,Mask 581 {0x59,0x0000,0x2000},//reg_lpll1_nossc_pd 582 {0x40,0x0003,0x0007},//reg_lpll_ext_ictrl 583 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 584 {0x41,0x0030,0x0030},//reg_lpll_ext_loop_div_fst 585 {0x41,0x0400,0x0F00},//reg_lpll_ext_loop_div_sec 586 {0x42,0x0003,0x0003},//reg_lpll_ext_scalar_div_fst 587 {0x42,0x0030,0x00F0},//reg_lpll_ext_scalar_div_sec 588 {0x43,0x0001,0x0007},//reg_lpll_ext_skew_div 589 {0x42,0x0400,0x0700},//reg_lpll_ext_fifo_div 590 {0x40,0x1000,0x1000},//reg_lpll_ext_fifo_div5_en 591 {0x5A,0x0000,0x0040},//reg_lpll_ext_en_fix_clk 592 {0x40,0x0800,0x0800},//reg_lpll_ext_dual_lp_en 593 {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en 594 {0x40,0x0000,0x2000},//reg_lpll_ext_en_mini 595 {0x40,0x0400,0x0400},//reg_lpll1_ext_en_fifo 596 {0x4A,0x0000,0x8000},//reg_lpll_ext_test[15] 597 {0x4B,0x0000,0x0001},//reg_lpll_ext_test[16] 598 {0x4B,0x0000,0x0040},//reg_lpll_ext_test[22] 599 {0x59,0x4000,0x4000},//reg_lpll2_ext_nossc_pd 600 {0x58,0x0000,0x4000},//reg_lpll2_ext_ibias_ictrl 601 {0x58,0x0000,0x001F},//reg_lpll2_ext_input_div_first 602 {0x58,0x0000,0x0060},//reg_lpll2_ext_loop_div_first 603 {0x58,0x0000,0x1F00},//reg_lpll2_ext_loop_div_second 604 {0x5A,0x0000,0x000F},//reg_lpll2_ext_output_div_first 605 {0x59,0x0000,0x0800},//reg_lpll2_ext_test[11] 606 {0x59,0x0000,0x1000},//reg_lpll2_ext_test[12] 607 {0x59,0x0000,0x0100},//reg_lpll2_ext_test[8] 608 {0x5A,0x0000,0x2000},//reg_lpll_ext_2ndpll_clk_sel 609 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 610 {0x5A,0x0000,0x0200},//reg_lpll_ext_scalar2fifo_en 611 {0x5A,0x0000,0x0100},//reg_lpll_scalar2fifo_div2 612 }, 613 614 { //E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_1LANE_37_5to37_5MHz NO.14 615 //Address,Value,Mask 616 {0x59,0x0000,0x2000},//reg_lpll1_nossc_pd 617 {0x40,0x0003,0x0007},//reg_lpll_ext_ictrl 618 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 619 {0x41,0x0030,0x0030},//reg_lpll_ext_loop_div_fst 620 {0x41,0x0400,0x0F00},//reg_lpll_ext_loop_div_sec 621 {0x42,0x0003,0x0003},//reg_lpll_ext_scalar_div_fst 622 {0x42,0x0030,0x00F0},//reg_lpll_ext_scalar_div_sec 623 {0x43,0x0001,0x0007},//reg_lpll_ext_skew_div 624 {0x42,0x0400,0x0700},//reg_lpll_ext_fifo_div 625 {0x40,0x1000,0x1000},//reg_lpll_ext_fifo_div5_en 626 {0x5A,0x0000,0x0040},//reg_lpll_ext_en_fix_clk 627 {0x40,0x0800,0x0800},//reg_lpll_ext_dual_lp_en 628 {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en 629 {0x40,0x0000,0x2000},//reg_lpll_ext_en_mini 630 {0x40,0x0400,0x0400},//reg_lpll1_ext_en_fifo 631 {0x4A,0x0000,0x8000},//reg_lpll_ext_test[15] 632 {0x4B,0x0000,0x0001},//reg_lpll_ext_test[16] 633 {0x4B,0x0000,0x0040},//reg_lpll_ext_test[22] 634 {0x59,0x4000,0x4000},//reg_lpll2_ext_nossc_pd 635 {0x58,0x0000,0x4000},//reg_lpll2_ext_ibias_ictrl 636 {0x58,0x0000,0x001F},//reg_lpll2_ext_input_div_first 637 {0x58,0x0000,0x0060},//reg_lpll2_ext_loop_div_first 638 {0x58,0x0000,0x1F00},//reg_lpll2_ext_loop_div_second 639 {0x5A,0x0000,0x000F},//reg_lpll2_ext_output_div_first 640 {0x59,0x0000,0x0800},//reg_lpll2_ext_test[11] 641 {0x59,0x0000,0x1000},//reg_lpll2_ext_test[12] 642 {0x59,0x0000,0x0100},//reg_lpll2_ext_test[8] 643 {0x5A,0x0000,0x2000},//reg_lpll_ext_2ndpll_clk_sel 644 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 645 {0x5A,0x0000,0x0200},//reg_lpll_ext_scalar2fifo_en 646 {0x5A,0x0000,0x0100},//reg_lpll_scalar2fifo_div2 647 }, 648 649 { //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_100to150MHz NO.15 650 //Address,Value,Mask 651 {0x59,0x0000,0x2000},//reg_lpll1_nossc_pd 652 {0x40,0x0001,0x0007},//reg_lpll_ext_ictrl 653 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 654 {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst 655 {0x41,0x0300,0x0F00},//reg_lpll_ext_loop_div_sec 656 {0x42,0x0000,0x0003},//reg_lpll_ext_scalar_div_fst 657 {0x42,0x0070,0x00F0},//reg_lpll_ext_scalar_div_sec 658 {0x43,0x0000,0x0007},//reg_lpll_ext_skew_div 659 {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div 660 {0x40,0x0000,0x1000},//reg_lpll_ext_fifo_div5_en 661 {0x5A,0x0040,0x0040},//reg_lpll_ext_en_fix_clk 662 {0x40,0x0000,0x0800},//reg_lpll_ext_dual_lp_en 663 {0x40,0x0000,0x0100},//reg_lpll_ext_sdiv2p5_en 664 {0x40,0x2000,0x2000},//reg_lpll_ext_en_mini 665 {0x40,0x0000,0x0400},//reg_lpll1_ext_en_fifo 666 {0x4A,0x0000,0x8000},//reg_lpll_ext_test[15] 667 {0x4B,0x0000,0x0001},//reg_lpll_ext_test[16] 668 {0x4B,0x0000,0x0040},//reg_lpll_ext_test[22] 669 {0x59,0x4000,0x4000},//reg_lpll2_ext_nossc_pd 670 {0x58,0x0000,0x4000},//reg_lpll2_ext_ibias_ictrl 671 {0x58,0x0000,0x001F},//reg_lpll2_ext_input_div_first 672 {0x58,0x0000,0x0060},//reg_lpll2_ext_loop_div_first 673 {0x58,0x0000,0x1F00},//reg_lpll2_ext_loop_div_second 674 {0x5A,0x0000,0x000F},//reg_lpll2_ext_output_div_first 675 {0x59,0x0000,0x0800},//reg_lpll2_ext_test[11] 676 {0x59,0x0000,0x1000},//reg_lpll2_ext_test[12] 677 {0x59,0x0000,0x0100},//reg_lpll2_ext_test[8] 678 {0x5A,0x0000,0x2000},//reg_lpll_ext_2ndpll_clk_sel 679 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 680 {0x5A,0x0000,0x0200},//reg_lpll_ext_scalar2fifo_en 681 {0x5A,0x0000,0x0100},//reg_lpll_scalar2fifo_div2 682 }, 683 684 { //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_50to100MHz NO.16 685 //Address,Value,Mask 686 {0x59,0x0000,0x2000},//reg_lpll1_nossc_pd 687 {0x40,0x0001,0x0007},//reg_lpll_ext_ictrl 688 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 689 {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst 690 {0x41,0x0300,0x0F00},//reg_lpll_ext_loop_div_sec 691 {0x42,0x0001,0x0003},//reg_lpll_ext_scalar_div_fst 692 {0x42,0x0070,0x00F0},//reg_lpll_ext_scalar_div_sec 693 {0x43,0x0001,0x0007},//reg_lpll_ext_skew_div 694 {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div 695 {0x40,0x0000,0x1000},//reg_lpll_ext_fifo_div5_en 696 {0x5A,0x0040,0x0040},//reg_lpll_ext_en_fix_clk 697 {0x40,0x0000,0x0800},//reg_lpll_ext_dual_lp_en 698 {0x40,0x0000,0x0100},//reg_lpll_ext_sdiv2p5_en 699 {0x40,0x2000,0x2000},//reg_lpll_ext_en_mini 700 {0x40,0x0000,0x0400},//reg_lpll1_ext_en_fifo 701 {0x4A,0x0000,0x8000},//reg_lpll_ext_test[15] 702 {0x4B,0x0000,0x0001},//reg_lpll_ext_test[16] 703 {0x4B,0x0000,0x0040},//reg_lpll_ext_test[22] 704 {0x59,0x4000,0x4000},//reg_lpll2_ext_nossc_pd 705 {0x58,0x0000,0x4000},//reg_lpll2_ext_ibias_ictrl 706 {0x58,0x0000,0x001F},//reg_lpll2_ext_input_div_first 707 {0x58,0x0000,0x0060},//reg_lpll2_ext_loop_div_first 708 {0x58,0x0000,0x1F00},//reg_lpll2_ext_loop_div_second 709 {0x5A,0x0000,0x000F},//reg_lpll2_ext_output_div_first 710 {0x59,0x0000,0x0800},//reg_lpll2_ext_test[11] 711 {0x59,0x0000,0x1000},//reg_lpll2_ext_test[12] 712 {0x59,0x0000,0x0100},//reg_lpll2_ext_test[8] 713 {0x5A,0x0000,0x2000},//reg_lpll_ext_2ndpll_clk_sel 714 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 715 {0x5A,0x0000,0x0200},//reg_lpll_ext_scalar2fifo_en 716 {0x5A,0x0000,0x0100},//reg_lpll_scalar2fifo_div2 717 }, 718 719 { //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_25to50MHz NO.17 720 //Address,Value,Mask 721 {0x59,0x0000,0x2000},//reg_lpll1_nossc_pd 722 {0x40,0x0001,0x0007},//reg_lpll_ext_ictrl 723 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 724 {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst 725 {0x41,0x0300,0x0F00},//reg_lpll_ext_loop_div_sec 726 {0x42,0x0002,0x0003},//reg_lpll_ext_scalar_div_fst 727 {0x42,0x0070,0x00F0},//reg_lpll_ext_scalar_div_sec 728 {0x43,0x0002,0x0007},//reg_lpll_ext_skew_div 729 {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div 730 {0x40,0x0000,0x1000},//reg_lpll_ext_fifo_div5_en 731 {0x5A,0x0040,0x0040},//reg_lpll_ext_en_fix_clk 732 {0x40,0x0000,0x0800},//reg_lpll_ext_dual_lp_en 733 {0x40,0x0000,0x0100},//reg_lpll_ext_sdiv2p5_en 734 {0x40,0x2000,0x2000},//reg_lpll_ext_en_mini 735 {0x40,0x0000,0x0400},//reg_lpll1_ext_en_fifo 736 {0x4A,0x0000,0x8000},//reg_lpll_ext_test[15] 737 {0x4B,0x0000,0x0001},//reg_lpll_ext_test[16] 738 {0x4B,0x0000,0x0040},//reg_lpll_ext_test[22] 739 {0x59,0x4000,0x4000},//reg_lpll2_ext_nossc_pd 740 {0x58,0x0000,0x4000},//reg_lpll2_ext_ibias_ictrl 741 {0x58,0x0000,0x001F},//reg_lpll2_ext_input_div_first 742 {0x58,0x0000,0x0060},//reg_lpll2_ext_loop_div_first 743 {0x58,0x0000,0x1F00},//reg_lpll2_ext_loop_div_second 744 {0x5A,0x0000,0x000F},//reg_lpll2_ext_output_div_first 745 {0x59,0x0000,0x0800},//reg_lpll2_ext_test[11] 746 {0x59,0x0000,0x1000},//reg_lpll2_ext_test[12] 747 {0x59,0x0000,0x0100},//reg_lpll2_ext_test[8] 748 {0x5A,0x0000,0x2000},//reg_lpll_ext_2ndpll_clk_sel 749 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 750 {0x5A,0x0000,0x0200},//reg_lpll_ext_scalar2fifo_en 751 {0x5A,0x0000,0x0100},//reg_lpll_scalar2fifo_div2 752 }, 753 754 { //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_25to25MHz NO.18 755 //Address,Value,Mask 756 {0x59,0x0000,0x2000},//reg_lpll1_nossc_pd 757 {0x40,0x0001,0x0007},//reg_lpll_ext_ictrl 758 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 759 {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst 760 {0x41,0x0300,0x0F00},//reg_lpll_ext_loop_div_sec 761 {0x42,0x0002,0x0003},//reg_lpll_ext_scalar_div_fst 762 {0x42,0x0070,0x00F0},//reg_lpll_ext_scalar_div_sec 763 {0x43,0x0002,0x0007},//reg_lpll_ext_skew_div 764 {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div 765 {0x40,0x0000,0x1000},//reg_lpll_ext_fifo_div5_en 766 {0x5A,0x0040,0x0040},//reg_lpll_ext_en_fix_clk 767 {0x40,0x0000,0x0800},//reg_lpll_ext_dual_lp_en 768 {0x40,0x0000,0x0100},//reg_lpll_ext_sdiv2p5_en 769 {0x40,0x2000,0x2000},//reg_lpll_ext_en_mini 770 {0x40,0x0000,0x0400},//reg_lpll1_ext_en_fifo 771 {0x4A,0x0000,0x8000},//reg_lpll_ext_test[15] 772 {0x4B,0x0000,0x0001},//reg_lpll_ext_test[16] 773 {0x4B,0x0000,0x0040},//reg_lpll_ext_test[22] 774 {0x59,0x4000,0x4000},//reg_lpll2_ext_nossc_pd 775 {0x58,0x0000,0x4000},//reg_lpll2_ext_ibias_ictrl 776 {0x58,0x0000,0x001F},//reg_lpll2_ext_input_div_first 777 {0x58,0x0000,0x0060},//reg_lpll2_ext_loop_div_first 778 {0x58,0x0000,0x1F00},//reg_lpll2_ext_loop_div_second 779 {0x5A,0x0000,0x000F},//reg_lpll2_ext_output_div_first 780 {0x59,0x0000,0x0800},//reg_lpll2_ext_test[11] 781 {0x59,0x0000,0x1000},//reg_lpll2_ext_test[12] 782 {0x59,0x0000,0x0100},//reg_lpll2_ext_test[8] 783 {0x5A,0x0000,0x2000},//reg_lpll_ext_2ndpll_clk_sel 784 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 785 {0x5A,0x0000,0x0200},//reg_lpll_ext_scalar2fifo_en 786 {0x5A,0x0000,0x0100},//reg_lpll_scalar2fifo_div2 787 }, 788 789 }; 790 MS_U16 u16EXT_LoopGain[E_PNL_SUPPORTED_LPLL_EXT_MAX]= 791 { 792 32, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_10BIT_4LANE_150to340MHz NO.0 793 32, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_10BIT_4LANE_150to150MHz NO.1 794 32, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_10BIT_2LANE_75to150MHz NO.2 795 32, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_10BIT_2LANE_75to75MHz NO.3 796 32, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_10BIT_1LANE_37_5to75MHz NO.4 797 32, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_10BIT_1LANE_37_5to37_5MHz NO.5 798 64, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_4LANE_200to340MHz NO.6 799 32, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_4LANE_150to200MHz NO.7 800 32, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_4LANE_150to150MHz NO.8 801 32, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_2LANE_100to150MHz NO.9 802 32, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_2LANE_75to100MHz NO.10 803 32, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_2LANE_75to75MHz NO.11 804 32, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_1LANE_50to75MHz NO.12 805 32, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_1LANE_37_5to50MHz NO.13 806 32, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_1LANE_37_5to37_5MHz NO.14 807 12, //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_100to150MHz NO.15 808 12, //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_50to100MHz NO.16 809 12, //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_25to50MHz NO.17 810 12, //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_25to25MHz NO.18 811 }; 812 MS_U16 u16EXT_LoopDiv[E_PNL_SUPPORTED_LPLL_EXT_MAX]= 813 { 814 10, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_10BIT_4LANE_150to340MHz NO.0 815 10, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_10BIT_4LANE_150to150MHz NO.1 816 20, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_10BIT_2LANE_75to150MHz NO.2 817 20, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_10BIT_2LANE_75to75MHz NO.3 818 40, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_10BIT_1LANE_37_5to75MHz NO.4 819 40, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_10BIT_1LANE_37_5to37_5MHz NO.5 820 15, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_4LANE_200to340MHz NO.6 821 15, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_4LANE_150to200MHz NO.7 822 15, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_4LANE_150to150MHz NO.8 823 15, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_2LANE_100to150MHz NO.9 824 30, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_2LANE_75to100MHz NO.10 825 30, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_2LANE_75to75MHz NO.11 826 30, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_1LANE_50to75MHz NO.12 827 60, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_1LANE_37_5to50MHz NO.13 828 60, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_8BIT_1LANE_37_5to37_5MHz NO.14 829 7, //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_100to150MHz NO.15 830 14, //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_50to100MHz NO.16 831 28, //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_25to50MHz NO.17 832 28, //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_25to25MHz NO.18 833 }; 834 835 #endif //_LPLL_TBL_H_ 836