1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34 // kind. Any warranties are hereby expressly disclaimed by MStar, including 35 // without limitation, any warranties of merchantability, non-infringement of 36 // intellectual property rights, fitness for a particular purpose, error free 37 // and in conformity with any international standard. You agree to waive any 38 // claim against MStar for any loss, damage, cost or expense that you may 39 // incur related to your use of MStar Software. 40 // In no event shall MStar be liable for any direct, indirect, incidental or 41 // consequential damages, including without limitation, lost of profit or 42 // revenues, lost or damage of data, and unauthorized system use. 43 // You agree that this Section 4 shall still apply without being affected 44 // even if MStar Software has been modified by MStar in accordance with your 45 // request or instruction for your use, except otherwise agreed by both 46 // parties in writing. 47 // 48 // 5. If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 // All rights reserved. 79 // 80 // Unless otherwise stipulated in writing, any and all information contained 81 // herein regardless in any format shall remain the sole proprietary of 82 // MStar Semiconductor Inc. and be kept in strict confidence 83 // ("MStar Confidential Information") by the recipient. 84 // Any unauthorized act including without limitation unauthorized disclosure, 85 // copying, use, reproduction, sale, distribution, modification, disassembling, 86 // reverse engineering and compiling of the contents of MStar Confidential 87 // Information is unlawful and strictly prohibited. MStar hereby reserves the 88 // rights to any and all damages, losses, costs and expenses resulting therefrom. 89 // 90 //////////////////////////////////////////////////////////////////////////////// 91 //============================================================================== 92 // [mhal_mux.h] 93 // Date: 20090220 94 // Descriptions: Add a new mux layer for HW setting 95 //============================================================================== 96 #ifndef MHAL_MUX_H 97 #define MHAL_MUX_H 98 99 /////////////////////////////// 100 // Mux Hardware Option 101 /////////////////////////////// 102 // Please set this #define after Mux tree is ready 103 #define MUX_TREE_HEIGHT 4 104 105 #define NUMBER_OF_ANALOG_PORT 3 106 #define NUMBER_OF_CVBS_PORT 11 107 #define NUMBER_OF_DVI_PORT 4 108 #define NUMBER_OF_MVOP_PORT 2 109 #define NUMBER_OF_CVBS_OUT_PORT 2 110 #define NUMBER_OF_YPBPR_OUT_PORT 0 111 #define PIP_SUPPORTED (MAX_WINDOW_NUM > 1) 112 #define NUMBER_OF_SCALER_OP_PORT 1 113 114 #define HAL_DVI_IP_A 0 //alex_tung 115 #define HAL_DVI_IP_B 1 116 #define HAL_DVI_IP_C 2 117 #define HAL_DVI_IP_D 3 118 119 /* 120 Input ports. 121 It is interface between Hal and Driver level. 122 */ 123 124 typedef enum 125 { 126 HAL_INPUTPORT_NONE = INPUT_PORT_NONE_PORT, 127 128 HAL_INPUTPORT_ANALOG0 = INPUT_PORT_ANALOG0, 129 HAL_INPUTPORT_ANALOG1, 130 HAL_INPUTPORT_ANALOG2, 131 132 HAL_INPUTPORT_ANALOG_SYNC0 = INPUT_PORT_ANALOG0_SYNC, 133 HAL_INPUTPORT_ANALOG_SYNC1, 134 HAL_INPUTPORT_ANALOG_SYNC2, 135 HAL_INPUTPORT_ANALOG_SYNC3, 136 137 HAL_INPUTPORT_YMUX_CVBS0 = INPUT_PORT_YMUX_CVBS0, 138 HAL_INPUTPORT_YMUX_CVBS1, 139 HAL_INPUTPORT_YMUX_CVBS2, 140 HAL_INPUTPORT_YMUX_CVBS3, 141 HAL_INPUTPORT_YMUX_CVBS4, 142 HAL_INPUTPORT_YMUX_CVBS5, 143 HAL_INPUTPORT_YMUX_CVBS6, 144 HAL_INPUTPORT_YMUX_CVBS7, 145 HAL_INPUTPORT_YMUX_G0, 146 HAL_INPUTPORT_YMUX_G1, 147 HAL_INPUTPORT_YMUX_G2, 148 149 HAL_INPUTPORT_CMUX_CVBS0 = INPUT_PORT_CMUX_CVBS0, 150 HAL_INPUTPORT_CMUX_CVBS1, 151 HAL_INPUTPORT_CMUX_CVBS2, 152 HAL_INPUTPORT_CMUX_CVBS3, 153 HAL_INPUTPORT_CMUX_CVBS4, 154 HAL_INPUTPORT_CMUX_CVBS5, 155 HAL_INPUTPORT_CMUX_CVBS6, 156 HAL_INPUTPORT_CMUX_CVBS7, 157 HAL_INPUTPORT_CMUX_R0, 158 HAL_INPUTPORT_CMUX_R1, 159 HAL_INPUTPORT_CMUX_R2, 160 161 HAL_INPUTPORT_DVI0 = INPUT_PORT_DVI0, 162 HAL_INPUTPORT_DVI1, 163 HAL_INPUTPORT_DVI2, 164 HAL_INPUTPORT_DVI3, 165 166 HAL_INPUTPORT_MVOP = INPUT_PORT_MVOP, 167 HAL_INPUTPORT_MVOP2, 168 169 HAL_INPUTPORT_SCALER_OP = INPUT_PORT_SCALER_OP, 170 } E_INPUT_PORT_TYPE; 171 172 // Output ports. 173 174 175 typedef enum 176 { 177 HAL_OUTPUTPORT_NONE_PORT = OUTPUT_PORT_NONE_PORT, 178 179 HAL_OUTPUTPORT_SCALER_MAIN_WINDOW = OUTPUT_PORT_SCALER_MAIN_WINDOW, 180 HAL_OUTPUTPORT_SCALER2_MAIN_WINDOW = OUTPUT_PORT_SCALER2_MAIN_WINDOW, 181 182 HAL_OUTPUTPORT_SCALER_SUB_WINDOW1 = OUTPUT_PORT_SCALER_SUB_WINDOW1, 183 HAL_OUTPUTPORT_SCALER2_SUB_WINDOW = OUTPUT_PORT_SCALER2_SUB_WINDOW, 184 185 HAL_OUTPUTPORT_CVBS1 = OUTPUT_PORT_CVBS1, 186 HAL_OUTPUTPORT_CVBS2 , 187 188 HAL_OUTPUTPORT_YPBPR1 = OUTPUT_PORT_YPBPR1, 189 190 HAL_OUTPUTPORT_DIP_WINDOW = OUTPUT_PORT_DWIN, 191 192 193 }E_OUTPUT_PORT_TYPE; 194 195 typedef enum 196 { 197 SC_MAINWIN_IPMUX_ADC_A = 0, ///< ADC A 198 SC_MAINWIN_IPMUX_HDMI_DVI = 1, ///< DVI 199 SC_MAINWIN_IPMUX_VD = 2, ///< VD 200 SC_MAINWIN_IPMUX_MVOP = 3, ///< MPEG/DC0 201 SC_MAINWIN_IPMUX_SC_VOP = 4, ///< Scaler VOP output 202 SC_MAINWIN_IPMUX_EXT_VD = 5, ///< External VD 203 SC_MAINWIN_IPMUX_ADC_B = 6, ///< ADC B 204 SC_MAINWIN_IPMUX_CAPTURE = 7, ///< Capture 205 SC_MAINWIN_IPMUX_MVOP2 = 8, ///< MPEG/DC1 206 SC_MAINWIN_IPMUX_IP_SUB = 9, ///< IP SUB/VE 207 SC_MAINWIN_IPMUX_NOUSE = 10, ///< no use now 208 SC_MAINWIN_IPMUX_DC2 = 11, ///< DC2 209 SC_MAINWIN_IPMUX_IP_SUB2 = 12, ///< IP SUB2/DIP 210 SC_MAINWIN_IPMUX_MHL = 13, ///< MHL 211 SC_MAINWIN_IPMUX_VD2 = 14, ///< VD2 212 } SC_MAINWIN_IPMUX_TYPE; 213 214 typedef enum 215 { 216 SC_SUBWIN_IPMUX_ADC_A = 0, ///< ADC A 217 SC_SUBWIN_IPMUX_HDMI_DVI = 1, ///< DVI 218 SC_SUBWIN_IPMUX_VD = 2, ///< VD 219 SC_SUBWIN_IPMUX_MVOP = 3, ///< MPEG/DC0 220 SC_SUBWIN_IPMUX_SC_VOP = 4, ///< Scaler VOP output 221 SC_SUBWIN_IPMUX_EXT_VD = 5, ///< External VD 222 SC_SUBWIN_IPMUX_ADC_B = 6, ///< ADC B 223 SC_SUBWIN_IPMUX_MLINK = 8, ///< MLink 224 SC_SUBWIN_IPMUX_CAPTURE = 7, ///< Capture 225 SC_SUBWIN_IPMUX_MVOP2 = 8, ///< MPEG/DC1 226 SC_SUBWIN_IPMUX_IP_SUB = 9, ///< IP SUB/VE 227 SC_SUBWIN_IPMUX_NOUSE = 10, ///< no use now 228 SC_SUBWIN_IPMUX_DC2 = 11, ///< DC2 229 SC_SUBWIN_IPMUX_IP_SUB2 = 12, ///< IP SUB2/DIP 230 SC_SUBWIN_IPMUX_MHL = 13, ///< MHL 231 SC_SUBWIN_IPMUX_VD2 = 14, ///< VD2 232 } SC_SUBWIN_IPMUX_TYPE; 233 234 typedef enum 235 { 236 SC_CLK_ADC_A = 0, ///< ADC A 237 SC_CLK_HDMI_DVI = 1, ///< DVI 238 SC_CLK_VD = 2, ///< VD 239 SC_CLK_DC0 = 3, ///< MPEG/DC0 240 SC_CLK_ADC_B = 4, ///< ADC_B 241 242 SC_CLK_ODCLK = 7, ///< ODLCK 243 SC_CLK_DC1 = 8, ///< MPEG/DC1 244 SC_CLK_ADC_C = 9, ///< ADC 245 SC_CLK_ODCLK_B = 10, ///<ODCLK 246 SC_CLK_MHL = 11, ///<MHL 247 } SC_IDCLK_TYPE; 248 249 typedef enum 250 { 251 SC_OFFLINE_IPMUX_ADC_A = 0, ///< ADC A 252 SC_OFFLINE_IPMUX_HDMI_DVI = 1, ///< DVI 253 SC_OFFLINE_IPMUX_VD = 2, ///< VD 254 SC_OFFLINE_IPMUX_MVOP = 3, ///< MPEG/DC0 255 SC_OFFLINE_IPMUX_SC_VOP = 4, ///< Scaler VOP output 256 SC_OFFLINE_IPMUX_EXT_VD = 5, ///< External VD 257 SC_OFFLINE_IPMUX_ADC_B = 6, ///< ADC B 258 SC_OFFLINE_IPMUX_CAPTURE = 7, ///< Capture 259 SC_OFFLINE_IPMUX_MVOP2 = 8, ///< MPEG/DC1 260 SC_OFFLINE_IPMUX_IP_SUB = 9, ///< IP SUB/VE 261 SC_OFFLINE_IPMUX_NOUSE = 10, ///< no use now 262 SC_OFFLINE_IPMUX_DC2 = 11, ///< DC2 263 SC_OFFLINE_IPMUX_IP_SUB2 = 12, ///< IP SUB2/DIP 264 SC_OFFLINE_IPMUX_MHL = 13, ///< MHL 265 } SC_OFFLINE_IPMUX_TYPE; 266 267 typedef enum 268 { 269 SC_DWIN_IPMUX_ADC_A = 0, ///< ADC A 270 SC_DWIN_IPMUX_HDMI_DVI = 1, ///< DVI 271 SC_DWIN_IPMUX_VD = 2, ///< VD 272 SC_DWIN_IPMUX_MVOP = 3, ///< MPEG/DC0 273 SC_DWIN_IPMUX_SC_VOP = 4, ///< Scaler VOP output 274 SC_DWIN_IPMUX_EXT_VD = 5, ///< External VD 275 SC_DWIN_IPMUX_ADC_B = 6, ///< ADC B 276 SC_DWIN_IPMUX_MLINK = 8, ///< MLink 277 SC_DWIN_IPMUX_CAPTURE = 7, ///< Capture 278 SC_DWIN_IPMUX_MVOP2 = 8, ///< MPEG/DC1 279 SC_DWIN_IPMUX_IP_SUB = 9, ///< IP SUB/VE 280 SC_DWIN_IPMUX_NOUSE = 10, ///< no use now 281 SC_DWIN_IPMUX_DC2 = 11, ///< DC2 282 SC_DWIN_IPMUX_IP_SUB2 = 12, ///< IP SUB2/DIP 283 SC_DWIN_IPMUX_MHL = 13, ///< MHL 284 SC_DWIN_IPMUX_VD2 = 14, ///< VD2 285 } SC_DWIN_IPMUX_TYPE; 286 287 typedef enum 288 { 289 SC2_MAINWIN_IPMUX_ADC_A = 0, ///< ADC A 290 SC2_MAINWIN_IPMUX_HDMI_DVI = 1, ///< DVI 291 SC2_MAINWIN_IPMUX_VD = 2, ///< VD 292 SC2_MAINWIN_IPMUX_MVOP = 3, ///< MPEG/DC0 293 294 SC2_MAINWIN_IPMUX_CAPTURE = 7, ///< Capture 295 SC2_MAINWIN_IPMUX_MVOP2 = 8, ///< MPEG/DC1 296 297 SC2_MAINWIN_IPMUX_SPT4K_CH0 = 11, ///< 4K spliter ch0 298 299 SC2_MAINWIN_IPMUX_MHL = 13, ///< MHL 300 SC2_MAINWIN_IPMUX_SPT4K_CH1 = 14, ///< 4K spliter ch1 301 } SC2_MAINWIN_IPMUX_TYPE; 302 303 typedef enum 304 { 305 SC2_CLK_ADC_A = 0, ///< ADC A 306 SC2_CLK_HDMI_DVI = 1, ///< DVI 307 SC2_CLK_VD = 2, ///< VD 308 SC2_CLK_DC0 = 3, ///< MPEG/DC0 309 SC2_CLK_ADC_B = 4, ///< ADC_B 310 311 SC2_CLK_ODCLK = 7, ///< ODLCK 312 SC2_CLK_DC1 = 8, ///< MPEG/DC1 313 SC2_CLK_ADC_C = 9, ///< ADC 314 SC2_CLK_ODCLK_B = 10, ///<ODCLK 315 SC2_CLK_MHL = 13, ///<MHL 316 } SC2_IDCLK_TYPE; 317 318 void Hal_SC_mux_dispatch(void *pInstance, E_MUX_INPUTPORT src , E_MUX_OUTPUTPORT dest); 319 void Hal_SC_mux_set_dvi_mux(void *pInstance, MS_U8 PortId, E_OUTPUT_PORT_TYPE enDstPort); 320 void Hal_SC_mux_set_adc_y_mux(void *pInstance, MS_U8 PortId); 321 void Hal_SC_mux_set_adc_c_mux(void *pInstance, MS_U8 PortId); 322 void Hal_SC_set_sync_port_by_dataport(void *pInstance, E_MUX_INPUTPORT src_port ); 323 324 void Hal_SC_mux_set_mainwin_ip_mux(void *pInstance, MS_U8 u8Data_Mux, MS_U8 u8Clk_Mux); 325 MS_BOOL Hal_SC_mux_get_mainwin_ip_mux(void *pInstance, MS_U8 *pU8Data_Mux, MS_U8 *pU8Clk_Mux); 326 void Hal_SC_set_subwin_ip_mux(void *pInstance, MS_U8 u8Data_Mux, MS_U8 u8Clk_Mux); 327 void Hal_SC_mux_set_dipwin_ip_mux(void *pInstance, MS_U8 u8Data_Mux, MS_U8 u8Clk_Mux); 328 void Hal_SC_EnableCLK_for_DIP(void *pInstance, MS_BOOL bEnable); 329 330 void Hal_SC2_mux_set_mainwin_ip_mux(void *pInstance, MS_U8 u8Data_Mux, MS_U8 u8Clk_Mux); 331 MS_BOOL Hal_SC2_mux_get_mainwin_ip_mux(void *pInstance, MS_U8 *pU8Data_Mux, MS_U8 *pU8Clk_Mux); 332 void Hal_SC_mux_SetScalerIndexInformationToADC(void *pInstance, MS_U8 u8ScalerIndex, MS_U16 u16InputSourceType); 333 334 #endif // MHAL_MUX_H 335