1 #include "hwreg_frc_map.h"
2 #include "Maserati_ACT_4K1K.h"
3
4 // ACT_4K1K
5 // 3D_4K1K_ACT_NO_FRC
MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC(void)6 void MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC(void)
7 {
8 // FSC_TOP
9 MDrv_WriteByteMask( REG_FSC_BK20_A2, 0x80, 0xff); // reg_splt_gb_in_size_r
10 MDrv_WriteByteMask( REG_FSC_BK20_A3, 0x00, 0x01); // reg_splt_gb_in_size_r
11 MDrv_WriteByteMask( REG_FSC_BK20_A4, 0x00, 0xff); // reg_splt_h_size
12 MDrv_WriteByteMask( REG_FSC_BK20_A5, 0x0f, 0x1f); // reg_splt_h_size
13 MDrv_WriteByteMask( REG_FSC_BK20_A6, 0x80, 0xff); // reg_splt_h_size_l
14 MDrv_WriteByteMask( REG_FSC_BK20_A7, 0x07, 0x0f); // reg_splt_h_size_l
15 MDrv_WriteByteMask( REG_FSC_BK20_A8, 0x80, 0x80); // reg_mcm_lr_en
16 MDrv_WriteByteMask( REG_FSC_BK20_49, 0x08, 0x0f); // reg_vertical_limit_cnt
17 MDrv_WriteByteMask( REG_FSC_BK20_48, 0x70, 0xff); // reg_vertical_limit_cnt
18 MDrv_WriteByteMask( REG_FSC_BK20_1D, 0x00, 0x1f); // reg_hde_st
19 MDrv_WriteByteMask( REG_FSC_BK20_1C, 0x00, 0xff); // reg_hde_st
20 MDrv_WriteByteMask( REG_FSC_BK20_1F, 0x00, 0x0f); // reg_vde_st
21 MDrv_WriteByteMask( REG_FSC_BK20_1E, 0x00, 0xff); // reg_vde_st
22 MDrv_WriteByteMask( REG_FSC_BK20_C1, 0x04, 0x04); // reg_de_h_mask_en
23 MDrv_WriteByteMask( REG_FSC_BK20_C1, 0x08, 0x08); // reg_de_v_mask_en
24 MDrv_WriteByteMask( REG_FSC_BK20_C1, 0x00, 0x10); // reg_hvmask_en
25 MDrv_WriteByteMask( REG_FSC_BK20_C1, 0x00, 0x20); // reg_mask_hcnt_sel
26 MDrv_WriteByteMask( REG_FSC_BK20_C1, 0x00, 0x40); // reg_mask_vcnt_sel
27 MDrv_WriteByteMask( REG_FSC_BK20_CA, 0x00, 0x01); // reg_path_selection
28 MDrv_WriteByteMask( REG_FSC_BK20_05, 0x10, 0x10); // reg_ckg_ficlk
29 MDrv_WriteByteMask( REG_FSC_BK20_04, 0x0C, 0x1f); // reg_ckg_odclk
30 // CSC
31 // DD
32 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x00, 0xff); // reg_dd_pixel_num (H)
33 MDrv_WriteByteMask( REG_FSC_BK1D_03, 0x08, 0x0f); // reg_dd_pixel_num
34 MDrv_WriteByteMask( REG_FSC_BK1D_04, 0x70, 0xff); // reg_dd_line_num (V)
35 MDrv_WriteByteMask( REG_FSC_BK1D_05, 0x08, 0x0f); // reg_dd_line_num
36 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x40, 0x7f); // reg_flh_last_ctr
37 MDrv_WriteByteMask( REG_FSC_BK1D_0B, 0x40, 0x7f); // reg_flh_req_ctr
38 MDrv_WriteByteMask( REG_FSC_BK1D_0D, 0x00, 0x40); // reg_blk_md
39 // MCNR
40 MDrv_WriteByteMask( REG_FSC_BK20_20, 0x00, 0xff); // reg_fetch_num
41 MDrv_WriteByteMask( REG_FSC_BK20_21, 0x08, 0xff); // reg_fetch_num
42 MDrv_WriteByteMask( REG_FSC_BK20_22, 0x70, 0xff); // reg_vlen
43 MDrv_WriteByteMask( REG_FSC_BK20_23, 0x08, 0xff); // reg_vlen
44 // MCM
45 MDrv_WriteByteMask( REG_FSC_BK12_1C, 0x80, 0xff); // reg_mcm_offset
46 MDrv_WriteByteMask( REG_FSC_BK12_1D, 0x07, 0x1f); // reg_mcm_offset
47 MDrv_WriteByteMask( REG_FSC_BK12_1E, 0x80, 0xff); // reg_mcm_fetch
48 MDrv_WriteByteMask( REG_FSC_BK12_1F, 0x07, 0x1f); // reg_mcm_fetch
49 MDrv_WriteByteMask( REG_FSC_BK12_60, 0x00, 0x0C); // reg_mcm_fi
50 MDrv_WriteByteMask( REG_FSC_BK12_2F, 0x80, 0x80); // reg_ipm_cut_en
51 // VSU
52 MDrv_WriteByteMask( REG_FSC_BK23_12, 0x00, 0xff); // vsp_scl_fac0
53 MDrv_WriteByteMask( REG_FSC_BK23_13, 0x00, 0xff); // vsp_scl_fac1
54 MDrv_WriteByteMask( REG_FSC_BK23_14, 0x10, 0xff); // vsp_scl_fac2
55 MDrv_WriteByteMask( REG_FSC_BK23_15, 0x01, 0xff); // vsp_scl_en
56 MDrv_WriteByteMask( REG_FSC_BK23_15, 0x00, 0x02); // vsp_shift_mode_en
57 MDrv_WriteByteMask( REG_FSC_BK23_0A, 0x38, 0xff); // vsp_vsize_in0
58 MDrv_WriteByteMask( REG_FSC_BK23_0B, 0x04, 0xff); // vsp_vsize_in1
59 MDrv_WriteByteMask( REG_FSC_BK23_0C, 0x38, 0xff); // vsp_vsize_out0
60 MDrv_WriteByteMask( REG_FSC_BK23_0D, 0x04, 0xff); // vsp_vsize_out1
61 // HSU
62 MDrv_WriteByteMask( REG_FSC_BK23_0E, 0x00, 0xff); // hsp_scl_fac0
63 MDrv_WriteByteMask( REG_FSC_BK23_0F, 0x00, 0xff); // hsp_scl_fac1
64 MDrv_WriteByteMask( REG_FSC_BK23_10, 0x10, 0xff); // hsp_scl_fac2
65 MDrv_WriteByteMask( REG_FSC_BK23_11, 0x01, 0xff); // hsp_scl_en
66 MDrv_WriteByteMask( REG_FSC_BK23_11, 0x00, 0x02); // hsp_shift_mode_en
67 MDrv_WriteByteMask( REG_FSC_BK23_34, 0x80, 0xff); // hsp_hsize_in0
68 MDrv_WriteByteMask( REG_FSC_BK23_35, 0x07, 0xff); // hsp_hsize_in1
69 MDrv_WriteByteMask( REG_FSC_BK23_36, 0x80, 0xff); // hsp_hsize_out0
70 MDrv_WriteByteMask( REG_FSC_BK23_37, 0x07, 0xff); // hsp_hsize_out1
71 MDrv_WriteByteMask( REG_FSC_BK23_38, 0x80, 0xff); // gb_in_size
72 MDrv_WriteByteMask( REG_FSC_BK23_39, 0x00, 0x0f); // gb_in_size
73 MDrv_WriteByteMask( REG_FSC_BK23_39, 0x10, 0x10); // gb_in_en
74 MDrv_WriteByteMask( REG_FSC_BK23_3A, 0x80, 0xff); // gb_out_size
75 MDrv_WriteByteMask( REG_FSC_BK23_3B, 0x00, 0x0f); // gb_out_size
76 MDrv_WriteByteMask( REG_FSC_BK23_3B, 0x10, 0x10); // gb_out_en
77 MDrv_WriteByteMask( REG_FSC_BK23_3E, 0x04, 0x04); // hsize_half_en
78 MDrv_WriteByteMask( REG_FSC_BK23_3C, 0x00, 0xff); // hsp_mask_size
79 MDrv_WriteByteMask( REG_FSC_BK23_3D, 0x00, 0x01); // hsp_mask_size
80 // VIP
81 MDrv_WriteByteMask( REG_FSC_BK1B_1C, 0x00, 0xFF); // reg_vip_horizontal_num_lsb
82 MDrv_WriteByteMask( REG_FSC_BK1B_1D, 0x08, 0x0F); // reg_vip_horizontal_num_msb
83 MDrv_WriteByteMask( REG_FSC_BK1B_1E, 0x70, 0xFF); // reg_vip_vertical_num_lsb
84 MDrv_WriteByteMask( REG_FSC_BK1B_1F, 0x08, 0x1F); // reg_vip_vertical_num_msb
85 MDrv_WriteByteMask( REG_FSC_BK1B_1F, 0x00, 0x80); // reg_vip_tb_3d_en
86 // VIP_444to422
87 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x01); // reg_main_444to422_en
88 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en
89 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x40); // reg_main_444to422_filter
90 MDrv_WriteByteMask( REG_FSC_BK1B_11, 0x41, 0x01); // reg_sub_444to422_en
91 MDrv_WriteByteMask( REG_FSC_BK1B_11, 0x00, 0x02); // reg_sub_h_mirror_en
92 MDrv_WriteByteMask( REG_FSC_BK1B_11, 0x41, 0x40); // reg_sub_444to422_en
93 // SPTF_D2LR
94 MDrv_WriteByteMask( REG_FRC_BK33A_60 , 0x00, 0xff); // gb_cut_st_l
95 MDrv_WriteByteMask( REG_FRC_BK33A_61 , 0x00, 0xff); // gb_cut_st_l
96 MDrv_WriteByteMask( REG_FRC_BK33A_62 , 0x80, 0xff); // gb_cut_end_l
97 MDrv_WriteByteMask( REG_FRC_BK33A_63 , 0x07, 0xff); // gb_cut_end_l
98 MDrv_WriteByteMask( REG_FRC_BK33A_64 , 0x80, 0xff); // gb_cut_st_r
99 MDrv_WriteByteMask( REG_FRC_BK33A_65 , 0x00, 0xff); // gb_cut_st_r
100 MDrv_WriteByteMask( REG_FRC_BK33A_66 , 0xff, 0xff); // gb_cut_end_r
101 MDrv_WriteByteMask( REG_FRC_BK33A_67 , 0x1f, 0xff); // gb_cut_end_r
102 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass
103 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo
104 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr
105 MDrv_WriteByteMask( REG_FRC_BK33A_52 , 0x80, 0xff); // d2lr_output_h
106 MDrv_WriteByteMask( REG_FRC_BK33A_53 , 0x08, 0xff); // d2lr_output_h
107 MDrv_WriteByteMask( REG_FRC_BK33A_40 , 0x00, 0xff); // d2lr_w0_st
108 MDrv_WriteByteMask( REG_FRC_BK33A_41 , 0x00, 0xff); // d2lr_w0_st
109 MDrv_WriteByteMask( REG_FRC_BK33A_42 , 0xff, 0xff); // d2lr_w0_end
110 MDrv_WriteByteMask( REG_FRC_BK33A_43 , 0x0e, 0xff); // d2lr_w0_end
111 MDrv_WriteByteMask( REG_FRC_BK33A_44 , 0x00, 0xff); // d2lr_w1_st
112 MDrv_WriteByteMask( REG_FRC_BK33A_45 , 0x00, 0xff); // d2lr_w1_st
113 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end
114 MDrv_WriteByteMask( REG_FRC_BK33A_47 , 0x0e, 0xff); // d2lr_w1_end
115 MDrv_WriteByteMask( REG_FRC_BK33A_48 , 0x00, 0xff); // d2lr_r0_st
116 MDrv_WriteByteMask( REG_FRC_BK33A_49 , 0x00, 0xff); // d2lr_r0_st
117 MDrv_WriteByteMask( REG_FRC_BK33A_4A , 0x7f, 0xff); // d2lr_r0_end
118 MDrv_WriteByteMask( REG_FRC_BK33A_4B , 0x08, 0xff); // d2lr_r0_end
119 MDrv_WriteByteMask( REG_FRC_BK33A_4C , 0x80, 0xff); // d2lr_r1_st
120 MDrv_WriteByteMask( REG_FRC_BK33A_4D , 0x06, 0xff); // d2lr_r1_st
121 MDrv_WriteByteMask( REG_FRC_BK33A_4E , 0xff, 0xff); // d2lr_r1_end
122 MDrv_WriteByteMask( REG_FRC_BK33A_4F , 0x0e, 0xff); // d2lr_r1_end
123 // FSC_FBL
124 MDrv_WriteByteMask( REG_FSC_BK20_0E, 0x00, 0x01); // fbl_en
125 MDrv_WriteByteMask( REG_FSC_BK20_0C, 0x00, 0x03); // reg_ipm_lr_en
126 MDrv_WriteByteMask( REG_FSC_BK20_60, 0x00, 0x04); // 3d_sbs_en
127 MDrv_WriteByteMask( REG_FSC_BK20_60, 0x00, 0x01); // 3d_top_bot_en
128 // IPM_OPM
129 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2
130 MDrv_WriteByteMask( REG_FRC_BK134_1D , 0x07, 0xff); // ipm_offset_f2
131 MDrv_WriteByteMask( REG_FRC_BK134_1E , 0x80, 0xff); // ipm_fetch_f2
132 MDrv_WriteByteMask( REG_FRC_BK134_1F , 0x07, 0xff); // ipm_fetch_f2
133 MDrv_WriteByteMask( REG_FRC_BK134_04 , 0x00, 0xff); // ipm_mem_config_f2
134 MDrv_WriteByteMask( REG_FRC_BK134_05 , 0x01, 0xff); // ipm_mem_config_f2
135 MDrv_WriteByteMask( REG_FRC_BK13A_04 , 0x03, 0xff); // ipm_mem_config_f2
136 MDrv_WriteByteMask( REG_FRC_BK13A_05 , 0x31, 0xff); // ipm_mem_config_f2
137 MDrv_WriteByteMask( REG_FRC_BK13A_84 , 0x03, 0xff); // ipm_mem_config_f2
138 MDrv_WriteByteMask( REG_FRC_BK13A_85 , 0x31, 0xff); // ipm_mem_config_f2
139 MDrv_WriteByteMask( REG_FRC_BK134_9C , 0x80, 0xff); // ipm_fetch_f1
140 MDrv_WriteByteMask( REG_FRC_BK134_9D , 0x07, 0xff); // ipm_fetch_f1
141 MDrv_WriteByteMask( REG_FRC_BK134_9E , 0x80, 0xff); // ipm_offset_f1
142 MDrv_WriteByteMask( REG_FRC_BK134_9F , 0x07, 0xff); // ipm_offset_f1
143 MDrv_WriteByteMask( REG_FRC_BK134_84 , 0x00, 0xff); // ipm_mem_config_f1
144 MDrv_WriteByteMask( REG_FRC_BK134_85 , 0x01, 0xff); // ipm_mem_config_f1
145 MDrv_WriteByteMask( REG_FRC_BK134_2C , 0x80, 0xff); // opm_offset_f2
146 MDrv_WriteByteMask( REG_FRC_BK134_2D , 0x07, 0xff); // opm_offset_f2
147 MDrv_WriteByteMask( REG_FRC_BK134_2E , 0x80, 0xff); // opm_fetch_f2
148 MDrv_WriteByteMask( REG_FRC_BK134_2F , 0x07, 0xff); // opm_fetch_f2
149 MDrv_WriteByteMask( REG_FRC_BK134_30 , 0x38, 0xff); // reg_ipm_vcnt_limit_num_f2
150 MDrv_WriteByteMask( REG_FRC_BK134_31 , 0x04, 0xff); // reg_ipm_vcnt_limit_num_f2
151 MDrv_WriteByteMask( REG_FRC_BK136_2C , 0x80, 0xff); // opm_offset_f1
152 MDrv_WriteByteMask( REG_FRC_BK136_2D , 0x07, 0xff); // opm_offset_f1
153 MDrv_WriteByteMask( REG_FRC_BK136_2E , 0x80, 0xff); // opm_fetch_f1
154 MDrv_WriteByteMask( REG_FRC_BK136_2F , 0x07, 0xff); // opm_fetch_f1
155 MDrv_WriteByteMask( REG_FRC_BK136_30 , 0x38, 0xff); // reg_ipm_vcnt_limit_num_f2
156 MDrv_WriteByteMask( REG_FRC_BK136_31 , 0x04, 0xff); // reg_ipm_vcnt_limit_num_f2
157 MDrv_WriteByteMask( REG_FRC_BK13A_2C , 0x80, 0xff); // opm_offset_f2
158 MDrv_WriteByteMask( REG_FRC_BK13A_2D , 0x07, 0xff); // opm_offset_f2
159 MDrv_WriteByteMask( REG_FRC_BK13A_2E , 0x80, 0xff); // opm_fetch_f2
160 MDrv_WriteByteMask( REG_FRC_BK13A_2F , 0x07, 0xff); // opm_fetch_f2
161 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x38, 0xff); // reg_ipm_vcnt_limit_num_f2
162 MDrv_WriteByteMask( REG_FRC_BK13A_31 , 0x04, 0xff); // reg_ipm_vcnt_limit_num_f2
163 MDrv_WriteByteMask( REG_FRC_BK13B_2C , 0x80, 0xff); // opm_offset_f1
164 MDrv_WriteByteMask( REG_FRC_BK13B_2D , 0x07, 0xff); // opm_offset_f1
165 MDrv_WriteByteMask( REG_FRC_BK13B_2E , 0x80, 0xff); // opm_fetch_f1
166 MDrv_WriteByteMask( REG_FRC_BK13B_2F , 0x07, 0xff); // opm_fetch_f1
167 MDrv_WriteByteMask( REG_FRC_BK13B_30 , 0x38, 0xff); // reg_ipm_vcnt_limit_num_f2
168 MDrv_WriteByteMask( REG_FRC_BK13B_31 , 0x04, 0xff); // reg_ipm_vcnt_limit_num_f2
169 MDrv_WriteByteMask( REG_FRC_BK13C_2C , 0x80, 0xff); // opm_offset_f2
170 MDrv_WriteByteMask( REG_FRC_BK13C_2D , 0x07, 0xff); // opm_offset_f2
171 MDrv_WriteByteMask( REG_FRC_BK13C_2E , 0x80, 0xff); // opm_fetch_f2
172 MDrv_WriteByteMask( REG_FRC_BK13C_2F , 0x07, 0xff); // opm_fetch_f2
173 MDrv_WriteByteMask( REG_FRC_BK13C_30 , 0x38, 0xff); // reg_ipm_vcnt_limit_num_f2
174 MDrv_WriteByteMask( REG_FRC_BK13C_31 , 0x04, 0xff); // reg_ipm_vcnt_limit_num_f2
175 MDrv_WriteByteMask( REG_FRC_BK13D_2C , 0x80, 0xff); // opm_offset_f1
176 MDrv_WriteByteMask( REG_FRC_BK13D_2D , 0x07, 0xff); // opm_offset_f1
177 MDrv_WriteByteMask( REG_FRC_BK13D_2E , 0x80, 0xff); // opm_fetch_f1
178 MDrv_WriteByteMask( REG_FRC_BK13D_2F , 0x07, 0xff); // opm_fetch_f1
179 MDrv_WriteByteMask( REG_FRC_BK13D_30 , 0x38, 0xff); // reg_ipm_vcnt_limit_num_f2
180 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x04, 0xff); // reg_ipm_vcnt_limit_num_f2
181 // IPM_OPM_vlen
182 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel
183 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel
184 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel
185 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel
186 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel
187 MDrv_WriteByteMask( REG_FRC_BK13D_CD , 0x80, 0x80); // reg_opm_vlen_sel
188 MDrv_WriteByteMask( REG_FRC_BK134_62 , 0x38, 0xff); // reg_opm_vlen
189 MDrv_WriteByteMask( REG_FRC_BK134_63 , 0x04, 0x1f); // reg_opm_vlen
190 MDrv_WriteByteMask( REG_FRC_BK136_62 , 0x38, 0xff); // reg_opm_vlen
191 MDrv_WriteByteMask( REG_FRC_BK136_63 , 0x04, 0x1f); // reg_opm_vlen
192 MDrv_WriteByteMask( REG_FRC_BK13A_62 , 0x38, 0xff); // reg_opm_vlen
193 MDrv_WriteByteMask( REG_FRC_BK13A_63 , 0x04, 0x1f); // reg_opm_vlen
194 MDrv_WriteByteMask( REG_FRC_BK13B_62 , 0x38, 0xff); // reg_opm_vlen
195 MDrv_WriteByteMask( REG_FRC_BK13B_63 , 0x04, 0x1f); // reg_opm_vlen
196 MDrv_WriteByteMask( REG_FRC_BK13C_62 , 0x38, 0xff); // reg_opm_vlen
197 MDrv_WriteByteMask( REG_FRC_BK13C_63 , 0x04, 0x1f); // reg_opm_vlen
198 MDrv_WriteByteMask( REG_FRC_BK13D_62 , 0x38, 0xff); // reg_opm_vlen
199 MDrv_WriteByteMask( REG_FRC_BK13D_63 , 0x04, 0x1f); // reg_opm_vlen
200 MDrv_WriteByteMask( REG_FRC_BK134_CC , 0x70, 0xff); // reg_opm_vlen_new
201 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x08, 0x1f); // reg_opm_vlen_new
202 MDrv_WriteByteMask( REG_FRC_BK136_CC , 0x70, 0xff); // reg_opm_vlen_new
203 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x08, 0x1f); // reg_opm_vlen_new
204 MDrv_WriteByteMask( REG_FRC_BK13A_CC , 0x70, 0xff); // reg_opm_vlen_new
205 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x08, 0x1f); // reg_opm_vlen_new
206 MDrv_WriteByteMask( REG_FRC_BK13B_CC , 0x70, 0xff); // reg_opm_vlen_new
207 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x08, 0x1f); // reg_opm_vlen_new
208 MDrv_WriteByteMask( REG_FRC_BK13C_CC , 0x70, 0xff); // reg_opm_vlen_new
209 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x08, 0x1f); // reg_opm_vlen_new
210 MDrv_WriteByteMask( REG_FRC_BK13D_CC , 0x70, 0xff); // reg_opm_vlen_new
211 MDrv_WriteByteMask( REG_FRC_BK13D_CD , 0x08, 0x1f); // reg_opm_vlen_new
212 MDrv_WriteByteMask( REG_FRC_BK134_BA , 0x1c, 0xff); // reg_opm_meds_vlen
213 MDrv_WriteByteMask( REG_FRC_BK134_BB , 0x02, 0x1f); // reg_opm_meds_vlen
214 MDrv_WriteByteMask( REG_FRC_BK136_BA , 0x1c, 0xff); // reg_opm_meds_vlen
215 MDrv_WriteByteMask( REG_FRC_BK136_BB , 0x02, 0x1f); // reg_opm_meds_vlen
216 MDrv_WriteByteMask( REG_FRC_BK13A_BA , 0x1c, 0xff); // reg_opm_meds_vlen
217 MDrv_WriteByteMask( REG_FRC_BK13A_BB , 0x02, 0x1f); // reg_opm_meds_vlen
218 MDrv_WriteByteMask( REG_FRC_BK13B_BA , 0x1c, 0xff); // reg_opm_meds_vlen
219 MDrv_WriteByteMask( REG_FRC_BK13B_BB , 0x02, 0x1f); // reg_opm_meds_vlen
220 MDrv_WriteByteMask( REG_FRC_BK13C_BA , 0x1c, 0xff); // reg_opm_meds_vlen
221 MDrv_WriteByteMask( REG_FRC_BK13C_BB , 0x02, 0x1f); // reg_opm_meds_vlen
222 MDrv_WriteByteMask( REG_FRC_BK13D_BA , 0x1c, 0xff); // reg_opm_meds_vlen
223 MDrv_WriteByteMask( REG_FRC_BK13D_BB , 0x02, 0x1f); // reg_opm_meds_vlen
224 MDrv_WriteByteMask( REG_FRC_BK134_C8 , 0x38, 0xff); // reg_opm_meds_vlen_new
225 MDrv_WriteByteMask( REG_FRC_BK134_C9 , 0x04, 0x1f); // reg_opm_meds_vlen_new
226 MDrv_WriteByteMask( REG_FRC_BK136_C8 , 0x38, 0xff); // reg_opm_meds_vlen_new
227 MDrv_WriteByteMask( REG_FRC_BK136_C9 , 0x04, 0x1f); // reg_opm_meds_vlen_new
228 MDrv_WriteByteMask( REG_FRC_BK13A_C8 , 0x38, 0xff); // reg_opm_meds_vlen_new
229 MDrv_WriteByteMask( REG_FRC_BK13A_C9 , 0x04, 0x1f); // reg_opm_meds_vlen_new
230 MDrv_WriteByteMask( REG_FRC_BK13B_C8 , 0x38, 0xff); // reg_opm_meds_vlen_new
231 MDrv_WriteByteMask( REG_FRC_BK13B_C9 , 0x04, 0x1f); // reg_opm_meds_vlen_new
232 MDrv_WriteByteMask( REG_FRC_BK13C_C8 , 0x38, 0xff); // reg_opm_meds_vlen_new
233 MDrv_WriteByteMask( REG_FRC_BK13C_C9 , 0x04, 0x1f); // reg_opm_meds_vlen_new
234 MDrv_WriteByteMask( REG_FRC_BK13D_C8 , 0x38, 0xff); // reg_opm_meds_vlen_new
235 MDrv_WriteByteMask( REG_FRC_BK13D_C9 , 0x04, 0x1f); // reg_opm_meds_vlen_new
236 // IPM_OPM_DSmode
237 MDrv_WriteByteMask( REG_FRC_BK13A_1C , 0xc0, 0xff); // reg_ipm_offset_f2
238 MDrv_WriteByteMask( REG_FRC_BK13A_1D , 0x03, 0xff); // reg_ipm_offset_f2
239 MDrv_WriteByteMask( REG_FRC_BK13A_1E , 0xc0, 0xff); // reg_ipm_fetch_num_f2
240 MDrv_WriteByteMask( REG_FRC_BK13A_1F , 0x03, 0xff); // reg_ipm_fetch_num_f2
241 MDrv_WriteByteMask( REG_FRC_BK13A_9C , 0xc0, 0xff); // reg_ipm_offset_f1
242 MDrv_WriteByteMask( REG_FRC_BK13A_9D , 0x03, 0xff); // reg_ipm_offset_f1
243 MDrv_WriteByteMask( REG_FRC_BK13A_9E , 0xc0, 0xff); // reg_ipm_fetch_num_f1
244 MDrv_WriteByteMask( REG_FRC_BK13A_9F , 0x03, 0xff); // reg_ipm_fetch_num_f1
245 MDrv_WriteByteMask( REG_FRC_BK134_BC , 0xc0, 0xff); // reg_opm_meds_offset
246 MDrv_WriteByteMask( REG_FRC_BK134_BD , 0x03, 0xff); // reg_opm_meds_offset
247 MDrv_WriteByteMask( REG_FRC_BK134_BE , 0xc0, 0xff); // reg_opm_meds_fetch_num
248 MDrv_WriteByteMask( REG_FRC_BK134_BF , 0x03, 0xff); // reg_opm_meds_fetch_num
249 // IPM_3D
250 MDrv_WriteByteMask( REG_FRC_BK135_1C , 0x38, 0xff); // reg_v_toggle_value
251 MDrv_WriteByteMask( REG_FRC_BK135_1D , 0x04, 0x0f); // reg_v_toggle_value
252 MDrv_WriteByteMask( REG_FRC_BK135_04 , 0x20, 0x30); // reg_v_toggle_en
253 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en
254 MDrv_WriteByteMask( REG_FRC_BK13A_27 , 0x80, 0x80); // reg_ipm_meds_ud_en
255 MDrv_WriteByteMask( REG_FRC_BK134_26 , 0x1c, 0xff); // reg_ipm_turn_back_line
256 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x02, 0x1f); // reg_ipm_turn_back_line
257 MDrv_WriteByteMask( REG_FRC_BK13A_26 , 0x0e, 0xff); // reg_ipm_turn_back_line_meds
258 MDrv_WriteByteMask( REG_FRC_BK13A_27 , 0x01, 0x1f); // reg_ipm_turn_back_line_meds
259 // OPM_3D
260 MDrv_WriteByteMask( REG_FRC_BK134_60 , 0x01, 0x01); // reg_ipm_3d_en_f2
261 MDrv_WriteByteMask( REG_FRC_BK134_E0 , 0x01, 0x01); // reg_ipm_3d_en_f1
262 MDrv_WriteByteMask( REG_FRC_BK13A_60 , 0x01, 0x01); // reg_ipm_3d_en_mef3f4_f2
263 MDrv_WriteByteMask( REG_FRC_BK13A_E0 , 0x01, 0x01); // reg_ipm_3d_en_mef3f4_f1
264 MDrv_WriteByteMask( REG_FRC_BK134_66 , 0x80, 0x80); // reg_opm_3d_en_f2
265 MDrv_WriteByteMask( REG_FRC_BK136_66 , 0x80, 0x80); // reg_opm_3d_en_f1
266 MDrv_WriteByteMask( REG_FRC_BK13A_66 , 0x80, 0x80); // reg_opm_3d_en_mef3f4_f2
267 MDrv_WriteByteMask( REG_FRC_BK13B_66 , 0x80, 0x80); // reg_opm_3d_en_mef3f4_f1
268 MDrv_WriteByteMask( REG_FRC_BK13C_66 , 0x80, 0x80); // reg_opm_3d_en_mif3_f2
269 MDrv_WriteByteMask( REG_FRC_BK13D_66 , 0x80, 0x80); // reg_opm_3d_en_mif3_f1
270 MDrv_WriteByteMask( REG_FRC_BK134_67 , 0x00, 0x04); // reg_opm_passive_en_f2
271 MDrv_WriteByteMask( REG_FRC_BK136_67 , 0x00, 0x04); // reg_opm_passive_en_f1
272 MDrv_WriteByteMask( REG_FRC_BK13A_67 , 0x00, 0x04); // reg_opm_passive_en_f2
273 MDrv_WriteByteMask( REG_FRC_BK13B_67 , 0x00, 0x04); // reg_opm_passive_en_f1
274 MDrv_WriteByteMask( REG_FRC_BK13C_67 , 0x00, 0x04); // reg_opm_passive_en_f2
275 MDrv_WriteByteMask( REG_FRC_BK13D_67 , 0x00, 0x04); // reg_opm_passive_en_f1
276 MDrv_WriteByteMask( REG_FRC_BK134_2B , 0x00, 0x20); // reg_opm_line_repeat_en_f2
277 MDrv_WriteByteMask( REG_FRC_BK136_2B , 0x00, 0x20); // reg_opm_line_repeat_en_f1
278 MDrv_WriteByteMask( REG_FRC_BK13A_2B , 0x00, 0x20); // reg_opm_line_repeat_en_f2
279 MDrv_WriteByteMask( REG_FRC_BK13B_2B , 0x00, 0x20); // reg_opm_line_repeat_en_f1
280 MDrv_WriteByteMask( REG_FRC_BK13C_2B , 0x00, 0x20); // reg_opm_line_repeat_en_f2
281 MDrv_WriteByteMask( REG_FRC_BK13D_2B , 0x00, 0x20); // reg_opm_line_repeat_en_f1
282 // OPMRM
283 MDrv_WriteByteMask( REG_FRC_BK134_E8 , 0x00, 0x01); // reg_opm_ml_en
284 MDrv_WriteByteMask( REG_FRC_BK134_E9 , 0x00, 0x08); // reg_rbk_free
285 MDrv_WriteByteMask( REG_FRC_BK134_E9 , 0x00, 0x70); // reg_rbk_free_diff
286 MDrv_WriteByteMask( REG_FRC_BK134_32 , 0x00, 0x80); // reg_opm_2f_md
287 MDrv_WriteByteMask( REG_FRC_BK136_32 , 0x00, 0x80); // reg_opm_2f_md
288 MDrv_WriteByteMask( REG_FRC_BK134_33 , 0x01, 0x01); // reg_opm_3f_md
289 MDrv_WriteByteMask( REG_FRC_BK136_33 , 0x01, 0x01); // reg_opm_3f_md
290 MDrv_WriteByteMask( REG_FRC_BK134_CE , 0x05, 0x0f); // reg_opm_memc_md
291 MDrv_WriteByteMask( REG_FRC_BK134_CF , 0x04, 0x07); // reg_opm_memc_md
292 // HSD_MEDS
293 MDrv_WriteByteMask( REG_FRC_BK320_C2 , 0x33, 0xff); // reg_frc_ipm_hvsd_la_mode
294 MDrv_WriteByteMask( REG_FRC_BK320_C3 , 0x8E, 0xff); // reg_frc_ipm_hvsd_drop_mode
295 // MEMC_FSC
296 MDrv_WriteByteMask( REG_FRC_BK320_A4 , 0x00, 0xff); // reg_frc_xxxx
297 MDrv_WriteByteMask( REG_FRC_BK320_A5 , 0x0F, 0xff); // reg_frc_xxxx
298 MDrv_WriteByteMask( REG_FRC_BK320_A6 , 0x80, 0xff); // reg_frc_xxxx
299 MDrv_WriteByteMask( REG_FRC_BK320_A7 , 0x07, 0xff); // reg_frc_xxxx
300 // MLB
301 MDrv_WriteByteMask( REG_FRC_BK226_F4 , 0x01, 0xff); // reg_sadmvRangeL
302 MDrv_WriteByteMask( REG_FRC_BK226_F5 , 0x00, 0x03); // reg_sadmvRangeL
303 MDrv_WriteByteMask( REG_FRC_BK226_F8 , 0x01, 0xff); // reg_sadmvRangeU
304 MDrv_WriteByteMask( REG_FRC_BK226_F9 , 0x00, 0x01); // reg_sadmvRangeU
305 MDrv_WriteByteMask( REG_FRC_BK226_F6 , 0xff, 0xff); // reg_sadmvRangeR
306 MDrv_WriteByteMask( REG_FRC_BK226_F7 , 0x03, 0x03); // reg_sadmvRangeR
307 MDrv_WriteByteMask( REG_FRC_BK226_F2 , 0xff, 0xff); // reg_sadmvRangeD
308 MDrv_WriteByteMask( REG_FRC_BK226_F3 , 0x00, 0x01); // reg_sadmvRangeD
309 MDrv_WriteByteMask( REG_FRC_BK232_02 , 0x00, 0x02); // reg_pass3d_la
310 MDrv_WriteByteMask( REG_FRC_BK232_11 , 0x00, 0xc0); // reg_mask_en
311 // MV_PREPROC
312 MDrv_WriteByteMask( REG_FRC_BK22C_92 , 0x00, 0x03); // reg_mv_preprocess
313 // MFC_pipectrl
314 MDrv_WriteByteMask( REG_FRC_BK233_3E , 0x00, 0xff); // reg_ppctr_h_pixl_num_me
315 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x0f, 0x1f); // reg_ppctr_h_pixl_num_me
316 MDrv_WriteByteMask( REG_FRC_BK233_40 , 0x1c, 0xff); // reg_ppctr_v_line_num_me
317 MDrv_WriteByteMask( REG_FRC_BK233_41 , 0x02, 0x1f); // reg_ppctr_v_line_num_me
318 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x00, 0xff); // reg_me_h_pixel_num_mi
319 MDrv_WriteByteMask( REG_FRC_BK233_47 , 0x0f, 0x1f); // reg_me_h_pixel_num_mi
320 MDrv_WriteByteMask( REG_FRC_BK233_48 , 0x38, 0xff); // reg_me_v_pixel_num_mi
321 MDrv_WriteByteMask( REG_FRC_BK233_49 , 0x04, 0x1f); // reg_me_v_pixel_num_mi
322 MDrv_WriteByteMask( REG_FRC_BK233_F8 , 0x00, 0xff); // reg_h_pixel_num_mlb
323 MDrv_WriteByteMask( REG_FRC_BK233_F9 , 0x0f, 0x1f); // reg_h_pixel_num_mlb
324 MDrv_WriteByteMask( REG_FRC_BK233_FA , 0x38, 0xff); // reg_v_pixel_num_mlb
325 MDrv_WriteByteMask( REG_FRC_BK233_FB , 0x04, 0x1f); // reg_v_pixel_num_mlb
326 MDrv_WriteByteMask( REG_FRC_BK233_3A , 0x00, 0xff); // reg_time_gen_sw_h_width
327 MDrv_WriteByteMask( REG_FRC_BK233_3B , 0x0f, 0x1f); // reg_time_gen_sw_h_width
328 MDrv_WriteByteMask( REG_FRC_BK233_3C , 0x0d, 0xff); // reg_time_gen_sw_v_width
329 MDrv_WriteByteMask( REG_FRC_BK233_3D , 0x01, 0x1f); // reg_time_gen_sw_v_width
330 MDrv_WriteByteMask( REG_FRC_BK233_42 , 0x80, 0xff); // reg_mlb_disp_pixel_latch
331 MDrv_WriteByteMask( REG_FRC_BK233_43 , 0x07, 0x1f); // reg_mlb_disp_pixel_latch
332 MDrv_WriteByteMask( REG_FRC_BK233_A8 , 0x80, 0xff); // reg_gmv_vertical_active_window_height
333 MDrv_WriteByteMask( REG_FRC_BK233_A9 , 0x00, 0x01); // reg_gmv_vertical_active_window_height
334 // MFC_VDUP
335 MDrv_WriteByteMask( REG_FRC_BK20A_04 , 0xC0, 0xFF); // reg_VDUP_width
336 MDrv_WriteByteMask( REG_FRC_BK20A_05 , 0x03, 0xFF); // reg_VDUP_width
337 MDrv_WriteByteMask( REG_FRC_BK20A_06 , 0x70, 0xFF); // reg_VDUP_height
338 MDrv_WriteByteMask( REG_FRC_BK20A_07 , 0x08, 0xFF); // reg_VDUP_height
339 // MFC
340 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x73, 0xff); // reg_MFC_enable
341 MDrv_WriteByteMask( REG_FRC_BK226_70 , 0x20, 0x20); //
342 MDrv_WriteByteMask( REG_FRC_BK226_73 , 0x0f, 0x1f); // reg_h_pix_num_3D
343 MDrv_WriteByteMask( REG_FRC_BK226_72 , 0x00, 0xff); // reg_h_pix_num_3D
344 MDrv_WriteByteMask( REG_FRC_BK226_75 , 0x02, 0x1f); // reg_v_lin_num_3D
345 MDrv_WriteByteMask( REG_FRC_BK226_74 , 0x1c, 0xff); // reg_v_lin_num_3D
346 MDrv_WriteByteMask( REG_FRC_BK22C_80 , 0x08, 0x08); //
347 MDrv_WriteByteMask( REG_FRC_BK229_05 , 0x0f, 0xFF); // reg_h_pix_num_ME
348 MDrv_WriteByteMask( REG_FRC_BK229_04 , 0x00, 0xFF); // reg_h_pix_num_ME
349 MDrv_WriteByteMask( REG_FRC_BK229_07 , 0x04, 0x0F); // reg_v_lin_num_ME
350 MDrv_WriteByteMask( REG_FRC_BK229_06 , 0x40, 0xFF); // reg_v_lin_num_ME
351 MDrv_WriteByteMask( REG_FRC_BK229_91 , 0x0f, 0xFF); // reg_h_pix_num_MI
352 MDrv_WriteByteMask( REG_FRC_BK229_90 , 0x00, 0xFF); // reg_h_pix_num_MI
353 MDrv_WriteByteMask( REG_FRC_BK229_93 , 0x04, 0xFF); // reg_v_lin_num_MI
354 MDrv_WriteByteMask( REG_FRC_BK229_92 , 0x38, 0xFF); // reg_v_lin_num_MI
355 MDrv_WriteByteMask( REG_FRC_BK226_67 , 0x01, 0x01); // reg_422to444_en
356 MDrv_WriteByteMask( REG_FRC_BK232_D0 , 0x00, 0x02); // reg_rgb_bypass
357 MDrv_WriteByteMask( REG_FRC_BK226_60 , 0x80, 0x80); // reg_c_drop
358 MDrv_WriteByteMask( REG_FRC_BK229_9C , 0x80, 0x80); // reg_422_avgmode
359 MDrv_WriteByteMask( REG_FRC_BK22C_80 , 0x01, 0x01); // reg_pipectrl_bypass
360 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x10); // reg_mlb_mi_half_sr
361 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x20); // reg_mlb_me_half_sr
362 // MFC_Halo
363 MDrv_WriteByteMask( REG_FRC_BK22C_93 , 0x00, 0x80); // reg_halo_buf_frame_end_en
364 MDrv_WriteByteMask( REG_FRC_BK22C_A7 , 0x02, 0x02); // reg_halo_buf23_force_ready
365 // MFC_GMV
366 MDrv_WriteByteMask( REG_FRC_BK232_2A , 0x01, 0x01); // reg_gmv_in_ud_mode
367 // SNR
368 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en
369 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x04, 0x04); // reg_snr_la_en
370 MDrv_WriteByteMask( REG_FRC_BK2E_E2 , 0x00, 0xff); // reg_snr_pix_num_LSB
371 MDrv_WriteByteMask( REG_FRC_BK2E_E3 , 0x0f, 0x1f); // reg_snr_pix_num_MSB
372 MDrv_WriteByteMask( REG_FRC_BK2E_E8 , 0x38, 0xff); // reg_snr_line_num_LSB
373 MDrv_WriteByteMask( REG_FRC_BK2E_E9 , 0x04, 0x0f); // reg_snr_line_num_MSB
374 // SNR_3D
375 MDrv_WriteByteMask( REG_FRC_BK2E_65 , 0x00, 0x20); // reg_line_switch
376 // SNR_VSU2X
377 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x10, 0x10); // reg_lbi_vsu2x_en
378 // T3D
379 MDrv_WriteByteMask( REG_SC_BKC6_C0, 0x31, 0xff); // reg_pipe_guard_cycle_pb
380 MDrv_WriteByteMask( REG_SC_BKC6_C2, 0x00, 0xff); // reg_ln_width
381 MDrv_WriteByteMask( REG_SC_BKC6_C3, 0x0f, 0x3f); // reg_ln_width
382 MDrv_WriteByteMask( REG_SC_BKC6_C4, 0x70, 0xff); // reg_col_height
383 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x08, 0x1f); // reg_col_height
384 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x60); // reg_lb_mode_control
385 MDrv_WriteByteMask( REG_SC_BKC6_C6, 0x01, 0x01); // reg_srclb_en
386 MDrv_WriteByteMask( REG_SC_BKC6_C6, 0x02, 0x02); // reg_depthlb_en
387 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x01); // reg_render_control
388 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x02); // reg_lr_control_l
389 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x04, 0x04); // reg_lr_control_r
390 MDrv_WriteByteMask( REG_SC_BKC6_10, 0x10, 0x10); // reg_mtv_bypass_en
391 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x40); // reg_lineswap
392 MDrv_WriteByteMask( REG_SC_BKC7_02, 0x00, 0xff); // reg_hsu_size_1
393 MDrv_WriteByteMask( REG_SC_BKC7_03, 0x0f, 0x0f); // reg_hsu_size_1
394 MDrv_WriteByteMask( REG_SC_BKC7_12, 0x00, 0xff); // reg_hsu_size_2
395 MDrv_WriteByteMask( REG_SC_BKC7_13, 0x0f, 0x0f); // reg_hsu_size_2
396 // FO_HSU
397 MDrv_WriteByteMask( REG_FRC_BK115_30 , 0x00, 0xff); // hfac_smd0
398 MDrv_WriteByteMask( REG_FRC_BK115_31 , 0x00, 0xff); // hfac_smd1
399 MDrv_WriteByteMask( REG_FRC_BK115_32 , 0x00, 0x3f); // hfac_smd2
400 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en
401 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en
402 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0
403 MDrv_WriteByteMask( REG_FRC_BK115_0D , 0x0f, 0x1f); // hsp_size_in1
404 MDrv_WriteByteMask( REG_FRC_BK115_0E , 0x00, 0xff); // hsp_size_out0
405 MDrv_WriteByteMask( REG_FRC_BK115_0F , 0x0f, 0x1f); // hsp_size_out1
406 // SPTP
407 MDrv_WriteByteMask( REG_FRC_BK3E_80 , 0xff, 0xff); // reg_sptp_mfc_dc_m1
408 MDrv_WriteByteMask( REG_FRC_BK3E_81 , 0x0e, 0x0f); // reg_sptp_mfc_dc_m1
409 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en
410 MDrv_WriteByteMask( REG_FRC_BK3E_84 , 0x01, 0x01); // reg_sptp_usr_en
411 MDrv_WriteByteMask( REG_FRC_BK3E_88 , 0x00, 0xff); // reg_sptp_f0_st
412 MDrv_WriteByteMask( REG_FRC_BK3E_89 , 0x00, 0x01); // reg_sptp_f0_st
413 MDrv_WriteByteMask( REG_FRC_BK3E_8A , 0xf1, 0xff); // reg_sptp_f0_end
414 MDrv_WriteByteMask( REG_FRC_BK3E_8B , 0x00, 0x01); // reg_sptp_f0_end
415 MDrv_WriteByteMask( REG_FRC_BK3E_8C , 0xee, 0xff); // reg_sptp_f1_st
416 MDrv_WriteByteMask( REG_FRC_BK3E_8D , 0x00, 0x01); // reg_sptp_f1_st
417 MDrv_WriteByteMask( REG_FRC_BK3E_8E , 0xdf, 0xff); // reg_sptp_f1_end
418 MDrv_WriteByteMask( REG_FRC_BK3E_8F , 0x01, 0x01); // reg_sptp_f1_end
419 MDrv_WriteByteMask( REG_FRC_BK3E_86 , 0x02, 0xff); // reg_sptp_gb_en
420 // CSC
421 }
422
423
424
425 /********************************************/
426