1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. 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93 94 typedef struct 95 { 96 MS_U8 address; 97 MS_U16 value; 98 MS_U16 mask; 99 }TBLStruct_Ext,*pTBLStruct_Ext; 100 101 TBLStruct_Ext LPLLSettingTBL_Ext[E_PNL_SUPPORTED_LPLL_EXT_MAX][LPLL_EXT_REG_NUM]= 102 { 103 { //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_115to150MHz NO.0 104 //Address,Value,Mask 105 {0x40,0x0000,0x8000},//reg_lpll_ext_pd 106 {0x40,0x0001,0x0007},//reg_lpll_ext_ictrl 107 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 108 {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst 109 {0x41,0x0300,0x0F00},//reg_lpll_ext_loop_div_sec 110 {0x42,0x0000,0x0003},//reg_lpll_ext_scalar_div_fst 111 {0x42,0x0070,0x00F0},//reg_lpll_ext_scalar_div_sec 112 {0x43,0x0000,0x0007},//reg_lpll_ext_skew_div 113 {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div 114 {0x43,0x0010,0x0010},//reg_lpll_ext_skew_en_fixclk 115 {0x40,0x0000,0x0800},//reg_lpll_ext_dual_lp_en 116 {0x40,0x0000,0x0100},//reg_lpll_ext_sdiv2p5_en 117 {0x40,0x2000,0x2000},//reg_lpll_ext_en_mini 118 {0x40,0x0000,0x0400},//reg_lpll_ext_en_fifo 119 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 120 {0x40,0x0000,0x1000},//reg_lpll_ext_fifo_div5_en 121 {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en 122 }, 123 124 { //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_57to115MHz NO.1 125 //Address,Value,Mask 126 {0x40,0x0000,0x8000},//reg_lpll_ext_pd 127 {0x40,0x0001,0x0007},//reg_lpll_ext_ictrl 128 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 129 {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst 130 {0x41,0x0300,0x0F00},//reg_lpll_ext_loop_div_sec 131 {0x42,0x0001,0x0003},//reg_lpll_ext_scalar_div_fst 132 {0x42,0x0070,0x00F0},//reg_lpll_ext_scalar_div_sec 133 {0x43,0x0001,0x0007},//reg_lpll_ext_skew_div 134 {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div 135 {0x43,0x0010,0x0010},//reg_lpll_ext_skew_en_fixclk 136 {0x40,0x0000,0x0800},//reg_lpll_ext_dual_lp_en 137 {0x40,0x0000,0x0100},//reg_lpll_ext_sdiv2p5_en 138 {0x40,0x2000,0x2000},//reg_lpll_ext_en_mini 139 {0x40,0x0000,0x0400},//reg_lpll_ext_en_fifo 140 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 141 {0x40,0x0000,0x1000},//reg_lpll_ext_fifo_div5_en 142 {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en 143 }, 144 145 { //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_25to57MHz NO.2 146 //Address,Value,Mask 147 {0x40,0x0000,0x8000},//reg_lpll_ext_pd 148 {0x40,0x0001,0x0007},//reg_lpll_ext_ictrl 149 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 150 {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst 151 {0x41,0x0300,0x0F00},//reg_lpll_ext_loop_div_sec 152 {0x42,0x0002,0x0003},//reg_lpll_ext_scalar_div_fst 153 {0x42,0x0070,0x00F0},//reg_lpll_ext_scalar_div_sec 154 {0x43,0x0002,0x0007},//reg_lpll_ext_skew_div 155 {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div 156 {0x43,0x0010,0x0010},//reg_lpll_ext_skew_en_fixclk 157 {0x40,0x0000,0x0800},//reg_lpll_ext_dual_lp_en 158 {0x40,0x0000,0x0100},//reg_lpll_ext_sdiv2p5_en 159 {0x40,0x2000,0x2000},//reg_lpll_ext_en_mini 160 {0x40,0x0000,0x0400},//reg_lpll_ext_en_fifo 161 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 162 {0x40,0x0000,0x1000},//reg_lpll_ext_fifo_div5_en 163 {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en 164 }, 165 166 { //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_25to25MHz NO.3 167 //Address,Value,Mask 168 {0x40,0x0000,0x8000},//reg_lpll_ext_pd 169 {0x40,0x0001,0x0007},//reg_lpll_ext_ictrl 170 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 171 {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst 172 {0x41,0x0300,0x0F00},//reg_lpll_ext_loop_div_sec 173 {0x42,0x0002,0x0003},//reg_lpll_ext_scalar_div_fst 174 {0x42,0x0070,0x00F0},//reg_lpll_ext_scalar_div_sec 175 {0x43,0x0002,0x0007},//reg_lpll_ext_skew_div 176 {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div 177 {0x43,0x0010,0x0010},//reg_lpll_ext_skew_en_fixclk 178 {0x40,0x0000,0x0800},//reg_lpll_ext_dual_lp_en 179 {0x40,0x0000,0x0100},//reg_lpll_ext_sdiv2p5_en 180 {0x40,0x2000,0x2000},//reg_lpll_ext_en_mini 181 {0x40,0x0000,0x0400},//reg_lpll_ext_en_fifo 182 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 183 {0x40,0x0000,0x1000},//reg_lpll_ext_fifo_div5_en 184 {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en 185 }, 186 187 }; 188 MS_U16 u16EXT_LoopGain[E_PNL_SUPPORTED_LPLL_EXT_MAX]= 189 { 190 12, //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_115to150MHz NO.0 191 6, //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_57to115MHz NO.1 192 3, //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_25to57MHz NO.2 193 3, //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_25to25MHz NO.3 194 }; 195 MS_U16 u16EXT_LoopDiv[E_PNL_SUPPORTED_LPLL_EXT_MAX]= 196 { 197 7, //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_115to150MHz NO.0 198 7, //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_57to115MHz NO.1 199 7, //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_25to57MHz NO.2 200 7, //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_25to25MHz NO.3 201 }; 202 203 #endif //_LPLL_TBL_H_ 204