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MStar hereby reserves the 88 // rights to any and all damages, losses, costs and expenses resulting therefrom. 89 // 90 //////////////////////////////////////////////////////////////////////////////// 91 //============================================================================== 92 // [mhal_mux.h] 93 // Date: 20090220 94 // Descriptions: Add a new mux layer for HW setting 95 //============================================================================== 96 #ifndef MHAL_MUX_H 97 #define MHAL_MUX_H 98 99 /////////////////////////////// 100 // Mux Hardware Option 101 /////////////////////////////// 102 // Please set this #define after Mux tree is ready 103 #define MUX_TREE_HEIGHT 4 104 105 #define NUMBER_OF_ANALOG_PORT 3 106 #define NUMBER_OF_CVBS_PORT 8 107 #define NUMBER_OF_DVI_PORT 3 108 #define NUMBER_OF_MVOP_PORT 2 109 #define NUMBER_OF_CVBS_OUT_PORT 2 110 #define NUMBER_OF_YPBPR_OUT_PORT 0 111 #define PIP_SUPPORTED (MAX_WINDOW_NUM > 1) 112 #define NUMBER_OF_SCALER_OP_PORT 1 113 114 /* 115 Input ports. 116 It is interface between Hal and Driver level. 117 */ 118 119 typedef enum 120 { 121 HAL_INPUTPORT_NONE = INPUT_PORT_NONE_PORT, 122 123 HAL_INPUTPORT_ANALOG0 = INPUT_PORT_ANALOG0, 124 HAL_INPUTPORT_ANALOG1, 125 HAL_INPUTPORT_ANALOG2, 126 127 HAL_INPUTPORT_YMUX_CVBS0 = INPUT_PORT_YMUX_CVBS0, 128 HAL_INPUTPORT_YMUX_CVBS1, 129 HAL_INPUTPORT_YMUX_CVBS2, 130 HAL_INPUTPORT_YMUX_CVBS3, 131 HAL_INPUTPORT_YMUX_CVBS4, 132 HAL_INPUTPORT_YMUX_CVBS5, 133 HAL_INPUTPORT_YMUX_CVBS6, 134 HAL_INPUTPORT_YMUX_CVBS7, 135 136 HAL_INPUTPORT_CMUX_CVBS0 = INPUT_PORT_CMUX_CVBS0, 137 HAL_INPUTPORT_CMUX_CVBS1, 138 HAL_INPUTPORT_CMUX_CVBS2, 139 HAL_INPUTPORT_CMUX_CVBS3, 140 HAL_INPUTPORT_CMUX_CVBS4, 141 HAL_INPUTPORT_CMUX_CVBS5, 142 HAL_INPUTPORT_CMUX_CVBS6, 143 HAL_INPUTPORT_CMUX_CVBS7, 144 145 HAL_INPUTPORT_DVI0 = INPUT_PORT_DVI0, 146 HAL_INPUTPORT_DVI1, 147 HAL_INPUTPORT_DVI2, 148 149 HAL_INPUTPORT_MVOP = INPUT_PORT_MVOP, 150 HAL_INPUTPORT_MVOP2, 151 152 HAL_INPUTPORT_SCALER_OP = INPUT_PORT_SCALER_OP, 153 } E_INPUT_PORT_TYPE; 154 155 // Output ports. 156 157 typedef enum 158 { 159 HAL_OUTPUTPORT_NONE_PORT = OUTPUT_PORT_NONE_PORT, 160 161 HAL_OUTPUTPORT_SCALER_MAIN_WINDOW = OUTPUT_PORT_SCALER_MAIN_WINDOW, 162 163 HAL_OUTPUTPORT_SCALER_SUB_WINDOW1 = OUTPUT_PORT_SCALER_SUB_WINDOW1, 164 165 HAL_OUTPUTPORT_CVBS1 = OUTPUT_PORT_CVBS1, 166 HAL_OUTPUTPORT_CVBS2 , 167 168 HAL_OUTPUTPORT_DIP_WINDOW = OUTPUT_PORT_DWIN, 169 170 }E_OUTPUT_PORT_TYPE; 171 172 typedef enum 173 { 174 SC_MAINWIN_IPMUX_HDMI_DVI = 1, ///< DVI 175 SC_MAINWIN_IPMUX_OP1 = 2, ///< SC0 OP12SC1 176 SC_MAINWIN_IPMUX_MVOP = 3, ///< MPEG/DC0 177 SC_MAINWIN_IPMUX_IP_MAIN = 4, ///< IP MAIN 178 SC_MAINWIN_IPMUX_HDR = 6, ///< HDR output 179 SC_MAINWIN_IPMUX_MVOP2 = 8, ///< MPEG/DC1 180 SC_MAINWIN_IPMUX_SC1_CAPTURE = 10, ///< SC1 Capture 181 SC_MAINWIN_IPMUX_H2V2 = 11, ///< H2V2 output 182 } SC_MAINWIN_IPMUX_TYPE; 183 184 typedef enum 185 { 186 SC_SUBWIN_IPMUX_HDMI_DVI = 1, ///< DVI 187 SC_SUBWIN_IPMUX_OP1 = 2, ///< SC0 OP12SC1 188 SC_SUBWIN_IPMUX_MVOP = 3, ///< MPEG/DC0 189 SC_SUBWIN_IPMUX_IP_MAIN = 4, ///< IP MAIN 190 SC_SUBWIN_IPMUX_HDR = 6, ///< HDR output 191 SC_SUBWIN_IPMUX_MVOP2 = 8, ///< MPEG/DC1 192 SC_SUBWIN_IPMUX_SC1_CAPTURE = 10, ///< SC1 Capture 193 SC_SUBWIN_IPMUX_H2V2 = 11, ///< H2V2 output 194 SC_SUBWIN_IPMUX_ADC_B = 15, ///< ADC B, not using in Kano, only for fixing build error 195 } SC_SUBWIN_IPMUX_TYPE; 196 197 typedef enum 198 { 199 SC_HDR_IPMUX_HDMI_DVI = 1, ///< DVI 200 SC_HDR_IPMUX_OP1 = 2, ///< SC0 OP12SC1 201 SC_HDR_IPMUX_MVOP = 3, ///< MPEG/DC0 202 SC_HDR_IPMUX_IP_MAIN = 4, ///< IP MAIN 203 SC_HDR_IPMUX_HDR = 6, ///< HDR output 204 SC_HDR_IPMUX_MVOP2 = 8, ///< MPEG/DC1 205 SC_HDR_IPMUX_SC1_CAPTURE = 10, ///< SC1 Capture 206 SC_HDR_IPMUX_H2V2 = 11, ///< H2V2 output 207 SC_HDR_IPMUX_ADC_B = 15, ///< ADC B, not using in Kano, only for fixing build error 208 } SC_HDR_IPMUX_TYPE; 209 210 typedef enum 211 { 212 SC_OFFLINE_IPMUX_ADC_A = 0, ///< ADC A 213 SC_OFFLINE_IPMUX_HDMI_DVI = 1, ///< DVI 214 SC_OFFLINE_IPMUX_VD = 2, ///< VD 215 SC_OFFLINE_IPMUX_MVOP = 3, ///< MPEG/DC0 216 SC_OFFLINE_IPMUX_IP_MAIN = 4, ///< IP MAIN 217 SC_OFFLINE_IPMUX_EXT_VD = 5, ///< External VD 218 SC_OFFLINE_IPMUX_ADC_B = 6, ///< ADC B 219 SC_OFFLINE_IPMUX_CAPTURE = 7, ///< Capture 220 SC_OFFLINE_IPMUX_MVOP2 = 8, ///< MPEG/DC1 221 SC_OFFLINE_IPMUX_IP_SUB = 9, ///< IP SUB 222 SC_OFFLINE_IPMUX_SC1_CAPTURE = 10, ///< SC1 Capture 223 SC_OFFLINE_IPMUX_SC_VOP = 11, ///< Scaler VOP output 224 SC_OFFLINE_IPMUX_SC1_VOP = 12, ///< SC1 VOP output 225 } SC_OFFLINE_IPMUX_TYPE; 226 227 typedef enum 228 { 229 SC_DWIN_IPMUX_HDMI_DVI = 1, ///< DVI 230 SC_DWIN_IPMUX_OP1 = 7, ///< SC0 OP12SC1 231 SC_DWIN_IPMUX_MVOP = 3, ///< MPEG/DC0 232 SC_DWIN_IPMUX_IP_MAIN = 4, ///< IP MAIN 233 SC_DWIN_IPMUX_HDR = 6, ///< HDR output 234 SC_DWIN_IPMUX_MVOP2 = 8, ///< MPEG/DC1 235 SC_DWIN_IPMUX_SC1_CAPTURE = 10, ///< SC1 Capture 236 SC_DWIN_IPMUX_H2V2 = 11, ///< H2V2 output 237 SC_DWIN_IPMUX_IP_SUB = 9, ///< IP SUB/VE 238 } SC_DWIN_IPMUX_TYPE; 239 240 typedef enum 241 { 242 SC_CLK_ADC_A = 0, ///< ADC A 243 SC_CLK_HDMI_DVI = 1, ///< DVI 244 SC_CLK_VD = 2, ///< VD 245 SC_CLK_DC0 = 3, ///< MPEG/DC0 246 SC_CLK_ADC_B = 4, ///< ADC_B 247 248 SC_CLK_ODCLK = 7, ///< ODLCK 249 SC_CLK_DC1 = 8, ///< MPEG/DC1 250 SC_CLK_ADC_C = 9, ///< ADC 251 SC_CLK_ODCLK_B = 10, ///<ODCLK 252 SC_CLK_MHL = 11, ///<MHL 253 } SC_IDCLK_TYPE; 254 255 typedef enum 256 { 257 SC1_MAINWIN_IPMUX_HDMI_DVI = 1, ///< DVI 258 SC1_MAINWIN_IPMUX_OP1 = 2, ///< SC0 OP12SC1 259 SC1_MAINWIN_IPMUX_MVOP = 3, ///< MPEG/DC0 260 SC1_MAINWIN_IPMUX_IP_MAIN = 4, ///< IP MAIN 261 SC1_MAINWIN_IPMUX_HDR = 6, ///< HDR output 262 SC1_MAINWIN_IPMUX_MVOP2 = 8, ///< MPEG/DC1 263 SC1_MAINWIN_IPMUX_SC1_CAPTURE = 10, ///< SC1 Capture 264 SC1_MAINWIN_IPMUX_H2V2 = 11, ///< H2V2 output 265 } SC1_MAINWIN_IPMUX_TYPE; 266 267 typedef enum 268 { 269 SC1_CLK_PRE_H2V2 = 0, ///< Pre H2V2 270 SC1_CLK_HDMI_DVI = 1, ///< DVI 271 SC1_CLK_ODCLK = 2, ///< ODCLK 272 SC1_CLK_DC0 = 3, ///< MPEG/DC0 273 SC1_CLK_DC1 = 8, ///< MPEG/DC1 274 } SC1_IDCLK_TYPE; 275 276 typedef enum 277 { 278 SC2_MAINWIN_IPMUX_ADC_A = 0, ///< ADC A 279 SC2_MAINWIN_IPMUX_HDMI_DVI = 1, ///< DVI 280 SC2_MAINWIN_IPMUX_VD = 2, ///< VD 281 SC2_MAINWIN_IPMUX_MVOP = 3, ///< MPEG/DC0 282 283 SC2_MAINWIN_IPMUX_CAPTURE = 7, ///< Capture 284 SC2_MAINWIN_IPMUX_MVOP2 = 8, ///< MPEG/DC1 285 286 SC2_MAINWIN_IPMUX_SPT4K_CH0 = 11, ///< 4K spliter ch0 287 288 SC2_MAINWIN_IPMUX_MHL = 13, ///< MHL 289 SC2_MAINWIN_IPMUX_SPT4K_CH1 = 14, ///< 4K spliter ch1 290 } SC2_MAINWIN_IPMUX_TYPE; 291 292 typedef enum 293 { 294 SC2_CLK_ADC_A = 0, ///< ADC A 295 SC2_CLK_HDMI_DVI = 1, ///< DVI 296 SC2_CLK_VD = 2, ///< VD 297 SC2_CLK_DC0 = 3, ///< MPEG/DC0 298 SC2_CLK_ADC_B = 4, ///< ADC_B 299 300 SC2_CLK_ODCLK = 7, ///< ODLCK 301 SC2_CLK_DC1 = 8, ///< MPEG/DC1 302 SC2_CLK_ADC_C = 9, ///< ADC 303 SC2_CLK_ODCLK_B = 10, ///<ODCLK 304 SC2_CLK_MHL = 13, ///<MHL 305 } SC2_IDCLK_TYPE; 306 307 void Hal_SC_mux_dispatch(void *pInstance, E_MUX_INPUTPORT src , E_MUX_OUTPUTPORT dest); 308 void Hal_SC_mux_set_dvi_mux(void *pInstance, MS_U8 PortId, E_OUTPUT_PORT_TYPE enDstPort); 309 void Hal_SC_mux_set_adc_y_mux(void *pInstance, MS_U8 PortId); 310 void Hal_SC_mux_set_adc_c_mux(void *pInstance, MS_U8 PortId); 311 #define Hal_SC_set_sync_port_by_dataport(args...) 312 MS_BOOL Hal_SC_mux_get_mainwin_ip_mux( void *pInstance, MS_U8 *pU8Data_Mux, MS_U8 *pU8Clk_Mux); 313 void Hal_SC_set_subwin_ip_mux( void *pInstance, MS_U8 u8Data_Mux, MS_U8 u8Clk_Mux); 314 void Hal_SC_mux_set_mainwin_ip_mux( void *pInstance, MS_U8 u8Data_Mux, MS_U8 u8Clk_Mux); 315 316 void Hal_SC_mux_set_dipwin_ip_mux(void *pInstance, MS_U8 u8Data_Mux, MS_U8 u8Clk_Mux); 317 void Hal_SC_EnableCLK_for_DIP(void *pInstance, MS_BOOL bEnable); 318 319 320 321 #endif // MHAL_MUX_H 322