1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. 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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _HAL_VPU_EX_H_ 96 #define _HAL_VPU_EX_H_ 97 98 //------------------------------------------------------------------------------------------------- 99 // Macro and Define 100 //------------------------------------------------------------------------------------------------- 101 #if (!defined(MSOS_TYPE_NUTTX) && !defined(MSOS_TYPE_OPTEE)) || defined(SUPPORT_X_MODEL_FEATURE) 102 103 #if defined(REDLION_LINUX_KERNEL_ENVI) 104 #define ENABLE_VPU_MUTEX_PROTECTION 0 105 #define VPU_DEFAULT_MUTEX_TIMEOUT 0xFFFFFFFFUL 106 #define VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM 0 107 #else 108 #define ENABLE_VPU_MUTEX_PROTECTION 1 109 #define VPU_DEFAULT_MUTEX_TIMEOUT MSOS_WAIT_FOREVER 110 111 #if defined(FW_EXTERNAL_BIN) 112 #define VPU_ENABLE_EMBEDDED_FW_BINARY 0 113 #define VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM 1 114 #else 115 #define VPU_ENABLE_EMBEDDED_FW_BINARY 1 116 #define VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM 0 117 #endif 118 119 #endif 120 121 #define VPU_FORCE_MIU_MODE 1 122 #define HVD_ENABLE_IQMEM 0 123 #define VPU_IQMEM_BASE 0xe0000000 124 125 126 #define ENABLE_DECOMPRESS_FUNCTION TRUE 127 128 #define VPU_CLOCK_240MHZ BITS(4:2,0) 129 #define VPU_CLOCK_216MHZ BITS(4:2,1) 130 #define VPU_CLOCK_192MHZ BITS(4:2,2) 131 #define VPU_CLOCK_12MHZ BITS(4:2,3) 132 #define VPU_CLOCK_320MHZ BITS(4:2,4) 133 #define VPU_CLOCK_288MHZ BITS(4:2,5) 134 #define VPU_CLOCK_432MHZ BITS(4:2,6) 135 #define VPU_CLOCK_384MHZ BITS(4:2,7) 136 137 138 #define VPU_HI_MBOX0 0 139 #define VPU_HI_MBOX1 1 140 #define VPU_RISC_MBOX0 2 141 #define VPU_RISC_MBOX1 3 142 143 144 #define VPU_EX_TimerDelayMS(x) \ 145 do \ 146 { \ 147 volatile MS_U32 ticks = 0; \ 148 while (ticks < (((MS_U32) (x)) << 13)) \ 149 { \ 150 ticks++; \ 151 } \ 152 } while(0) 153 154 #ifdef VDEC3 155 #define VPU_BBU_NAL_TBL BIT(0) 156 #define VPU_BBU_ES_BUFFER BIT(1) 157 #define HAL_VPU_INVALID_BBU_ID 0xFFFFFFFF 158 #define VPU_MAX_DEC_NUM 16 159 #else 160 #define VPU_MAX_DEC_NUM 2 161 #endif 162 #define CHECK_NULL_PTR(vbbu_addr) (((void *)(vbbu_addr)) == NULL) 163 164 //------------------------------------------------------------------------------------------------- 165 // Type and Structure 166 //------------------------------------------------------------------------------------------------- 167 typedef enum 168 { 169 E_HAL_HVD_STREAM_NONE = 0x0, 170 171 //Support TSP/TS/File mode 172 E_HAL_HVD_MAIN_STREAM_BASE = 0x10, 173 E_HAL_HVD_MAIN_STREAM0 = E_HAL_HVD_MAIN_STREAM_BASE, 174 E_HAL_HVD_MAIN_STREAM_MAX, 175 176 //Only support file mode 177 E_HAL_HVD_SUB_STREAM_BASE = 0x20, 178 E_HAL_HVD_SUB_STREAM0 = E_HAL_HVD_SUB_STREAM_BASE, 179 E_HAL_HVD_SUB_STREAM1, 180 E_HAL_HVD_SUB_STREAM_MAX, 181 182 #ifdef VDEC3 183 E_HAL_HVD_N_STREAM_BASE = 0x40, 184 E_HAL_HVD_N_STREAM0 = E_HAL_HVD_N_STREAM_BASE, 185 E_HAL_HVD_N_STREAM_MAX = E_HAL_HVD_N_STREAM0 + VPU_MAX_DEC_NUM, 186 #endif 187 188 //Only support MVC stream 189 E_HAL_HVD_MVC_STREAM_BASE = 0xF0, 190 E_HAL_HVD_MVC_Main_View = E_HAL_HVD_MVC_STREAM_BASE, 191 E_HAL_HVD_MVC_Sub_View, 192 E_HAL_HVD_MVC_STREAM_MAX, 193 } HAL_HVD_StreamId; 194 195 typedef enum 196 { 197 E_VPU_EX_DECODER_NONE = 0, 198 E_VPU_EX_DECODER_GET, 199 E_VPU_EX_DECODER_GET_MVC, 200 E_VPU_EX_DECODER_MVD, 201 E_VPU_EX_DECODER_HVD, 202 E_VPU_EX_DECODER_MJPEG, 203 E_VPU_EX_DECODER_RVD, 204 E_VPU_EX_DECODER_MVC, 205 E_VPU_EX_DECODER_VP8, 206 #ifdef VDEC3 207 E_VPU_EX_DECODER_EVD, 208 #if SUPPORT_G2VP9 209 E_VPU_EX_DECODER_G2VP9, 210 #endif 211 #endif 212 } VPU_EX_DecoderType; 213 214 #ifdef CONFIG_MSTAR_CLKM 215 typedef enum 216 { 217 E_VPU_EX_CLKPORT_MVD = 0, 218 E_VPU_EX_CLKPORT_MVD_CORE, 219 E_VPU_EX_CLKPORT_MVD_PAS, 220 E_VPU_EX_CLKPORT_HVD, 221 E_VPU_EX_CLKPORT_HVD_IDB, 222 E_VPU_EX_CLKPORT_HVD_AEC, 223 E_VPU_EX_CLKPORT_HVD_AEC_LITE, 224 E_VPU_EX_CLKPORT_VP8, 225 E_VPU_EX_CLKPORT_EVD, 226 E_VPU_EX_CLKPORT_EVD_PPU, 227 E_VPU_EX_CLKPORT_EVD_LITE, 228 E_VPU_EX_CLKPORT_EVD_PPU_LITE, 229 E_VPU_EX_CLKPORT_VD_MHEG5, 230 E_VPU_EX_CLKPORT_VD_MHEG5_LITE, 231 } VPU_EX_ClkPortType; 232 #endif 233 234 typedef enum 235 { 236 E_VPU_EX_CLOCK_240MHZ = VPU_CLOCK_240MHZ, 237 E_VPU_EX_CLOCK_216MHZ = VPU_CLOCK_216MHZ, 238 E_VPU_EX_CLOCK_192MHZ = VPU_CLOCK_192MHZ, 239 E_VPU_EX_CLOCK_12MHZ = VPU_CLOCK_12MHZ, 240 E_VPU_EX_CLOCK_320MHZ = VPU_CLOCK_320MHZ, 241 E_VPU_EX_CLOCK_288MHZ = VPU_CLOCK_288MHZ, 242 E_VPU_EX_CLOCK_432MHZ = VPU_CLOCK_432MHZ, 243 E_VPU_EX_CLOCK_384MHZ = VPU_CLOCK_384MHZ, 244 245 } VPU_EX_ClockSpeed; 246 247 248 typedef enum 249 { 250 E_HAL_VPU_STREAM_NONE = 0x0, 251 252 //Support TSP/TS File/File mode 253 E_HAL_VPU_MAIN_STREAM_BASE = 0x10, 254 E_HAL_VPU_MAIN_STREAM0 = E_HAL_VPU_MAIN_STREAM_BASE, 255 E_HAL_VPU_MAIN_STREAM_MAX, 256 257 //Only support file mode 258 E_HAL_VPU_SUB_STREAM_BASE = 0x20, 259 E_HAL_VPU_SUB_STREAM0 = E_HAL_VPU_SUB_STREAM_BASE, 260 E_HAL_VPU_SUB_STREAM_MAX, 261 262 #ifdef VDEC3 263 E_HAL_VPU_N_STREAM_BASE = 0x40, 264 E_HAL_VPU_N_STREAM0 = E_HAL_VPU_N_STREAM_BASE, 265 E_HAL_VPU_N_STREAM_MAX = E_HAL_VPU_N_STREAM0 + VPU_MAX_DEC_NUM, 266 #endif 267 268 //Only support MVC stream 269 E_HAL_VPU_MVC_STREAM_BASE = 0xF0, 270 E_HAL_VPU_MVC_MAIN_VIEW = E_HAL_VPU_MVC_STREAM_BASE, 271 E_HAL_VPU_MVC_SUB_VIEW, 272 E_HAL_VPU_MVC_STREAM_MAX, 273 } HAL_VPU_StreamId; 274 275 typedef enum 276 { 277 //Support TSP/TS/File mode 278 E_HAL_VPU_MAIN_STREAM, 279 280 //Only support file mode 281 E_HAL_VPU_SUB_STREAM, 282 283 //Only support MVC mode 284 E_HAL_VPU_MVC_STREAM, 285 286 #ifdef VDEC3 287 E_HAL_VPU_N_STREAM, 288 #endif 289 } HAL_VPU_StreamType; 290 291 typedef enum 292 { 293 //Support TSP/TS/File mode 294 E_VPU_EX_INPUT_TSP, 295 //Only support file mode 296 E_VPU_EX_INPUT_FILE, 297 E_VPU_EX_INPUT_NONE, 298 } VPU_EX_SourceType; 299 300 typedef enum 301 { 302 E_VPU_EX_UART_LEVEL_NONE = 0, ///< Disable all uart message. 303 E_VPU_EX_UART_LEVEL_ERR, ///< Only output error message 304 E_VPU_EX_UART_LEVEL_INFO, ///< output general message, and above. 305 E_VPU_EX_UART_LEVEL_DBG, ///< output debug message, and above. 306 E_VPU_EX_UART_LEVEL_TRACE, ///< output function trace message, and above. 307 E_VPU_EX_UART_LEVEL_FW, ///< output FW message, and above. 308 } VPU_EX_UartLevel; 309 310 typedef enum 311 { 312 E_VPU_EX_FW_VER_CTRLR = 0, 313 E_VPU_EX_FW_VER_MVD_FW, 314 E_VPU_EX_FW_VER_HVD_FW, 315 E_VPU_EX_FW_VER_MVD_IF, 316 E_VPU_EX_FW_VER_HVD_IF, 317 } VPU_EX_FWVerType; 318 319 /// DecodeMode for f/w tasks 320 typedef enum 321 { 322 E_VPU_DEC_MODE_DUAL_INDIE, ///< Two independent tasks 323 E_VPU_DEC_MODE_DUAL_3D, ///< Two dependent tasks for 3D 324 E_VPU_DEC_MODE_SINGLE, ///< One task use the whole SRAM 325 E_VPU_DEC_MODE_MVC = E_VPU_DEC_MODE_SINGLE, 326 } VPU_EX_DecMode; 327 328 /// CmdMode for KOREA3D or PIP mode 329 typedef enum 330 { 331 //Group1:Set Korea3DTV mode 332 E_VPU_CMD_MODE_KR3D_BASE = 0x0000, 333 E_VPU_CMD_MODE_KR3D_INTERLACE = E_VPU_CMD_MODE_KR3D_BASE, 334 E_VPU_CMD_MODE_KR3D_FORCE_P, 335 E_VPU_CMD_MODE_KR3D_INTERLACE_TWO_PITCH, 336 E_VPU_CMD_MODE_KR3D_FORCE_P_TWO_PITCH, 337 338 //Group2:Set PIP mode 339 E_VPU_CMD_MODE_PIP_BASE = 0x1000, 340 E_VPU_CMD_MODE_PIP_SYNC_INDIE = E_VPU_CMD_MODE_PIP_BASE, 341 E_VPU_CMD_MODE_PIP_SYNC_MAIN_STC, 342 E_VPU_CMD_MODE_PIP_SYNC_SWITCH 343 } VPU_EX_CmdMode; 344 345 /// input source select enumerator 346 typedef enum 347 { 348 ///DTV mode 349 E_VPU_EX_SRC_MODE_DTV = 0, 350 ///TS file mode 351 E_VPU_EX_SRC_MODE_TS_FILE, 352 ///generic file mode 353 E_VPU_EX_SRC_MODE_FILE, 354 /// TS file and dual ES buffer mode 355 E_VPU_EX_SRC_MODE_TS_FILE_DUAL_ES, 356 ///generic file and dual ES buffer mode 357 E_VPU_EX_SRC_MODE_FILE_DUAL_ES, 358 } VPU_EX_SrcMode; 359 360 /// codec type enumerator 361 typedef enum 362 { 363 ///unsupported codec type 364 E_VPU_EX_CODEC_TYPE_NONE = 0, 365 ///MPEG 1/2 366 E_VPU_EX_CODEC_TYPE_MPEG2, 367 ///H263 (short video header) 368 E_VPU_EX_CODEC_TYPE_H263, 369 ///MPEG4 (default) 370 E_VPU_EX_CODEC_TYPE_MPEG4, 371 ///MPEG4 (Divx311) 372 E_VPU_EX_CODEC_TYPE_DIVX311, 373 ///MPEG4 (Divx412) 374 E_VPU_EX_CODEC_TYPE_DIVX412, 375 ///FLV 376 E_VPU_EX_CODEC_TYPE_FLV, 377 ///VC1 advanced profile (VC1) 378 E_VPU_EX_CODEC_TYPE_VC1_ADV, 379 ///VC1 main profile (RCV) 380 E_VPU_EX_CODEC_TYPE_VC1_MAIN, 381 ///Real Video version 8 382 E_VPU_EX_CODEC_TYPE_RV8, 383 ///Real Video version 9 and 10 384 E_VPU_EX_CODEC_TYPE_RV9, 385 ///H264 386 E_VPU_EX_CODEC_TYPE_H264, 387 ///AVS 388 E_VPU_EX_CODEC_TYPE_AVS, 389 ///MJPEG 390 E_VPU_EX_CODEC_TYPE_MJPEG, 391 ///MVC 392 E_VPU_EX_CODEC_TYPE_MVC, 393 ///VP8 394 E_VPU_EX_CODEC_TYPE_VP8, 395 ///HEVC 396 E_VPU_EX_CODEC_TYPE_HEVC, 397 ///VP9 398 E_VPU_EX_CODEC_TYPE_VP9, 399 // HEVC Dolby vision 400 E_VPU_EX_CODEC_TYPE_HEVC_DV, 401 E_VPU_EX_CODEC_TYPE_NUM 402 } VPU_EX_CodecType; 403 404 /// record origin stream type for VPU hal 405 typedef enum 406 { 407 E_VPU_ORIGINAL_MAIN_STREAM = 0, 408 E_VPU_ORIGINAL_SUB_STREAM, 409 E_VPU_ORIGINAL_N_STREAM, 410 } VPU_EX_Original_Stream; 411 412 typedef struct 413 { 414 VPU_EX_ClockSpeed eClockSpeed; 415 MS_BOOL bClockInv; 416 MS_S32 s32VPUMutexID; 417 MS_U32 u32VPUMutexTimeout; 418 MS_U8 u8MiuSel; 419 } VPU_EX_InitParam; 420 421 typedef struct 422 { 423 MS_U32 u32Id; 424 HAL_VPU_StreamId eVpuId; 425 VPU_EX_SourceType eSrcType; 426 VPU_EX_DecoderType eDecType; 427 MS_U8 u8HalId; // hal MVD/HVD id 428 MS_U32 u32HeapSize; 429 } VPU_EX_TaskInfo; 430 431 typedef struct 432 { 433 MS_VIRT u32DstAddr; 434 MS_VIRT u32DstSize; 435 MS_VIRT u32BinSize; 436 MS_VIRT u32BinAddr; 437 MS_U8 u8SrcType; 438 } VPU_EX_FWCodeCfg; 439 440 typedef struct 441 { 442 MS_VIRT u32DstAddr; 443 MS_VIRT u32BinAddr; 444 MS_VIRT u32BinSize; 445 MS_VIRT u32FrameBufAddr; 446 MS_VIRT u32VLCTableOffset; 447 } VPU_EX_VLCTblCfg; 448 449 #ifdef VDEC3 450 typedef struct 451 { 452 MS_VIRT u32FrameBufAddr; 453 MS_VIRT u32FrameBufSize; 454 } VPU_EX_FBCfg; 455 #endif 456 457 /// VPU init parameters for dual decoder 458 typedef struct 459 { 460 VPU_EX_FWCodeCfg *pFWCodeCfg; 461 VPU_EX_TaskInfo *pTaskInfo; 462 VPU_EX_VLCTblCfg *pVLCCfg; 463 #ifdef VDEC3 464 VPU_EX_FBCfg *pFBCfg; 465 #endif 466 } VPU_EX_NDecInitPara; 467 468 typedef struct 469 { 470 MS_U8 u8DecMod; 471 MS_U8 u8CodecCnt; 472 MS_U8 u8CodecType[VPU_MAX_DEC_NUM]; 473 MS_U8 u8ArgSize; 474 MS_U32 u32Arg; 475 } VPU_EX_DecModCfg; 476 477 478 typedef enum 479 { 480 E_VDEC_EX_CODEC_PROFILE_NONE, 481 482 E_VDEC_EX_CODEC_PROFILE_MP2_MAIN, 483 484 E_VDEC_EX_CODEC_PROFILE_MP4_ASP, 485 486 E_VDEC_EX_CODEC_PROFILE_H263_BASELINE, 487 488 E_VDEC_EX_CODEC_PROFILE_VC1_AP, 489 490 E_VDEC_EX_CODEC_PROFILE_RCV_MAIN, 491 492 E_VDEC_EX_CODEC_PROFILE_VP9_0, 493 E_VDEC_EX_CODEC_PROFILE_VP9_2, 494 495 E_VDEC_EX_CODEC_PROFILE_H264_CBP, 496 E_VDEC_EX_CODEC_PROFILE_H264_BP, 497 E_VDEC_EX_CODEC_PROFILE_H264_XP, 498 E_VDEC_EX_CODEC_PROFILE_H264_MP, 499 E_VDEC_EX_CODEC_PROFILE_H264_HIP, 500 E_VDEC_EX_CODEC_PROFILE_H264_PHIP, 501 E_VDEC_EX_CODEC_PROFILE_H264_CHIP, 502 E_VDEC_EX_CODEC_PROFILE_H264_HI10P, 503 E_VDEC_EX_CODEC_PROFILE_H264_HI422P, 504 E_VDEC_EX_CODEC_PROFILE_H264_HI444PP, 505 506 E_VDEC_EX_CODEC_PROFILE_H265_MAIN, 507 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_10, 508 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_12, 509 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_422_10, 510 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_422_12, 511 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_444, 512 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_444_10, 513 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_444_12, 514 515 E_VDEC_EX_CODEC_PROFILE_AVS_BROADCASTING, 516 517 518 } VDEC_EX_CODEC_CAP_PROFILE_INFO; 519 520 typedef enum 521 { 522 E_VDEC_EX_CODEC_LEVEL_NONE, 523 524 E_VDEC_EX_CODEC_LEVEL_MP2_HIGH, 525 526 E_VDEC_EX_CODEC_LEVEL_MP4_L5, 527 528 E_VDEC_EX_CODEC_LEVEL_VC1_L3, 529 530 E_VDEC_EX_CODEC_LEVEL_RCV_HIGH, 531 532 533 E_VDEC_EX_CODEC_LEVEL_H264_1, 534 E_VDEC_EX_CODEC_LEVEL_H264_1B, 535 E_VDEC_EX_CODEC_LEVEL_H264_1_1, 536 E_VDEC_EX_CODEC_LEVEL_H264_1_2, 537 E_VDEC_EX_CODEC_LEVEL_H264_1_3, 538 E_VDEC_EX_CODEC_LEVEL_H264_2, 539 E_VDEC_EX_CODEC_LEVEL_H264_2_1, 540 E_VDEC_EX_CODEC_LEVEL_H264_2_2, 541 E_VDEC_EX_CODEC_LEVEL_H264_3, 542 E_VDEC_EX_CODEC_LEVEL_H264_3_1, 543 E_VDEC_EX_CODEC_LEVEL_H264_3_2, 544 E_VDEC_EX_CODEC_LEVEL_H264_4, 545 E_VDEC_EX_CODEC_LEVEL_H264_4_1, 546 E_VDEC_EX_CODEC_LEVEL_H264_4_2, 547 E_VDEC_EX_CODEC_LEVEL_H264_5, 548 E_VDEC_EX_CODEC_LEVEL_H264_5_1, 549 E_VDEC_EX_CODEC_LEVEL_H264_5_2, 550 551 E_VDEC_EX_CODEC_LEVEL_H265_1, 552 E_VDEC_EX_CODEC_LEVEL_H265_2, 553 E_VDEC_EX_CODEC_LEVEL_H265_2_1, 554 E_VDEC_EX_CODEC_LEVEL_H265_3, 555 E_VDEC_EX_CODEC_LEVEL_H265_3_1, 556 E_VDEC_EX_CODEC_LEVEL_H265_4_MT, 557 E_VDEC_EX_CODEC_LEVEL_H265_4_HT, 558 E_VDEC_EX_CODEC_LEVEL_H265_4_1_MT, 559 E_VDEC_EX_CODEC_LEVEL_H265_4_1_HT, 560 E_VDEC_EX_CODEC_LEVEL_H265_5_MT, 561 E_VDEC_EX_CODEC_LEVEL_H265_5_HT, 562 E_VDEC_EX_CODEC_LEVEL_H265_5_1_MT, 563 E_VDEC_EX_CODEC_LEVEL_H265_5_1_HT, 564 E_VDEC_EX_CODEC_LEVEL_H265_5_2_MT, 565 E_VDEC_EX_CODEC_LEVEL_H265_5_2_HT, 566 E_VDEC_EX_CODEC_LEVEL_H265_6_MT, 567 E_VDEC_EX_CODEC_LEVEL_H265_6_HT, 568 E_VDEC_EX_CODEC_LEVEL_H265_6_1_MT, 569 E_VDEC_EX_CODEC_LEVEL_H265_6_1_HT, 570 E_VDEC_EX_CODEC_LEVEL_H265_6_2_MT, 571 E_VDEC_EX_CODEC_LEVEL_H265_6_2_HT, 572 573 E_VDEC_EX_CODEC_LEVEL_AVS_6010860, 574 575 } VDEC_EX_CODEC_CAP_LEVEL_INFO; 576 577 578 typedef enum 579 { 580 E_VDEC_EX_CODEC_VERSION_NONE, 581 582 E_VDEC_EX_CODEC_VERSION_DIVX_311, 583 E_VDEC_EX_CODEC_VERSION_DIVX_4, 584 E_VDEC_EX_CODEC_VERSION_DIVX_5, 585 E_VDEC_EX_CODEC_VERSION_DIVX_6, 586 587 E_VDEC_EX_CODEC_VERSION_FLV_1, 588 589 E_VDEC_EX_CODEC_VERSION_H263_1, 590 591 } VDEC_EX_CODEC_CAP_VERSION_INFO; 592 593 typedef struct DLL_PACKED 594 { 595 MS_U16 u16CodecCapWidth; 596 MS_U16 u16CodecCapHeight; 597 MS_U8 u8CodecCapFrameRate; 598 VDEC_EX_CODEC_CAP_PROFILE_INFO u8CodecCapProfile; 599 VDEC_EX_CODEC_CAP_VERSION_INFO u8CodecCapVersion; 600 VDEC_EX_CODEC_CAP_LEVEL_INFO u8CodecCapLevel; 601 MS_U32 u32CodecType; 602 MS_U32 u32Reserved1; 603 }VDEC_EX_CODEC_CAP_INFO; 604 605 //------------------------------------------------------------------------------------------------- 606 // Function and Variable 607 //------------------------------------------------------------------------------------------------- 608 MS_BOOL HAL_VPU_EX_SetSTCMode(MS_U32 u32Id, MS_U32 u32STCIndex); 609 MS_BOOL HAL_VPU_EX_SetDecodeMode(VPU_EX_DecModCfg *pstCfg); 610 MS_BOOL HAL_VPU_EX_SetSingleDecodeMode(MS_BOOL bEnable); 611 #ifdef VDEC3 612 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara, MS_BOOL bFWdecideFB, MS_U32 u32BBUId); 613 #else 614 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara); 615 #endif 616 MS_BOOL HAL_VPU_EX_TaskDelete(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara); 617 MS_BOOL HAL_VPU_EX_SetFWReload(MS_BOOL bReload); 618 619 MS_BOOL HAL_VPU_EX_LoadCode(VPU_EX_FWCodeCfg *pFWCodeCfg); 620 void HAL_VPU_EX_InitRegBase(MS_VIRT u32RegBase); 621 622 HAL_VPU_StreamId HAL_VPU_EX_GetFreeStream(HAL_VPU_StreamType eStreamType); 623 MS_BOOL HAL_VPU_EX_Init(VPU_EX_InitParam *InitParams); 624 MS_BOOL HAL_VPU_EX_DeInit(void); 625 void HAL_VPU_EX_PowerCtrl(MS_BOOL bEnable); 626 void HAL_VPU_EX_MIU_RW_Protect(MS_BOOL bEnable); 627 MS_BOOL HAL_VPU_EX_CPUSetting(MS_PHY u32StAddr); 628 MS_BOOL HAL_VPU_EX_SwRst(MS_BOOL bCheckMauIdle); 629 void HAL_VPU_EX_SwRstRelse(void); 630 void HAL_VPU_EX_SwRelseMAU(void); 631 MS_U32 HAL_VPU_EX_MemRead(MS_VIRT u32Address); 632 MS_BOOL HAL_VPU_EX_MemWrite(MS_VIRT u32Address, MS_U32 u32Value); 633 MS_BOOL HAL_VPU_EX_MBoxRdy(MS_U32 u32type); 634 MS_BOOL HAL_VPU_EX_MBoxRead(MS_U32 u32type, MS_U32 *u32Msg); 635 void HAL_VPU_EX_MBoxClear(MS_U32 u32type); 636 MS_BOOL HAL_VPU_EX_MBoxSend(MS_U32 u32type, MS_U32 u32Msg); 637 MS_U32 HAL_VPU_EX_GetProgCnt(void); 638 MS_U8 HAL_VPU_EX_GetTaskId(MS_U32 u32Id); 639 void HAL_VPU_EX_SetShareInfoAddr(MS_U32 u32Id, MS_VIRT u32ShmAddr); 640 MS_VIRT HAL_VPU_EX_GetShareInfoAddr(MS_U32 u32Id); 641 MS_VIRT HAL_VPU_EX_GetVsyncAddrOffset(MS_U32 u32Id); 642 MS_VIRT HAL_VPU_EX_GetVsyncExtAddrOffset(MS_U32 u32Id); 643 MS_BOOL HAL_VPU_EX_IsPowered(void); 644 MS_BOOL HAL_VPU_EX_IsRsted(void); 645 MS_BOOL HAL_VPU_EX_IsEVDR2(void); 646 MS_BOOL HAL_VPU_EX_MVDInUsed(void); 647 MS_BOOL HAL_VPU_EX_HVDInUsed(void); 648 #ifdef VDEC3 649 MS_BOOL HAL_VPU_EX_EVDInUsed(void); 650 #if SUPPORT_G2VP9 651 MS_BOOL HAL_VPU_EX_G2VP9InUsed(void); 652 #endif 653 #endif 654 void HAL_VPU_EX_IQMemSetDAMode(MS_BOOL bEnable); 655 void HAL_VPU_EX_SetDbgLevel(VPU_EX_UartLevel eLevel); 656 MS_U32 HAL_VPU_EX_GetFWVer(MS_U32 u32Id, VPU_EX_FWVerType eVerType); 657 MS_BOOL HAL_VPU_EX_Init_Share_Mem(void); 658 MS_BOOL HAL_VPU_EX_CHIP_Capability(void* pHWCap); 659 MS_BOOL HAL_VPU_EX_GetCodecCapInfo( int eCodecType, VDEC_EX_CODEC_CAP_INFO *pCodecCapInfo); 660 MS_U8 HAL_VPU_EX_GetOffsetIdx(MS_U32 u32Id); 661 MS_PHY HAL_VPU_EX_GetFWCodeAddr(MS_U32 u32Id); 662 void HAL_VPU_EX_Mutex_Lock(void); 663 void HAL_VPU_EX_Mutex_UnLock(void); 664 665 MS_VIRT HAL_VPU_EX_MIU1BASE(void); 666 MS_VIRT HAL_VPU_EX_GetSHMAddr(void); 667 MS_BOOL HAL_VPU_EX_EnableSecurityMode(MS_BOOL enable); 668 MS_BOOL HAL_VPU_EX_REE_SetSHMBaseAddr(MS_U32 U32Type,MS_PHY u32SHMAddr,MS_PHY u32SHMSize,MS_PHY u32MIU1Addr); 669 MS_BOOL HAL_VPU_EX_REE_RegisterMBX(void); 670 MS_BOOL HAL_VPU_Set_MBX_param(MS_U8 u8APIMbxMsgClass); 671 672 void HAL_VPU_EX_ForceSwRst(void); 673 674 #ifdef VDEC3 675 typedef enum 676 { 677 E_HVD_CMDQ_CMD, 678 E_HVD_CMDQ_ARG, 679 } HVD_COMMAND_QUEUE_TYPE; 680 681 typedef enum 682 { 683 E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL, 684 E_HVD_COMMAND_QUEUE_NOT_INITIALED, 685 E_HVD_COMMAND_QUEUE_FULL, 686 E_HVD_COMMAND_QUEUE_SEND_FAIL, 687 } HVD_DRAM_COMMAND_QUEUE_SEND_STATUS; 688 689 690 typedef struct 691 { 692 MS_VIRT u32Offset; ///< Packet offset from bitstream buffer base address. unit: byte. 693 MS_U32 u32Length; ///< Packet size. unit: byte. ==> Move _VDEC_EX_ReparseVP8Packet to FW 694 MS_U64 u64TimeStamp; ///< Packet time stamp. unit: ms. 695 MS_U32 u32ID_L; ///< Packet ID low part. 696 MS_U32 u32ID_H; ///< Packet ID high part. 697 MS_U8 u8Version; ///< Packet version 0 means u32Offset is the offset of ES buffer 698 ///< 1 means u32Offset is used as esHandleID 699 } HAL_VPU_EX_PacketInfo; 700 // *****************Virtual BBU function***************** 701 MS_BOOL HAL_VPU_EX_Push2VBBU(MS_U32 u32Id, HAL_VPU_EX_PacketInfo *stVpuPkt, MS_VIRT u32VBBUAddr); 702 MS_U32 HAL_VPU_EX_GetVBBUVacancy(MS_VIRT u32VBBUAddr); 703 MS_VIRT HAL_VPU_EX_GetESReadPtr(MS_U32 u32Id, MS_VIRT u32VBBUAddr); 704 MS_VIRT HAL_VPU_EX_GetESWritePtr(MS_U32 u32Id, MS_VIRT u32VBBUAddr); 705 MS_BOOL HAL_VPU_EX_IsVBBUEmpty(MS_VIRT u32VBBUAddr); 706 // *****************General dram command queue function***************** 707 MS_BOOL HAL_VPU_EX_IsMailBoxCMD(MS_U32 u32Cmd); 708 MS_BOOL HAL_VPU_EX_IsDisplayQueueCMD(MS_U32 u32Cmd); 709 MS_BOOL HAL_VPU_EX_DRAMCMDQueueSend(MS_VIRT u32DramAddr, MS_U32 u32Msg); 710 // *****************Dram command queue function***************** 711 MS_BOOL HAL_VPU_EX_DRAMCMDQueueIsEmpty(void *cmd_queue); 712 MS_BOOL HAL_VPU_EX_DRAMCMDQueueIsFull(void *cmd_queue); 713 MS_U32 HAL_VPU_EX_DRAMStreamCMDQueueSend(MS_U32 u32Id, void *cmd_queue, MS_U8 u8CmdType, MS_U32 u32Msg); 714 // *****************Display dram command queue function***************** 715 MS_BOOL HAL_VPU_EX_DRAMDispCMDQueueIsEmpty(void *cmd_queue); 716 MS_BOOL HAL_VPU_EX_DRAMDispCMDQueueIsFull(void *cmd_queue); 717 MS_U32 HAL_VPU_EX_DRAMStreamDispCMDQueueSend(MS_U32 u32Id, void *cmd_queue, MS_U8 u8CmdType, MS_U32 u32Msg); 718 // *****************General purpose function***************** 719 MS_BOOL HAL_VPU_EX_SetBitstreamBufAddress(MS_U32 u32Id, MS_VIRT u32BsAddr); 720 void HAL_VPU_EX_SetBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_DecoderType eDecType, MS_U8 u8TypeBit); 721 MS_BOOL HAL_VPU_EX_CheckBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_DecoderType eDecType, MS_U8 u8TypeBit); 722 void HAL_VPU_EX_ClearBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_DecoderType eDecType); 723 MS_U32 HAL_VPU_EX_GetBBUId(MS_U32 u32Id, VPU_EX_TaskInfo *pTaskInfo, MS_BOOL bShareBBU); 724 MS_BOOL HAL_VPU_EX_FreeBBUId(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_TaskInfo *pTaskInfo); 725 MS_SIZE HAL_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType); 726 // *****************CMA function***************** 727 MS_BOOL HAL_VPU_EX_GetCMAMemSize(VPU_EX_CodecType eCodecType, VPU_EX_SrcMode eSrcMode, 728 MS_U64 *offset, MS_SIZE *length, MS_U64 total_length, MS_SIZE unUseSize); 729 MS_BOOL HAL_VPU_EX_GetCapability(MS_U8 *pu8CmdNameIn, void *pParamIn, void *pParamOut); 730 #endif 731 #ifdef VDEC3_FB 732 MS_BOOL HAL_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType); 733 #endif 734 void HAL_VPU_EX_DynamicFBMode(MS_BOOL bEnable,MS_PHY u32address,MS_U32 u32Size); 735 MS_BOOL HAL_VPU_EX_ReleaseFreeStream(MS_U8 u8Idx); 736 MS_U8 HAL_VPU_EX_CheckFreeStream(VPU_EX_Original_Stream eStream); 737 #ifdef CONFIG_MSTAR_CLKM 738 void HAL_VPU_EX_SetClkManagement(VPU_EX_ClkPortType eClkPortType, MS_BOOL bEnable); 739 #endif 740 741 #else 742 typedef struct 743 { 744 MS_PHY Bitstream_Addr_Main; 745 MS_U32 Bitstream_Len_Main; 746 MS_PHY Bitstream_Addr_Sub; 747 MS_U32 Bitstream_Len_Sub; 748 MS_PHY MIU1_BaseAddr; 749 } VPU_EX_LOCK_DOWN_REGISTER; 750 751 752 MS_BOOL HAL_VPU_EX_LoadCodeInSecure(MS_VIRT addr); 753 MS_BOOL HAL_VPU_EX_SetLockDownRegister(void* param); 754 755 #endif 756 #endif // _HAL_VPU_EX_H_ 757 758