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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _HAL_VPU_EX_H_ 96 #define _HAL_VPU_EX_H_ 97 98 //------------------------------------------------------------------------------------------------- 99 // Macro and Define 100 //------------------------------------------------------------------------------------------------- 101 #ifndef MSOS_TYPE_NUTTX 102 103 #if defined(REDLION_LINUX_KERNEL_ENVI) 104 #define ENABLE_VPU_MUTEX_PROTECTION 0 105 #define VPU_DEFAULT_MUTEX_TIMEOUT 0xFFFFFFFFUL 106 #define VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM 0 107 #else 108 #define ENABLE_VPU_MUTEX_PROTECTION 1 109 #define VPU_DEFAULT_MUTEX_TIMEOUT MSOS_WAIT_FOREVER 110 111 #if defined(FW_EXTERNAL_BIN) 112 #define VPU_ENABLE_EMBEDDED_FW_BINARY 0 113 #define VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM 1 114 #else 115 #define VPU_ENABLE_EMBEDDED_FW_BINARY 1 116 #define VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM 0 117 #endif 118 119 #endif 120 121 #define ENABLE_DECOMPRESS_FUNCTION TRUE 122 123 #define VPU_CLOCK_216MHZ BITS(4:2,0) 124 #define VPU_CLOCK_192MHZ BITS(4:2,1) 125 #define VPU_CLOCK_160MHZ BITS(4:2,2) 126 #define VPU_CLOCK_144MHZ BITS(4:2,3) 127 #define VPU_CLOCK_320MHZ BITS(4:2,4) 128 #define VPU_CLOCK_288MHZ BITS(4:2,5) 129 130 #define VPU_HI_MBOX0 0 131 #define VPU_HI_MBOX1 1 132 #define VPU_RISC_MBOX0 2 133 #define VPU_RISC_MBOX1 3 134 135 136 #define VPU_EX_TimerDelayMS(x) \ 137 do \ 138 { \ 139 volatile MS_U32 ticks = 0; \ 140 while (ticks < (((MS_U32) (x)) << 13)) \ 141 { \ 142 ticks++; \ 143 } \ 144 } while(0) 145 146 #define VPU_MAX_DEC_NUM 2 147 148 //------------------------------------------------------------------------------------------------- 149 // Type and Structure 150 //------------------------------------------------------------------------------------------------- 151 typedef enum 152 { 153 E_HAL_HVD_STREAM_NONE = 0x0, 154 155 //Support TSP/TS/File mode 156 E_HAL_HVD_MAIN_STREAM_BASE = 0x10, 157 E_HAL_HVD_MAIN_STREAM0 = E_HAL_HVD_MAIN_STREAM_BASE, 158 E_HAL_HVD_MAIN_STREAM_MAX, 159 160 //Only support file mode 161 E_HAL_HVD_SUB_STREAM_BASE = 0x20, 162 E_HAL_HVD_SUB_STREAM0 = E_HAL_HVD_SUB_STREAM_BASE, 163 E_HAL_HVD_SUB_STREAM1, 164 E_HAL_HVD_SUB_STREAM_MAX, 165 166 //Only support MVC stream 167 E_HAL_HVD_MVC_STREAM_BASE = 0xF0, 168 E_HAL_HVD_MVC_Main_View = E_HAL_HVD_MVC_STREAM_BASE, 169 E_HAL_HVD_MVC_Sub_View, 170 E_HAL_HVD_MVC_STREAM_MAX, 171 } HAL_HVD_StreamId; 172 173 typedef enum 174 { 175 E_VPU_EX_DECODER_NONE = 0, 176 E_VPU_EX_DECODER_MVD, 177 E_VPU_EX_DECODER_HVD, 178 E_VPU_EX_DECODER_MJPEG, 179 E_VPU_EX_DECODER_RVD, 180 E_VPU_EX_DECODER_MVC, 181 } VPU_EX_DecoderType; 182 183 typedef enum 184 { 185 E_VPU_EX_CLOCK_216MHZ = VPU_CLOCK_216MHZ, 186 E_VPU_EX_CLOCK_192MHZ = VPU_CLOCK_192MHZ, 187 E_VPU_EX_CLOCK_160MHZ = VPU_CLOCK_160MHZ, 188 E_VPU_EX_CLOCK_144MHZ = VPU_CLOCK_144MHZ, 189 E_VPU_EX_CLOCK_320MHZ = VPU_CLOCK_320MHZ, 190 E_VPU_EX_CLOCK_288MHZ = VPU_CLOCK_288MHZ, 191 192 } VPU_EX_ClockSpeed; 193 194 typedef enum 195 { 196 E_HAL_VPU_STREAM_NONE = 0x0, 197 198 //Support TSP/TS File/File mode 199 E_HAL_VPU_MAIN_STREAM_BASE = 0x10, 200 E_HAL_VPU_MAIN_STREAM0 = E_HAL_VPU_MAIN_STREAM_BASE, 201 E_HAL_VPU_MAIN_STREAM_MAX, 202 203 //Only support file mode 204 E_HAL_VPU_SUB_STREAM_BASE = 0x20, 205 E_HAL_VPU_SUB_STREAM0 = E_HAL_VPU_SUB_STREAM_BASE, 206 E_HAL_VPU_SUB_STREAM_MAX, 207 208 //Only support MVC stream 209 E_HAL_VPU_MVC_STREAM_BASE = 0xF0, 210 E_HAL_VPU_MVC_MAIN_VIEW = E_HAL_VPU_MVC_STREAM_BASE, 211 E_HAL_VPU_MVC_SUB_VIEW, 212 E_HAL_VPU_MVC_STREAM_MAX, 213 } HAL_VPU_StreamId; 214 215 typedef enum 216 { 217 //Support TSP/TS/File mode 218 E_HAL_VPU_MAIN_STREAM, 219 220 //Only support file mode 221 E_HAL_VPU_SUB_STREAM, 222 223 //Only support MVC mode 224 E_HAL_VPU_MVC_STREAM, 225 226 } HAL_VPU_StreamType; 227 228 typedef enum 229 { 230 //Support TSP/TS/File mode 231 E_VPU_EX_INPUT_TSP, 232 //Only support file mode 233 E_VPU_EX_INPUT_FILE, 234 E_VPU_EX_INPUT_NONE, 235 } VPU_EX_SourceType; 236 237 typedef enum 238 { 239 E_VPU_EX_UART_LEVEL_NONE = 0, ///< Disable all uart message. 240 E_VPU_EX_UART_LEVEL_ERR, ///< Only output error message 241 E_VPU_EX_UART_LEVEL_INFO, ///< output general message, and above. 242 E_VPU_EX_UART_LEVEL_DBG, ///< output debug message, and above. 243 E_VPU_EX_UART_LEVEL_TRACE, ///< output function trace message, and above. 244 E_VPU_EX_UART_LEVEL_FW, ///< output FW message, and above. 245 } VPU_EX_UartLevel; 246 247 typedef enum 248 { 249 E_VPU_EX_FW_VER_CTRLR = 0, 250 E_VPU_EX_FW_VER_MVD_FW, 251 E_VPU_EX_FW_VER_HVD_FW, 252 E_VPU_EX_FW_VER_MVD_IF, 253 E_VPU_EX_FW_VER_HVD_IF, 254 } VPU_EX_FWVerType; 255 256 /// DecodeMode for f/w tasks 257 typedef enum 258 { 259 E_VPU_DEC_MODE_DUAL_INDIE, ///< Two independent tasks 260 E_VPU_DEC_MODE_DUAL_3D, ///< Two dependent tasks for 3D 261 E_VPU_DEC_MODE_SINGLE, ///< One task use the whole SRAM 262 E_VPU_DEC_MODE_MVC = E_VPU_DEC_MODE_SINGLE, 263 } VPU_EX_DecMode; 264 265 /// CmdMode for KOREA3D or PIP mode 266 typedef enum 267 { 268 //Group1:Set Korea3DTV mode 269 E_VPU_CMD_MODE_KR3D_BASE = 0x0000, 270 E_VPU_CMD_MODE_KR3D_INTERLACE = E_VPU_CMD_MODE_KR3D_BASE, 271 E_VPU_CMD_MODE_KR3D_FORCE_P, 272 E_VPU_CMD_MODE_KR3D_INTERLACE_TWO_PITCH, 273 E_VPU_CMD_MODE_KR3D_FORCE_P_TWO_PITCH, 274 275 //Group2:Set PIP mode 276 E_VPU_CMD_MODE_PIP_BASE = 0x1000, 277 E_VPU_CMD_MODE_PIP_SYNC_INDIE = E_VPU_CMD_MODE_PIP_BASE, 278 E_VPU_CMD_MODE_PIP_SYNC_MAIN_STC, 279 E_VPU_CMD_MODE_PIP_SYNC_SWITCH 280 } VPU_EX_CmdMode; 281 282 typedef struct 283 { 284 VPU_EX_ClockSpeed eClockSpeed; 285 MS_BOOL bClockInv; 286 MS_S32 s32VPUMutexID; 287 MS_U32 u32VPUMutexTimeout; 288 MS_BOOL bInMIU1; 289 } VPU_EX_InitParam; 290 291 typedef struct 292 { 293 MS_U32 u32Id; 294 HAL_VPU_StreamId eVpuId; 295 VPU_EX_SourceType eSrcType; 296 VPU_EX_DecoderType eDecType; 297 MS_U8 u8Rsvd; 298 MS_U32 u32HeapSize; 299 } VPU_EX_TaskInfo; 300 301 typedef struct 302 { 303 MS_VIRT u32DstAddr; 304 MS_VIRT u32DstSize; 305 MS_VIRT u32BinSize; 306 MS_VIRT u32BinAddr; 307 MS_U8 u8SrcType; 308 } VPU_EX_FWCodeCfg; 309 310 typedef struct 311 { 312 MS_VIRT u32DstAddr; 313 MS_VIRT u32BinAddr; 314 MS_VIRT u32BinSize; 315 MS_VIRT u32FrameBufAddr; 316 MS_VIRT u32VLCTableOffset; 317 } VPU_EX_VLCTblCfg; 318 319 /// VPU init parameters for dual decoder 320 typedef struct 321 { 322 VPU_EX_FWCodeCfg *pFWCodeCfg; 323 VPU_EX_TaskInfo *pTaskInfo; 324 VPU_EX_VLCTblCfg *pVLCCfg; 325 } VPU_EX_NDecInitPara; 326 327 typedef struct 328 { 329 MS_U8 u8DecMod; 330 MS_U8 u8CodecCnt; 331 MS_U8 u8CodecType[VPU_MAX_DEC_NUM]; 332 MS_U8 u8ArgSize; 333 MS_U32 u32Arg; 334 } VPU_EX_DecModCfg; 335 336 //------------------------------------------------------------------------------------------------- 337 // Function and Variable 338 //------------------------------------------------------------------------------------------------- 339 MS_BOOL HAL_VPU_EX_SetDecodeMode(VPU_EX_DecModCfg *pstCfg); 340 MS_BOOL HAL_VPU_EX_SetSingleDecodeMode(MS_BOOL bEnable); 341 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara); 342 MS_BOOL HAL_VPU_EX_TaskDelete(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara); 343 MS_BOOL HAL_VPU_EX_SetFWReload(MS_BOOL bReload); 344 345 MS_BOOL HAL_VPU_EX_LoadCode(VPU_EX_FWCodeCfg *pFWCodeCfg); 346 void HAL_VPU_EX_InitRegBase(MS_VIRT u32RegBase); 347 348 HAL_VPU_StreamId HAL_VPU_EX_GetFreeStream(HAL_VPU_StreamType eStreamType); 349 MS_BOOL HAL_VPU_EX_Init(VPU_EX_InitParam *InitParams); 350 MS_BOOL HAL_VPU_EX_DeInit(void); 351 void HAL_VPU_EX_PowerCtrl(MS_BOOL bEnable); 352 void HAL_VPU_EX_MIU_RW_Protect(MS_BOOL bEnable); 353 MS_BOOL HAL_VPU_EX_CPUSetting(MS_U32 u32StAddr); 354 MS_BOOL HAL_VPU_EX_SwRst(MS_BOOL bCheckMauIdle); 355 void HAL_VPU_EX_SwRstRelse(void); 356 void HAL_VPU_EX_SwRelseMAU(void); 357 MS_U32 HAL_VPU_EX_MemRead(MS_U32 u32Address); 358 MS_BOOL HAL_VPU_EX_MemWrite(MS_U32 u32Address, MS_U32 u32Value); 359 MS_BOOL HAL_VPU_EX_MBoxRdy(MS_U32 u32type); 360 MS_BOOL HAL_VPU_EX_MBoxRead(MS_U32 u32type, MS_U32 *u32Msg); 361 void HAL_VPU_EX_MBoxClear(MS_U32 u32type); 362 MS_BOOL HAL_VPU_EX_MBoxSend(MS_U32 u32type, MS_U32 u32Msg); 363 MS_U32 HAL_VPU_EX_GetProgCnt(void); 364 MS_U8 HAL_VPU_EX_GetTaskId(MS_U32 u32Id); 365 void HAL_VPU_EX_SetShareInfoAddr(MS_U32 u32Id, MS_VIRT u32ShmAddr); 366 MS_VIRT HAL_VPU_EX_GetShareInfoAddr(MS_U32 u32Id); 367 MS_BOOL HAL_VPU_EX_IsPowered(void); 368 MS_BOOL HAL_VPU_EX_IsRsted(void); 369 MS_BOOL HAL_VPU_EX_MVDInUsed(void); 370 MS_BOOL HAL_VPU_EX_HVDInUsed(void); 371 372 void HAL_VPU_EX_SetDbgLevel(VPU_EX_UartLevel eLevel); 373 MS_U32 HAL_VPU_EX_GetFWVer(MS_U32 u32Id, VPU_EX_FWVerType eVerType); 374 MS_BOOL HAL_VPU_EX_Init_Share_Mem(void); 375 376 MS_VIRT HAL_VPU_EX_MIU1BASE(void); 377 MS_VIRT HAL_VPU_EX_GetSHMAddr(void); 378 MS_BOOL HAL_VPU_EX_EnableSecurityMode(MS_BOOL enable); 379 MS_BOOL HAL_VPU_EX_REE_SetSHMBaseAddr(void); 380 MS_BOOL HAL_VPU_EX_REE_RegisterMBX(void); 381 MS_BOOL HAL_VPU_EX_CHIP_Capability(void* pHWCap); 382 383 #else 384 385 typedef struct 386 { 387 MS_U32 Bitstream_Addr_Main; 388 MS_U32 Bitstream_Len_Main; 389 MS_U32 Bitstream_Addr_Sub; 390 MS_U32 Bitstream_Len_Sub; 391 MS_U32 MIU1_BaseAddr; 392 } VPU_EX_LOCK_DOWN_REGISTER; 393 394 395 MS_BOOL HAL_VPU_EX_LoadCodeInSecure(MS_U32 addr); 396 MS_BOOL HAL_VPU_EX_SetLockDownRegister(void* param); 397 398 #endif 399 400 #endif // _HAL_VPU_EX_H_ 401 402