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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _REG_VBI_H 96 #define _REG_VBI_H 97 98 #define VBI_REG_BASE 0x3700 // 0x3700 - 0x37FF 99 #define AFEC_REG_BASE 0x3500 // 0x3500 - 0x35FF 100 #define CHIP_REG_BASE 0x1E00 // 0x1E00 - 0x1EFF 101 #define ADC_ATOP_REG_BASE 0x2500 // 0x2500 - 0x25FF 102 103 #define BK_REG_L( x, y ) ((x) | (((y) << 1))) 104 #define BK_REG_H( x, y ) (((x) | (((y) << 1))) + 1) 105 106 #define CC_BUF_BIT 28 107 #define TTX_BUF_BIT 28 108 //////////////////////////////////////////////////////////////////////////////// 109 // VBI register 110 //////////////////////////////////////////////////////////////////////////////// 111 #define BK_VBI_1D (VBI_REG_BASE+0x1D) 112 #define BK_VBI_2A (VBI_REG_BASE+0x2A) 113 #define BK_VBI_40 (VBI_REG_BASE+0x40) 114 #define BK_VBI_41 (VBI_REG_BASE+0x41) 115 #define BK_VBI_42 (VBI_REG_BASE+0x42) 116 #define BK_VBI_44 (VBI_REG_BASE+0x44) 117 #define BK_VBI_45 (VBI_REG_BASE+0x45) 118 #define BK_VBI_46 (VBI_REG_BASE+0x46) 119 #define BK_VBI_4A (VBI_REG_BASE+0x4A) 120 #define BK_VBI_4B (VBI_REG_BASE+0x4B) 121 #define BK_VBI_4D (VBI_REG_BASE+0x4D) 122 #define BK_VBI_4F (VBI_REG_BASE+0x4F) 123 #define BK_VBI_50 (VBI_REG_BASE+0x50) 124 #define BK_VBI_51 (VBI_REG_BASE+0x51) 125 #define BK_VBI_53 (VBI_REG_BASE+0x53) 126 #define BK_VBI_55 (VBI_REG_BASE+0x55) 127 #define BK_VBI_56 (VBI_REG_BASE+0x56) 128 #define BK_VBI_57 (VBI_REG_BASE+0x57) 129 #define BK_VBI_58 (VBI_REG_BASE+0x58) 130 #define BK_VBI_59 (VBI_REG_BASE+0x59) 131 #define BK_VBI_5A (VBI_REG_BASE+0x5A) 132 #define BK_VBI_5B (VBI_REG_BASE+0x5B) 133 #define BK_VBI_5C (VBI_REG_BASE+0x5C) 134 #define BK_VBI_5D (VBI_REG_BASE+0x5D) 135 #define BK_VBI_5E (VBI_REG_BASE+0x5E) 136 #define BK_VBI_5F (VBI_REG_BASE+0x5F) 137 #define BK_VBI_70 (VBI_REG_BASE+0x70) 138 #define BK_VBI_71 (VBI_REG_BASE+0x71) 139 #define BK_VBI_72 (VBI_REG_BASE+0x72) 140 #define BK_VBI_77 (VBI_REG_BASE+0x77) 141 #define BK_VBI_7C (VBI_REG_BASE+0x7C) 142 #define BK_VBI_7D (VBI_REG_BASE+0x7D) 143 #define BK_VBI_7E (VBI_REG_BASE+0x7E) 144 #define BK_VBI_7F (VBI_REG_BASE+0x7F) 145 #define BK_VBI_81 (VBI_REG_BASE+0x81) 146 #define BK_VBI_82 (VBI_REG_BASE+0x82) 147 #define BK_VBI_83 (VBI_REG_BASE+0x83) 148 #define BK_VBI_86 (VBI_REG_BASE+0x86) 149 #define BK_VBI_89 (VBI_REG_BASE+0x89) 150 #define BK_VBI_8A (VBI_REG_BASE+0x8A) 151 #define BK_VBI_8B (VBI_REG_BASE+0x8B) 152 #define BK_VBI_8D (VBI_REG_BASE+0x8D) 153 #define BK_VBI_90 (VBI_REG_BASE+0x90) 154 #define BK_VBI_91 (VBI_REG_BASE+0x91) 155 #define BK_VBI_92 (VBI_REG_BASE+0x92) 156 #define BK_VBI_99 (VBI_REG_BASE+0x99) 157 #define BK_VBI_9A (VBI_REG_BASE+0x9A) 158 #define BK_VBI_A6 (VBI_REG_BASE+0xA6) 159 #define BK_VBI_A7 (VBI_REG_BASE+0xA7) 160 #define BK_VBI_AD (VBI_REG_BASE+0xAD) 161 #define BK_VBI_AE (VBI_REG_BASE+0xAE) 162 #define BK_VBI_AF (VBI_REG_BASE+0xAF) 163 #define BK_VBI_B4 (VBI_REG_BASE+0xB4) 164 #define BK_VBI_B5 (VBI_REG_BASE+0xB5) 165 #define BK_VBI_B7 (VBI_REG_BASE+0xB7) 166 #define BK_VBI_B8 (VBI_REG_BASE+0xB8) 167 #define BK_VBI_BB (VBI_REG_BASE+0xBB) 168 #define BK_VBI_BF (VBI_REG_BASE+0xBF) 169 #define BK_VBI_C4 (VBI_REG_BASE+0xC4) 170 #define BK_VBI_CA (VBI_REG_BASE+0xCA) 171 #define BK_VBI_CB (VBI_REG_BASE+0xCB) 172 #define BK_VBI_CC (VBI_REG_BASE+0xCC) 173 #define BK_VBI_CD (VBI_REG_BASE+0xCD) 174 #define BK_VBI_CE (VBI_REG_BASE+0xCE) 175 176 #define BK_VBI_DE (VBI_REG_BASE+0xDE) 177 #define BK_VBI_DF (VBI_REG_BASE+0xDF) 178 #define BK_VBI_E0 (VBI_REG_BASE+0xE0) 179 #define BK_VBI_E1 (VBI_REG_BASE+0xE1) 180 #define BK_VBI_E2 (VBI_REG_BASE+0xE2) 181 #define BK_VBI_E3 (VBI_REG_BASE+0xE3) 182 #define BK_VBI_E4 (VBI_REG_BASE+0xE4) 183 #define BK_VBI_E5 (VBI_REG_BASE+0xE5) 184 #define BK_VBI_E6 (VBI_REG_BASE+0xE6) 185 #define BK_VBI_E7 (VBI_REG_BASE+0xE7) 186 187 #define VBI_INTERRUPT_MASK 0x6C + (VBI_REG_BASE) 188 #define VBI_INTERRUPT_CLEAR 0x6D + (VBI_REG_BASE) 189 #define VBI_INTERRUPT_STATUS 0x6E + (VBI_REG_BASE) 190 #define VBI_INTERRUPT_RAW 0x6F + (VBI_REG_BASE) 191 192 #define VBI_VPS_COUNT 0xA5 + (VBI_REG_BASE) 193 #define VBI_WSS_COUNT 0xA5 + (VBI_REG_BASE) 194 195 //////////////////////////////////////////////////////////////////////////////// 196 // Other registers 197 //////////////////////////////////////////////////////////////////////////////// 198 #define BK_AFEC_6B (AFEC_REG_BASE + 0x6B) 199 #define L_BK_ADC_ATOP(x) BK_REG_L(ADC_ATOP_REG_BASE, x) 200 #define H_BK_ADC_ATOP(x) BK_REG_H(ADC_ATOP_REG_BASE, x) 201 #define L_BK_CHIPTOP(x) BK_REG_L(CHIP_REG_BASE, x) 202 #define H_BK_CHIPTOP(x) BK_REG_H(CHIP_REG_BASE, x) 203 204 /********************************************************************************/ 205 /* Start of Teletext Register definitions */ 206 /********************************************************************************/ 207 #define TT_ENABLE 0x10 + (VBI_REG_BASE) 208 209 // DMA and Tag Search Register 210 #define DMASRC_ADR_L 0x11 + (VBI_REG_BASE) // DMA Source Linear Address 211 #define DMASRC_ADR_M 0x12 + (VBI_REG_BASE) 212 #define DMASRC_ADR_H 0x13 + (VBI_REG_BASE) 213 214 #define DMADES_ADR_L 0x14 + (VBI_REG_BASE)// DMA Destination Linear Address 215 #define DMADES_ADR_M 0x15 + (VBI_REG_BASE) 216 #define DMADES_ADR_H 0x16 + (VBI_REG_BASE) 217 218 #define DMAQW_CNT_L 0x17 + (VBI_REG_BASE)// DMA Block Move Count 219 #define DMAQW_CNT_H 0x18 + (VBI_REG_BASE) 220 221 #define DMA_FUNC 0x19 + (VBI_REG_BASE)// DMA Function Seletction 222 #define DMA_HEADER 0x01 223 #define DMA_PACKET1_TO_25 0x02 224 #define DMA_BTT 0x04 225 #define DMA_AIT 0x05 226 #define DMA_MCU_READ 0x0D 227 #define DMA_MCU_WRITE 0x0E 228 #define DMA_PACKET26_28_29 0x03 229 #define DMA_PACKET27 0x06 230 #define DMA_TAG_READ 0x1D 231 #define DMA_TAG_WRITE 0x1E 232 #define DMA_ERASE 0x1F 233 234 #define DMA_COMMAND 0x1A + (VBI_REG_BASE) 235 #define DMA_READY _BIT1 236 #define DMA_FIRE _BIT0 237 238 #define DMAERASE_DATA 0x1B + (VBI_REG_BASE) 239 240 #define VBI_BIT24_ADDR 0x1D + (VBI_REG_BASE) 241 #define CCBASE_ADDR24 _BIT7 242 #define TTBASE_ADDR24 _BIT6 243 #define DMASRC_ADDR24 _BIT5 244 #define DMADES_ADDR24 _BIT4 245 #define TAGBASE_ADDR24 _BIT2 246 #define PAGEBASE_ADDR24 _BIT1 247 #define TTBASE2_ADDR24 _BIT0 248 249 #define TTDEC_COMMAND 0x1F + (VBI_REG_BASE) 250 251 #define TTDEC_STATIS 0x20 + (VBI_REG_BASE) 252 #define VBIREADY _BIT7 253 254 #define SLICERREADY 0x21 + (VBI_REG_BASE) 255 256 #define MCU_ADDR_PORT 0x22 + (VBI_REG_BASE) 257 #define BURST_RD_MD _BIT7 258 #define BURST_WR_MD _BIT6 259 260 261 #define MCU_DATA_PORT 0x23 + (VBI_REG_BASE) 262 263 #define TAGRW_POS_L 0x24 + (VBI_REG_BASE) 264 #define TAGRW_POS_H 0x25 + (VBI_REG_BASE) 265 266 #define PAGEBUF_ADDR_L 0x26 + (VBI_REG_BASE) 267 #define PAGEBUF_ADDR_M 0x27 + (VBI_REG_BASE) 268 #define PAGEBUF_ADDR_H 0x28 + (VBI_REG_BASE) 269 270 #define PAGEBUF_CNT_L 0x29 + (VBI_REG_BASE) 271 #define PAGEBUF_CNT_H 0x2A + (VBI_REG_BASE) 272 273 #define FUNCTION 0x2B + (VBI_REG_BASE) 274 275 #define TAG_MAGAZINE 0x2C + (VBI_REG_BASE) 276 #define TAG_PAGE 0x2D + (VBI_REG_BASE) 277 #define TAG_SUBCODE_H 0x2E + (VBI_REG_BASE) 278 #define TAG_SUBCODE_L 0x2F + (VBI_REG_BASE) 279 280 281 #define TAG_BASE_L 0x30 + (VBI_REG_BASE) 282 #define TAG_BASE_H 0x31 + (VBI_REG_BASE) 283 284 #define PAGE_BASE_L 0x32 + (VBI_REG_BASE) 285 #define PAGE_BASE_H 0x33 + (VBI_REG_BASE) 286 287 #define PAGE_SIZE 0x34 + (VBI_REG_BASE) // Per 8 Bytes 288 289 #define TAG_PHT_SIZE_L 0x35 + (VBI_REG_BASE) 290 #define TAG_PHT_SIZE_H 0x36 + (VBI_REG_BASE) 291 292 293 #define TAG_COMMAND 0x37 + (VBI_REG_BASE) 294 #define BUF_ADDR_RDY _BIT3 295 #define HIT_STATUS _BIT2 296 #define TAG_READY _BIT1 297 #define TAG_FIRE _BIT0 298 299 300 #define VBI_BASEADDR_L 0x38 + (VBI_REG_BASE) 301 #define VBI_BASEADDR_M 0x39 + (VBI_REG_BASE) 302 #define VBI_BASEADDR_H 0x3A + (VBI_REG_BASE) 303 #define VBI_BUF_LEN 0x3B + (VBI_REG_BASE) 304 #define VBI_BUF_LEN_H 0x3C + (VBI_REG_BASE) 305 306 #define VBI_W_COUNT 0x3D + (VBI_REG_BASE) 307 #define VBI_PKTCNT_L 0x3D + (VBI_REG_BASE) 308 309 310 #define TT_LineUpdDef 0x72 + (VBI_REG_BASE) 311 #define TT_DAT_LN_STR1 0x7C + (VBI_REG_BASE) 312 #define TT_DAT_LN_END1 0x7D + (VBI_REG_BASE) 313 #define TT_DAT_LN_STR2 0x7E + (VBI_REG_BASE) 314 #define TT_DAT_LN_END2 0x7F + (VBI_REG_BASE) 315 #define TTSLCTHRD 0x8D + (VBI_REG_BASE) 316 317 #define TT_CLK_RUN_IN_START_POINT 0x77 + (VBI_REG_BASE) 318 319 #endif 320 321