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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _REG_VBI_H 96 #define _REG_VBI_H 97 98 #define VBI_REG_BASE 0x3700 // 0x3700 - 0x37FF 99 #define AFEC_REG_BASE 0x3500 // 0x3500 - 0x35FF 100 #define CHIP_REG_BASE 0x1E00 // 0x1E00 - 0x1EFF 101 #define ADC_ATOP_REG_BASE 0x2500 // 0x2500 - 0x25FF 102 103 #define BK_REG_L( x, y ) ((x) | (((y) << 1))) 104 #define BK_REG_H( x, y ) (((x) | (((y) << 1))) + 1) 105 106 //////////////////////////////////////////////////////////////////////////////// 107 // VBI register 108 //////////////////////////////////////////////////////////////////////////////// 109 #define BK_VBI_2A (VBI_REG_BASE+0x2A) 110 #define BK_VBI_40 (VBI_REG_BASE+0x40) 111 #define BK_VBI_41 (VBI_REG_BASE+0x41) 112 #define BK_VBI_42 (VBI_REG_BASE+0x42) 113 #define BK_VBI_44 (VBI_REG_BASE+0x44) 114 #define BK_VBI_45 (VBI_REG_BASE+0x45) 115 #define BK_VBI_46 (VBI_REG_BASE+0x46) 116 #define BK_VBI_4A (VBI_REG_BASE+0x4A) 117 #define BK_VBI_4B (VBI_REG_BASE+0x4B) 118 #define BK_VBI_4D (VBI_REG_BASE+0x4D) 119 #define BK_VBI_4F (VBI_REG_BASE+0x4F) 120 #define BK_VBI_50 (VBI_REG_BASE+0x50) 121 #define BK_VBI_51 (VBI_REG_BASE+0x51) 122 #define BK_VBI_55 (VBI_REG_BASE+0x55) 123 #define BK_VBI_56 (VBI_REG_BASE+0x56) 124 #define BK_VBI_57 (VBI_REG_BASE+0x57) 125 #define BK_VBI_58 (VBI_REG_BASE+0x58) 126 #define BK_VBI_59 (VBI_REG_BASE+0x59) 127 #define BK_VBI_5A (VBI_REG_BASE+0x5A) 128 #define BK_VBI_5B (VBI_REG_BASE+0x5B) 129 #define BK_VBI_5C (VBI_REG_BASE+0x5C) 130 #define BK_VBI_5D (VBI_REG_BASE+0x5D) 131 #define BK_VBI_5E (VBI_REG_BASE+0x5E) 132 #define BK_VBI_5F (VBI_REG_BASE+0x5F) 133 #define BK_VBI_70 (VBI_REG_BASE+0x70) 134 #define BK_VBI_71 (VBI_REG_BASE+0x71) 135 #define BK_VBI_72 (VBI_REG_BASE+0x72) 136 #define BK_VBI_77 (VBI_REG_BASE+0x77) 137 #define BK_VBI_7C (VBI_REG_BASE+0x7C) 138 #define BK_VBI_7D (VBI_REG_BASE+0x7D) 139 #define BK_VBI_7E (VBI_REG_BASE+0x7E) 140 #define BK_VBI_7F (VBI_REG_BASE+0x7F) 141 #define BK_VBI_81 (VBI_REG_BASE+0x81) 142 #define BK_VBI_82 (VBI_REG_BASE+0x82) 143 #define BK_VBI_83 (VBI_REG_BASE+0x83) 144 #define BK_VBI_86 (VBI_REG_BASE+0x86) 145 #define BK_VBI_89 (VBI_REG_BASE+0x89) 146 #define BK_VBI_8A (VBI_REG_BASE+0x8A) 147 #define BK_VBI_8B (VBI_REG_BASE+0x8B) 148 #define BK_VBI_8D (VBI_REG_BASE+0x8D) 149 #define BK_VBI_91 (VBI_REG_BASE+0x91) 150 #define BK_VBI_92 (VBI_REG_BASE+0x92) 151 #define BK_VBI_99 (VBI_REG_BASE+0x99) 152 #define BK_VBI_9A (VBI_REG_BASE+0x9A) 153 #define BK_VBI_A6 (VBI_REG_BASE+0xA6) 154 #define BK_VBI_A7 (VBI_REG_BASE+0xA7) 155 #define BK_VBI_AD (VBI_REG_BASE+0xAD) 156 #define BK_VBI_AE (VBI_REG_BASE+0xAE) 157 #define BK_VBI_AF (VBI_REG_BASE+0xAF) 158 #define BK_VBI_B4 (VBI_REG_BASE+0xB4) 159 #define BK_VBI_B5 (VBI_REG_BASE+0xB5) 160 #define BK_VBI_B7 (VBI_REG_BASE+0xB7) 161 #define BK_VBI_B8 (VBI_REG_BASE+0xB8) 162 #define BK_VBI_BB (VBI_REG_BASE+0xBB) 163 #define BK_VBI_C4 (VBI_REG_BASE+0xC4) 164 #define BK_VBI_CA (VBI_REG_BASE+0xCA) 165 #define BK_VBI_CB (VBI_REG_BASE+0xCB) 166 #define BK_VBI_CC (VBI_REG_BASE+0xCC) 167 #define BK_VBI_CD (VBI_REG_BASE+0xCD) 168 #define BK_VBI_CE (VBI_REG_BASE+0xCE) 169 170 #define VBI_INTERRUPT_MASK 0x6C + (VBI_REG_BASE) 171 #define VBI_INTERRUPT_CLEAR 0x6D + (VBI_REG_BASE) 172 #define VBI_INTERRUPT_STATUS 0x6E + (VBI_REG_BASE) 173 #define VBI_INTERRUPT_RAW 0x6F + (VBI_REG_BASE) 174 175 #define VBI_VPS_COUNT 0xA5 + (VBI_REG_BASE) 176 #define VBI_WSS_COUNT 0xA5 + (VBI_REG_BASE) 177 178 //////////////////////////////////////////////////////////////////////////////// 179 // Other registers 180 //////////////////////////////////////////////////////////////////////////////// 181 #define BK_AFEC_6B (AFEC_REG_BASE + 0x6B) 182 #define L_BK_ADC_ATOP(x) BK_REG_L(ADC_ATOP_REG_BASE, x) 183 #define H_BK_ADC_ATOP(x) BK_REG_H(ADC_ATOP_REG_BASE, x) 184 #define L_BK_CHIPTOP(x) BK_REG_L(CHIP_REG_BASE, x) 185 #define H_BK_CHIPTOP(x) BK_REG_H(CHIP_REG_BASE, x) 186 187 /********************************************************************************/ 188 /* Start of Teletext Register definitions */ 189 /********************************************************************************/ 190 #define TT_ENABLE 0x10 + (VBI_REG_BASE) 191 192 // DMA and Tag Search Register 193 #define DMASRC_ADR_L 0x11 + (VBI_REG_BASE) // DMA Source Linear Address 194 #define DMASRC_ADR_M 0x12 + (VBI_REG_BASE) 195 #define DMASRC_ADR_H 0x13 + (VBI_REG_BASE) 196 197 #define DMADES_ADR_L 0x14 + (VBI_REG_BASE)// DMA Destination Linear Address 198 #define DMADES_ADR_M 0x15 + (VBI_REG_BASE) 199 #define DMADES_ADR_H 0x16 + (VBI_REG_BASE) 200 201 #define DMAQW_CNT_L 0x17 + (VBI_REG_BASE)// DMA Block Move Count 202 #define DMAQW_CNT_H 0x18 + (VBI_REG_BASE) 203 204 #define DMA_FUNC 0x19 + (VBI_REG_BASE)// DMA Function Seletction 205 #define DMA_HEADER 0x01 206 #define DMA_PACKET1_TO_25 0x02 207 #define DMA_BTT 0x04 208 #define DMA_AIT 0x05 209 #define DMA_MCU_READ 0x0D 210 #define DMA_MCU_WRITE 0x0E 211 #define DMA_PACKET26_28_29 0x03 212 #define DMA_PACKET27 0x06 213 #define DMA_TAG_READ 0x1D 214 #define DMA_TAG_WRITE 0x1E 215 #define DMA_ERASE 0x1F 216 217 #define DMA_COMMAND 0x1A + (VBI_REG_BASE) 218 #define DMA_READY _BIT1 219 #define DMA_FIRE _BIT0 220 221 #define DMAERASE_DATA 0x1B + (VBI_REG_BASE) 222 223 #define TTDEC_COMMAND 0x1F + (VBI_REG_BASE) 224 225 #define TTDEC_STATIS 0x20 + (VBI_REG_BASE) 226 #define VBIREADY _BIT7 227 228 #define SLICERREADY 0x21 + (VBI_REG_BASE) 229 230 #define MCU_ADDR_PORT 0x22 + (VBI_REG_BASE) 231 #define BURST_RD_MD _BIT7 232 #define BURST_WR_MD _BIT6 233 234 235 #define MCU_DATA_PORT 0x23 + (VBI_REG_BASE) 236 237 #define TAGRW_POS_L 0x24 + (VBI_REG_BASE) 238 #define TAGRW_POS_H 0x25 + (VBI_REG_BASE) 239 240 #define PAGEBUF_ADDR_L 0x26 + (VBI_REG_BASE) 241 #define PAGEBUF_ADDR_M 0x27 + (VBI_REG_BASE) 242 #define PAGEBUF_ADDR_H 0x28 + (VBI_REG_BASE) 243 244 #define PAGEBUF_CNT_L 0x29 + (VBI_REG_BASE) 245 #define PAGEBUF_CNT_H 0x2A + (VBI_REG_BASE) 246 247 #define FUNCTION 0x2B + (VBI_REG_BASE) 248 249 #define TAG_MAGAZINE 0x2C + (VBI_REG_BASE) 250 #define TAG_PAGE 0x2D + (VBI_REG_BASE) 251 #define TAG_SUBCODE_H 0x2E + (VBI_REG_BASE) 252 #define TAG_SUBCODE_L 0x2F + (VBI_REG_BASE) 253 254 255 #define TAG_BASE_L 0x30 + (VBI_REG_BASE) 256 #define TAG_BASE_H 0x31 + (VBI_REG_BASE) 257 258 #define PAGE_BASE_L 0x32 + (VBI_REG_BASE) 259 #define PAGE_BASE_H 0x33 + (VBI_REG_BASE) 260 261 #define PAGE_SIZE 0x34 + (VBI_REG_BASE) // Per 8 Bytes 262 263 #define TAG_PHT_SIZE_L 0x35 + (VBI_REG_BASE) 264 #define TAG_PHT_SIZE_H 0x36 + (VBI_REG_BASE) 265 266 267 #define TAG_COMMAND 0x37 + (VBI_REG_BASE) 268 #define BUF_ADDR_RDY _BIT3 269 #define HIT_STATUS _BIT2 270 #define TAG_READY _BIT1 271 #define TAG_FIRE _BIT0 272 273 274 #define VBI_BASEADDR_L 0x38 + (VBI_REG_BASE) 275 #define VBI_BASEADDR_M 0x39 + (VBI_REG_BASE) 276 #define VBI_BASEADDR_H 0x3A + (VBI_REG_BASE) 277 #define VBI_BUF_LEN 0x3B + (VBI_REG_BASE) 278 #define VBI_BUF_LEN_H 0x3C + (VBI_REG_BASE) 279 280 #define VBI_W_COUNT 0x3D + (VBI_REG_BASE) 281 #define VBI_PKTCNT_L 0x3D + (VBI_REG_BASE) 282 283 284 #define TT_LineUpdDef 0x72 + (VBI_REG_BASE) 285 #define TT_DAT_LN_STR1 0x7C + (VBI_REG_BASE) 286 #define TT_DAT_LN_END1 0x7D + (VBI_REG_BASE) 287 #define TT_DAT_LN_STR2 0x7E + (VBI_REG_BASE) 288 #define TT_DAT_LN_END2 0x7F + (VBI_REG_BASE) 289 #define TTSLCTHRD 0x8D + (VBI_REG_BASE) 290 291 #define TT_CLK_RUN_IN_START_POINT 0x77 + (VBI_REG_BASE) 292 293 #endif 294 295