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See the GNU General Public License 100 // for more details. 101 // 102 // You should have received a copy of the GNU General Public License along 103 // with eCos; if not, write to the Free Software Foundation, Inc., 104 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. 105 // 106 // As a special exception, if other files instantiate templates or use macros 107 // or inline functions from this file, or you compile this file and link it 108 // with other works to produce a work based on this file, this file does not 109 // by itself cause the resulting work to be covered by the GNU General Public 110 // License. However the source code for this file must still be made available 111 // in accordance with section (3) of the GNU General Public License. 112 // 113 // This exception does not invalidate any other reasons why a work based on 114 // this file might be covered by the GNU General Public License. 115 // 116 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. 117 // at http://sources.redhat.com/ecos/ecos-license/ 118 // ------------------------------------------- 119 //####ECOSGPLCOPYRIGHTEND#### 120 //============================================================================= 121 //#####DESCRIPTIONBEGIN#### 122 // 123 // Author(s): Scott Furman 124 // Contributors: 125 // Date: 2003-02-08 126 // Purpose: Cache control API 127 // Description: The macros defined here provide the HAL APIs for handling 128 // cache control operations. 129 // Usage: 130 // #include <cyg/hal/hal_cache.h> 131 // ... 132 // 133 // 134 //####DESCRIPTIONEND#### 135 // 136 //============================================================================= 137 138 //----------------------------------------------------------------------------- 139 // Cache dimensions. 140 // These really should be defined in var_cache.h. If they are not, then provide 141 // a set of numbers that are typical of many variants. 142 143 #ifndef HAL_DCACHE_SIZE 144 145 // Data cache 146 #ifdef __AEONR2__ 147 #define HAL_DCACHE_SIZE 32768 // Size of data cache in bytes 148 #define HAL_DCACHE_LINE_SIZE 16 // Bytes in a data cache line 149 #define HAL_DCACHE_WAYS 4 // 1 // Associativity of the cache 150 // Instruction cache 151 #define HAL_ICACHE_SIZE 16384 // 4096 // Size of cache in bytes 152 #define HAL_ICACHE_LINE_SIZE 32 // Bytes in a cache line 153 #define HAL_ICACHE_WAYS 2 // 1 // Associativity of the cache 154 #else 155 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes 156 #define HAL_DCACHE_LINE_SIZE 16 // Bytes in a data cache line 157 #define HAL_DCACHE_WAYS 2 // 1 // Associativity of the cache 158 // Instruction cache 159 #define HAL_ICACHE_SIZE 8192 // 4096 // Size of cache in bytes 160 #define HAL_ICACHE_LINE_SIZE 16 // Bytes in a cache line 161 #define HAL_ICACHE_WAYS 2 // 1 // Associativity of the cache 162 #endif 163 164 165 166 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) 167 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) 168 169 #endif 170 171 #ifndef __ASSEMBLER__ 172 173 #include "hal_arch.h" 174 #ifdef NOS_MIPS 175 void mhal_dcache_flush(unsigned long u32Base, unsigned long u32Size ); 176 #else //NOS_MIPS 177 //----------------------------------------------------------------------------- 178 // Global control of data cache 179 #ifndef __AEONR2__ 180 // Enable the data cache 181 #define HAL_DCACHE_ENABLE() MTSPR(SPR_SR, MFSPR(SPR_SR) | SPR_SR_DCE) 182 183 // Disable the data cache 184 #define HAL_DCACHE_DISABLE() MTSPR(SPR_SR, MFSPR(SPR_SR) & ~SPR_SR_DCE) 185 186 // Enable or disable the data cache, depending on argument, which is required 187 // to be 0 or 1. 188 #define HAL_SET_DCACHE_ENABLED(enable) \ 189 MTSPR(SPR_SR, MFSPR(SPR_SR) | (SPR_SR_DCE & -(enable))) 190 191 // Invalidate the entire data cache 192 #define HAL_DCACHE_INVALIDATE_ALL() \ 193 CYG_MACRO_START \ 194 int cache_enabled, addr; \ 195 \ 196 /* Save current cache mode (disabled/enabled) */ \ 197 HAL_DCACHE_IS_ENABLED(cache_enabled); \ 198 \ 199 /* Disable cache, so that invalidation ignores cache tags */\ 200 HAL_DCACHE_DISABLE(); \ 201 addr = HAL_DCACHE_SIZE; \ 202 do { \ 203 MTSPR(SPR_DCBIR, addr); \ 204 addr -= HAL_DCACHE_LINE_SIZE; \ 205 } while (addr > 0); \ 206 \ 207 /* Re-enable cache if it was enabled on entry */ \ 208 HAL_SET_DCACHE_ENABLED(cache_enabled); \ 209 CYG_MACRO_END 210 211 // Synchronize the contents of the cache with memory. 212 // (Unnecessary on OR12K, since cache is write-through.) 213 #define HAL_DCACHE_SYNC() \ 214 CYG_MACRO_START \ 215 CYG_MACRO_END 216 217 // Query the state (enabled/disabled) of the data cache 218 #define HAL_DCACHE_IS_ENABLED(_state_) \ 219 CYG_MACRO_START \ 220 (_state_) = (1 - !(MFSPR(SPR_SR) & SPR_SR_DCE)); \ 221 CYG_MACRO_END 222 223 // Load the contents of the given address range into the data cache 224 // and then lock the cache so that it stays there. 225 226 // The OpenRISC architecture defines these operations, but no 227 // implementation supports them yet. 228 229 //#define HAL_DCACHE_LOCK(_base_, _size_) 230 231 // Undo a previous lock operation 232 //#define HAL_DCACHE_UNLOCK(_base_, _size_) 233 234 // Unlock entire cache 235 //#define HAL_DCACHE_UNLOCK_ALL() 236 237 238 //----------------------------------------------------------------------------- 239 // Data cache line control 240 241 // Write dirty cache lines to memory and invalidate the cache entries 242 // for the given address range. 243 // OR12k has write-through cache, so no flushing of writes to memory 244 // are necessary. 245 #define HAL_DCACHE_FLUSH( _base_ , _size_ ) \ 246 HAL_DCACHE_INVALIDATE(_base_, _size_) 247 248 // Invalidate cache lines in the given range without writing to memory. 249 #define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) \ 250 CYG_MACRO_START \ 251 U32 addr; \ 252 U32 end = (U32)_base_ + (U32)_size_; \ 253 for (addr = end; addr >= (U32)_base_; addr -= HAL_DCACHE_LINE_SIZE) { \ 254 MTSPR(SPR_DCBIR, addr); \ 255 } \ 256 CYG_MACRO_END 257 258 // Write dirty cache lines to memory for the given address range. 259 // OR12k has write-through cache, so this is a NOP 260 #define HAL_DCACHE_STORE( _base_ , _size_ ) 261 262 // Preread the given range into the cache with the intention of reading 263 // from it later. 264 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) 265 266 // Preread the given range into the cache with the intention of writing 267 // to it later. 268 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) 269 270 // Allocate and zero the cache lines associated with the given range. 271 //#define HAL_DCACHE_ZERO( _base_ , _size_ ) 272 273 //----------------------------------------------------------------------------- 274 // Global control of Instruction cache 275 276 // Enable the instruction cache 277 #define HAL_ICACHE_ENABLE() MTSPR(SPR_SR, MFSPR(SPR_SR) | SPR_SR_ICE) 278 279 // Disable the instruction cache 280 #define HAL_ICACHE_DISABLE() MTSPR(SPR_SR, MFSPR(SPR_SR) & ~SPR_SR_ICE) 281 282 // Enable or disable the data cache, depending on argument, which must 283 // be 0 or 1. 284 #define HAL_SET_ICACHE_ENABLED(enable) \ 285 MTSPR(SPR_SR, MFSPR(SPR_SR) | (SPR_SR_ICE & -(enable))) 286 287 // Invalidate the entire instruction cache 288 #define HAL_ICACHE_INVALIDATE_ALL() \ 289 CYG_MACRO_START \ 290 int cache_enabled, addr; \ 291 \ 292 /* Save current cache mode (disabled/enabled) */ \ 293 HAL_ICACHE_IS_ENABLED(cache_enabled); \ 294 \ 295 /* Disable cache, so that invalidation ignores cache tags */\ 296 HAL_ICACHE_DISABLE(); \ 297 addr = HAL_ICACHE_SIZE; \ 298 do { \ 299 MTSPR(SPR_ICBIR, addr); \ 300 addr -= HAL_ICACHE_LINE_SIZE; \ 301 } while (addr > 0); \ 302 \ 303 /* Re-enable cache if it was enabled on entry */ \ 304 HAL_SET_ICACHE_ENABLED(cache_enabled); \ 305 CYG_MACRO_END 306 307 // Synchronize the contents of the cache with memory. 308 #define HAL_ICACHE_SYNC() HAL_ICACHE_INVALIDATE_ALL() 309 310 // Query the state of the instruction cache 311 #define HAL_ICACHE_IS_ENABLED(_state_) \ 312 CYG_MACRO_START \ 313 (_state_) = (1 - !(MFSPR(SPR_SR) & SPR_SR_ICE)); \ 314 CYG_MACRO_END 315 316 #endif 317 // Load the contents of the given address range into the instruction cache 318 // and then lock the cache so that it stays there. 319 320 // The OpenRISC architecture defines these operations, but no 321 // implementation supports them yet. 322 323 //#define HAL_ICACHE_LOCK(_base_, _size_) 324 325 // Undo a previous lock operation 326 //#define HAL_ICACHE_UNLOCK(_base_, _size_) 327 328 // Unlock entire cache 329 //#define HAL_ICACHE_UNLOCK_ALL() 330 331 #endif /* __ASSEMBLER__ */ 332 #endif//NOS_MIPS 333 #endif // ifndef CYGONCE_HAL_CACHE_H 334 // End of hal_cache.h 335