1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. 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These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 #ifndef DRV_USB_HOST_CONFIG_H 79 #define DRV_USB_HOST_CONFIG_H 80 81 //#define ATV_SERISE_USE 82 //#define NEPTUNE_SERIAL_USE 83 //#define CERAMAL_SERISE_USE 84 //#define PLUTO_SERIAL_USE 85 //#define TITANIA2_SERIAL_USE 86 #define TITANIA3_SERIAL_USE 87 //#define EUCLID_SERIAL_USE 88 89 #if defined (MCU_AEON) 90 #define CPU_TYPE_AEON 91 #elif defined (MCU_MIPS_4KE) || defined(MCU_MIPS_34K) || defined(MCU_MIPS_74K) || defined(MCU_MIPS_1004K) 92 #define CPU_TYPE_MIPS 93 #elif defined (__arm__) || defined (__aarch64__) 94 #define CPU_TYPE_ARM 95 #else 96 #if defined (MIPS_CHAKRA) 97 #define CPU_TYPE_MIPS 98 #else 99 #define CPU_TYPE_AEON 100 #endif 101 #endif 102 103 104 #if defined(CPU_TYPE_AEON) 105 #define OS_BASE_ADDR 0xa0000000 106 #elif defined(CPU_TYPE_MIPS) 107 #if defined(TITANIA3_SERIAL_USE) || defined(EUCLID_SERIAL_USE) 108 #define OS_BASE_ADDR 0xbf000000 109 #else 110 #define OS_BASE_ADDR 0xbf800000 111 #endif 112 #elif defined(CPU_TYPE_ARM) 113 #define OS_BASE_ADDR 0xfd000000 114 #else 115 #No_CPU_type_for_USB 116 #endif 117 118 #ifdef PLUTO_SERIAL_USE 119 #define UHC_BASE (OS_BASE_ADDR+0x4800) 120 #define UHC2_BASE (OS_BASE_ADDR+0x1600) 121 #define UTMIBaseAddr (OS_BASE_ADDR+0x7500) 122 #define UTMIBaseAddr2 (OS_BASE_ADDR+0x7580) 123 #define USBCBase (OS_BASE_ADDR+0xe00) 124 #define USBCBase2 (OS_BASE_ADDR+0x1800) 125 #endif 126 127 #ifdef TITANIA2_SERIAL_USE 128 #define UHC_BASE (OS_BASE_ADDR+0x4800) 129 #define UHC2_BASE (OS_BASE_ADDR+0x1a00) 130 #define UTMIBaseAddr (OS_BASE_ADDR+0x7500) 131 #define UTMIBaseAddr2 (OS_BASE_ADDR+0x7400) 132 #define USBCBase (OS_BASE_ADDR+0xe00) 133 #define USBCBase2 (OS_BASE_ADDR+0xf00) 134 #endif 135 136 #ifdef EUCLID_SERIAL_USE 137 #define UHC_BASE (OS_BASE_ADDR+0x204800) 138 #define UHC2_BASE (OS_BASE_ADDR+0x201a00) 139 #define UTMIBaseAddr (OS_BASE_ADDR+0x207500) 140 #define UTMIBaseAddr2 (OS_BASE_ADDR+0x207400) 141 #define USBCBase (OS_BASE_ADDR+0x200e00) 142 #define USBCBase2 (OS_BASE_ADDR+0x200f00) 143 #endif 144 145 #ifdef TITANIA3_SERIAL_USE 146 #define UHC_BASE (OS_BASE_ADDR+0x204800) 147 #define UHC2_BASE (OS_BASE_ADDR+0x201a00) 148 #define UTMIBaseAddr (OS_BASE_ADDR+0x207500) 149 #define UTMIBaseAddr2 (OS_BASE_ADDR+0x207400) 150 #define USBCBase (OS_BASE_ADDR+0x200e00) 151 #define USBCBase2 (OS_BASE_ADDR+0x200f00) 152 153 #define UHC3_BASE (OS_BASE_ADDR+0x227200) 154 #define UTMIBaseAddr3 (OS_BASE_ADDR+0x207200) 155 #define USBCBase3 (OS_BASE_ADDR+0x227000) 156 157 #define UHC4_BASE (OS_BASE_ADDR+0x244c00) 158 #define UTMIBaseAddr4 (OS_BASE_ADDR+0x244100) 159 #define USBCBase4 (OS_BASE_ADDR+0x227100) 160 #endif 161 162 #ifdef TRITON_SERIAL_USE 163 #define UHC_BASE 0x2e00 164 #define UTMIBaseAddr 0x3100 165 #endif 166 167 #ifdef NEPTUNE_SERIAL_USE 168 #define UHC_BASE (OS_BASE_ADDR+0x4800) 169 #define UTMIBaseAddr (OS_BASE_ADDR+0x7500) 170 #endif 171 172 #if 0 173 #ifdef CERAMAL_SERISE_USE 174 #define UHC_BASE 0x2400 175 #define UTMIBaseAddr 0x1f00 176 #define OnePort_OTG_EHCI 177 #define Process_018_USE 178 #endif 179 #endif 180 181 #ifdef ATV_SERISE_USE 182 #define UHC_BASE (OS_BASE_ADDR+0x4800) 183 #define UTMIBaseAddr (OS_BASE_ADDR+0x7500) 184 #endif 185 186 187 //#define USB_PTP_ENABLE 188 //#define USB2_PTP_ENABLE 189 //#define USB3_PTP_ENABLE 190 //#define USB4_PTP_ENABLE 191 192 #define USB_HID_ENABLE 193 #define USB2_HID_ENABLE 194 //#define USB3_HID_ENABLE 195 //#define USB4_HID_ENABLE 196 197 198 #endif //#ifndef DRV_USB_HOST_CONFIG_H 199 200