1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
9 // or part of MStar Software is expressly prohibited, unless prior written
10 // permission has been granted by MStar.
11 //
12 // By accessing, browsing and/or using MStar Software, you acknowledge that you
13 // have read, understood, and agree, to be bound by below terms ("Terms") and to
14 // comply with all applicable laws and regulations:
15 //
16 // 1. MStar shall retain any and all right, ownership and interest to MStar
17 // Software and any modification/derivatives thereof.
18 // No right, ownership, or interest to MStar Software and any
19 // modification/derivatives thereof is transferred to you under Terms.
20 //
21 // 2. You understand that MStar Software might include, incorporate or be
22 // supplied together with third party`s software and the use of MStar
23 // Software may require additional licenses from third parties.
24 // Therefore, you hereby agree it is your sole responsibility to separately
25 // obtain any and all third party right and license necessary for your use of
26 // such third party`s software.
27 //
28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as
29 // MStar`s confidential information and you agree to keep MStar`s
30 // confidential information in strictest confidence and not disclose to any
31 // third party.
32 //
33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any
34 // kind. Any warranties are hereby expressly disclaimed by MStar, including
35 // without limitation, any warranties of merchantability, non-infringement of
36 // intellectual property rights, fitness for a particular purpose, error free
37 // and in conformity with any international standard. You agree to waive any
38 // claim against MStar for any loss, damage, cost or expense that you may
39 // incur related to your use of MStar Software.
40 // In no event shall MStar be liable for any direct, indirect, incidental or
41 // consequential damages, including without limitation, lost of profit or
42 // revenues, lost or damage of data, and unauthorized system use.
43 // You agree that this Section 4 shall still apply without being affected
44 // even if MStar Software has been modified by MStar in accordance with your
45 // request or instruction for your use, except otherwise agreed by both
46 // parties in writing.
47 //
48 // 5. If requested, MStar may from time to time provide technical supports or
49 // services in relation with MStar Software to you for your use of
50 // MStar Software in conjunction with your or your customer`s product
51 // ("Services").
52 // You understand and agree that, except otherwise agreed by both parties in
53 // writing, Services are provided on an "AS IS" basis and the warranty
54 // disclaimer set forth in Section 4 above shall apply.
55 //
56 // 6. Nothing contained herein shall be construed as by implication, estoppels
57 // or otherwise:
58 // (a) conferring any license or right to use MStar name, trademark, service
59 // mark, symbol or any other identification;
60 // (b) obligating MStar or any of its affiliates to furnish any person,
61 // including without limitation, you and your customers, any assistance
62 // of any kind whatsoever, or any information; or
63 // (c) conferring any license or right under any intellectual property right.
64 //
65 // 7. These terms shall be governed by and construed in accordance with the laws
66 // of Taiwan, R.O.C., excluding its conflict of law rules.
67 // Any and all dispute arising out hereof or related hereto shall be finally
68 // settled by arbitration referred to the Chinese Arbitration Association,
69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration
70 // Rules of the Association by three (3) arbitrators appointed in accordance
71 // with the said Rules.
72 // The place of arbitration shall be in Taipei, Taiwan and the language shall
73 // be English.
74 // The arbitration award shall be final and binding to both parties.
75 //
76 //******************************************************************************
77 //<MStar Software>
78
79
80 #ifndef _PORTS_H_
81 #define _PORTS_H_
82
83 #include <cyg/hal/hal_arch.h>
84 #include "MsCommon.h"
85 #include "../drvUsbcommon.h"
86
87 #undef CONFIG_FARADAY_USB
88 #define CONFIG_FARADAY_USB
89
90
91 #define USB_ASSERT( _bool_, _msg_ ) \
92 do { \
93 if ( ! ( _bool_ ) ) \
94 { while (1){} } \
95 } while (0);
96
97
98
99 /* Cache instruction opcodes */
100 #define HAL_CACHE_OP(which, op) (which | (op << 2))
101 #define HAL_DCACHE_HIT_INVALIDATE 0x5 // write back and invalidate
102 #define HAL_HIT_INVALIDATE 0x4 // address invalidate
103
104 #define HAL_WHICH_ICACHE 0x0
105 #define HAL_WHICH_DCACHE 0x1
106
107 ///#define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
108
109 #define HAL_MIPS32_DCACHE_START_ADDRESS(_addr_) \
110 (((U32)(_addr_)) & ~(HAL_DCACHE_LINE_SIZE-1))
111
112 #define HAL_MIPS32_DCACHE_END_ADDRESS(_addr_, _asize_) \
113 (((U32)((_addr_) + (_asize_) + (HAL_DCACHE_LINE_SIZE-1) )) & ~(HAL_DCACHE_LINE_SIZE-1))
114
115
116 #if 0
117
118 #define USBHAL_DCACHE_FLUSH( _base_ , _asize_ ) \
119 do { \
120 register U32 _addr_ = HAL_MIPS32_DCACHE_START_ADDRESS((U32)(_base_)); \
121 register U32 _eaddr_ = HAL_MIPS32_DCACHE_END_ADDRESS((U32)(_base_), _asize_); \
122 for( ; _addr_ < _eaddr_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
123 asm volatile (" cache %0, 0(%1)" \
124 : \
125 : "I" (HAL_CACHE_OP(HAL_WHICH_DCACHE, HAL_DCACHE_HIT_INVALIDATE)), \
126 "r"(_addr_)); \
127 } while (0)
128
129 #define USBHAL_DCACHE_INVALIDATE( _base_ , _asize_ ) \
130 do { \
131 register U32 _addr_ = HAL_MIPS32_DCACHE_START_ADDRESS( (U32)(_base_) ); \
132 register U32 _eaddr_ = HAL_MIPS32_DCACHE_END_ADDRESS( (U32)(_base_) , (_asize_) ); \
133 for( ; _addr_ < _eaddr_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
134 asm volatile (" cache %0, 0(%1)" \
135 : \
136 : "I" (HAL_CACHE_OP(HAL_WHICH_DCACHE, HAL_HIT_INVALIDATE)), \
137 "r"(_addr_)); \
138 } while (0)
139 #endif
140 #define wmb() HAL_REORDER_BARRIER()
141 #define rmb() HAL_REORDER_BARRIER()
142 #define barrier() HAL_REORDER_BARRIER()
143
144 // Debug Function
145 #define KERN_DEBUG "KERN_DEBUG "
146 #define KERN_ERR "KERN_ERR "
147 #define KERN_INFO "KERN_INFO "
148 #define KERN_WARNING "KERN_WARNING "
149
150 #define printk(x,...)
151
152 #define USB_sprintf sprintf //UTL_sprintf
153
154 #define CPUToLE32(_x_) (_x_)
155 #define LE16ToCPU(x) (x)
156 #define CPUToLE16(x) (x)
157 #define LE32ToCPU(x) (x)
158 // Delay routines
159 #define DelayTime(x) MsOS_DelayTask(x)
160
161 //#define wait_ms(x) DelayTime(x)
162 #define mdelay(x) DelayTime(x)
163 // Linux Device Driver related ports
164 extern void wait_ms(int x);
165
166 #define __init
167 #define __exit
168
169 // Prefetch for List (ARM v4 doesn't supports this feature
prefetch(void * x)170 static __inline__ void prefetch(void *x) {;} // Do nothing
171
172 /* ======================================== Function Declaration ======================================== */
173 extern void udelay(MS_U32 us);
174 extern void busyloop_delay(MS_U32 count);
175
176 /* ======================================== Data structures ======================================== */
177
178 // Used for ISR to stored the processor's context befor the processor entered interrupt code
179 struct pt_regs {
180 MS_U32 uregs[18];
181 };
182 #define ARM_cpsr uregs[16]
183 #define ARM_pc uregs[15]
184 #define ARM_lr uregs[14]
185 #define ARM_sp uregs[13]
186 #define ARM_ip uregs[12]
187 #define ARM_fp uregs[11]
188 #define ARM_r10 uregs[10]
189 #define ARM_r9 uregs[9]
190 #define ARM_r8 uregs[8]
191 #define ARM_r7 uregs[7]
192 #define ARM_r6 uregs[6]
193 #define ARM_r5 uregs[5]
194 #define ARM_r4 uregs[4]
195 #define ARM_r3 uregs[3]
196 #define ARM_r2 uregs[2]
197 #define ARM_r1 uregs[1]
198 #define ARM_r0 uregs[0]
199 #define ARM_ORIG_r0 uregs[17]
200
201 struct pci_dev{
202 void *dev;
203 };
204
205 #define CPE_FAKE_PCIDEV ((struct pci_dev *) 1111)
206 #define pcidev_is_CPE(dev) (dev == CPE_FAKE_PCIDEV)
207
208 // Timer data structure for Root hub
209
210 #define SLAB_KERNEL 0 //unmeaning
211 #define SLAB_ATOMIC 1 //unmeaning
212 #define GFP_KERNEL 2 //unmeaning
213 #define GFP_ATOMIC 3 //unmeaning
214 #define GFP_NOIO 4 //unmeaning
215 #define ASYNC_MAKE_QTD 5 //Asynchronous IO mode for making qtd list
216 #define ASYNC_SUBMIT_QTD 6 //Asynchronous IO mode for sumbitting qtd list
217
218 #define min_t(type,x,y) \
219 ( (type)x < (type)y ? (type) x : (type) y)
220 #define max_t(type,x,y) \
221 ( (type)x > (type)y ? (type) x : (type) y)
222
223 #ifdef min
224 #undef min
225 #define min(x,y) \
226 ( x < y ? x : y)
227 #endif
228 #ifdef max
229 #undef max
230 #define max(x,y) \
231 ( x > y ? x : y)
232 #endif
233
234 #define BUG()
235 extern void init_sys(void);
236 extern void exit_sys(void);
237 #endif
238
239
240