xref: /utopia/UTPA2-700.0.x/modules/usb/drv/usb_ecos/usbhost/drvUSBHwCtl.c (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)
1 //<MStar Software>
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77 //<MStar Software>
78 
79 #include "MsCommon.h"
80 #include "drvUSBHwCtl.h"
81 #include "drvEHCI.h"
82 #include "drvUSB.h"
83 
XBYTE_OR(MS_U32 Addr,MS_U8 offset,MS_U8 val)84 void XBYTE_OR(MS_U32 Addr, MS_U8 offset, MS_U8 val)
85 {
86     MS_U16 temp;
87 
88     if (offset & 1)
89     {
90         temp=*(MS_U16 volatile   *)(Addr+(offset-1)*2);
91         *(MS_U16 volatile   *)(Addr+(offset-1)*2)=(((MS_U16)val)<<8) | (temp );
92     }
93     else
94     {
95         temp=*(MS_U16 volatile   *)(Addr+offset*2);
96         *(MS_U16 volatile   *)(Addr+offset*2)=(temp )|val;
97      }
98 }
99 
XBYTE_AND(MS_U32 Addr,MS_U8 offset,MS_U8 val)100 void XBYTE_AND(MS_U32 Addr, MS_U8 offset,MS_U8 val)
101 {
102     MS_U16 temp;
103 
104     if (offset &1)
105     {
106         temp=*(MS_U16 volatile   *)(Addr+(offset-1)*2);
107         *(MS_U16 volatile   *)(Addr+(offset-1)*2)=((((MS_U16)val)<<8)|0xff) & (temp );
108     }
109     else
110     {
111         temp=*(MS_U16 volatile   *)(Addr+offset*2);
112         *(MS_U16 volatile   *)(Addr+offset*2)=(temp & (0xff00|val) );
113 
114      }
115 }
116 
XBYTE_SET(MS_U32 Addr,MS_U8 offset,MS_U8 val)117 void XBYTE_SET(MS_U32 Addr, MS_U8 offset,MS_U8 val)
118 {
119     MS_U16 temp;
120 
121     if (offset &1)
122     {
123         temp=*(MS_U16 volatile   *)(Addr+(offset-1)*2);
124         *(MS_U16 volatile   *)(Addr+(offset-1)*2)=((temp & 0x00ff) | (((MS_U16)val)<<8));
125     }
126     else
127     {
128         temp=*(MS_U16 volatile   *)(Addr+offset*2);
129         *(MS_U16 volatile   *)(Addr+offset*2)=((temp & 0xff00) |val );
130      }
131 }
132 
XBYTE_READ(MS_U32 Addr,MS_U8 offset)133 MS_U8 XBYTE_READ(MS_U32 Addr, MS_U8 offset)
134 {
135     MS_U16 temp;
136     MS_U8  uRetVal = 0;
137 
138     if (offset &1)
139     {
140         temp=*(MS_U16 volatile   *)(Addr+(offset-1)*2);
141         uRetVal = (MS_U8) (temp >> 8);
142     }
143     else
144     {
145         temp=*(MS_U16 volatile   *)(Addr+offset*2);
146         uRetVal = (MS_U8) temp;
147     }
148 
149     //diag_printf("XBYTE_READ: Addr: %X, offset: %X, uRetVal: %X\n", Addr, offset, uRetVal);
150     return uRetVal;
151 }
152 // ------------------------------------------------------------------------
153 #include "drvEHCI.h"
ResetMstarUsb(struct ehci_hcd * ehci)154 void ResetMstarUsb(struct ehci_hcd *ehci)
155 {
156     U32 reg_cmd, reg_inten;
157 
158     reg_inten = ehci_readl((U32)&ehci->regs->intr_enable);
159 
160     // 20110324: only reset UHC
161     // TODO: without UTMI TX/RX reset after K1
162     reg_cmd = ehci_readl((U32)&ehci->regs->command);
163     ehci_writel(reg_cmd | CMD_RESET, (U32)&ehci->regs->command);
164     //MsOS_DelayTask(2);
165     while(ehci_readb((U32)&ehci->regs->command) & CMD_RESET); // wait for reset done
166 
167     // restore UHC register
168     ehci_writel (reg_inten, (U32)&ehci->regs->intr_enable);
169     ehci_writel (reg_cmd, (U32)&ehci->regs->command);
170 }
UTMI_ORXBYTE_EX(MS_U8 offset,MS_U8 val,MS_U32 base)171 void UTMI_ORXBYTE_EX(MS_U8 offset,MS_U8 val, MS_U32 base)
172 {
173     XBYTE_OR(base, offset, val);
174 }
175 
UTMI_ANDXBYTE_EX(MS_U8 offset,MS_U8 val,MS_U32 base)176 void UTMI_ANDXBYTE_EX(MS_U8 offset,MS_U8 val, MS_U32 base)
177 {
178     XBYTE_AND(base, offset, val);
179 }
180 
UTMI_SETXBYTE_EX(MS_U8 offset,MS_U8 val,MS_U32 base)181 void UTMI_SETXBYTE_EX(MS_U8 offset,MS_U8 val, MS_U32 base)
182 {
183     XBYTE_SET(base, offset, val);
184 }
185 
UTMI_READXBYTE_EX(MS_U8 offset,MS_U32 base)186 MS_U8 UTMI_READXBYTE_EX(MS_U8 offset, MS_U32 base)
187 {
188     return XBYTE_READ(base, offset);
189 }
190 
191 #if USBC_IP_SUPPORT // USBC control
usbc_irq(MS_U32 regUTMI,MS_U32 regUSBC,struct s_UsbcInfo * pUsbc)192 void usbc_irq(MS_U32 regUTMI, MS_U32 regUSBC, struct s_UsbcInfo *pUsbc)
193 {
194     U16 status, vbus_t;
195 
196     pUsbc->intSts = status = usb_readw((void*)(regUSBC+0x6*2));
197     vbus_t = usb_readw((void*)(regUTMI+0x30*2)) & 0x20;  // bit[5]
198     pUsbc->eventType = vbus_t ? 1 : 0;
199     diag_printf("<usbc_irq> status change(%x) vbus(%x)\n", status, vbus_t);
200     status &= pUsbc->intEn;
201     usb_writew(status, (void*)(regUSBC+0x6*2)); // write 1 clear status
202     if (status)
203         pUsbc->eventFlag = 1;
204 }
205 
206 extern struct s_ChipUsbHostDef *pCurrentChip;
_usbc_on_intr(InterruptNum eIntNum)207 void _usbc_on_intr(InterruptNum eIntNum)
208 {
209     struct s_ChipUsbHostDef *pChip = pCurrentChip;
210     MS_U8 p;
211 
212     if (pChip == NULL)
213         return;
214     MsOS_DisableInterrupt(eIntNum);
215     for (p = 0; p < pChip->nRootHub; p++)
216     {
217         if (eIntNum == pChip->reg[p].usbcIRQ)
218             break;
219     }
220     usbc_irq(pChip->reg[p].baseUTMI, pChip->reg[p].baseUSBC, &pChip->usbc_ip[p]);
221     MsOS_EnableInterrupt(eIntNum);
222 
223 }
init_usbc_intr(MS_U8 p)224 void init_usbc_intr(MS_U8 p)
225 {
226     struct s_ChipUsbHostDef *pChip = pCurrentChip;
227     struct s_UsbcInfo *pUsbc = &pChip->usbc_ip[p];
228     MS_U8 intNum = pChip->reg[p].usbcIRQ;
229     MS_U32 regUSBC = pChip->reg[p].baseUSBC;
230 
231     pUsbc->portNum = p;
232     pUsbc->eventFlag = 0;
233     pUsbc->intEn = USBCINTR_VBusValidChange;
234     //pUsbc->intEn = USBCINTR_AValidChange; // for testing
235     pUsbc->int_pol = 1;
236 
237     diag_printf("<init_usbc_intr> port: %d, enable %x\n", p, pUsbc->intEn);
238     //usb_writeb((pUsbc->int_pol << 2) || usb_readb((void*)(regUSBC+0x2*2)), (void*)(regUSBC+0x2*2)); // set interrupt polarity
239     usb_writew(pUsbc->intEn, (void*)(regUSBC+0x6*2)); // clear interrupt status
240     usb_writew(pUsbc->intEn, (void*)(regUSBC+0x4*2)); // set interrupt enable
241 #ifndef  MS_NOSAPI
242     MsOS_AttachInterrupt(intNum, _usbc_on_intr);
243     MsOS_EnableInterrupt(intNum);
244 #endif
245 }
246 #endif
247