1 //<MStar Software>
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76 //******************************************************************************
77 //<MStar Software>
78
79 #ifndef __MS_EHCI_HCD_H
80 #define __MS_EHCI_HCD_H
81
82 #include <MsTypes.h>
83 #include "include/drvConfig.h"
84
85 #ifdef CONFIG_USB_DEBUG
86 #define DEBUG
87 #else
88 #undef DEBUG
89 #endif
90
91 // Flib Includes
92 #include "include/drvCompiler.h"
93 #include "include/drvPorts.h"
94 #include "include/drvBitops.h"
95 #include "include/drvPCIMEM.h"
96 #include "include/drvList.h"
97 #include "include/drvTimer.h"
98 #include "include/drvKernel.h"
99 // USB related implemented header files
100 #include "include/drvUSBHost.h"
101 #include "drvUsbd.h"
102
103 #define EHCI_IAA_MSEC (20) /* if USB_SW_TIMER_TICK < 10, it could be 10 ms */
104 #define EHCI_IAA_JIFFIES (HZ/100) /* arbitrary; ~10 msec */
105 #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog */
106 #define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */
107 #define EHCI_SHRINK_JIFFIES (HZ/200) /* async qh unlink delay */
108
109 struct usb_api_data
110 {
111 int done;
112 };
113
114 /* save EHCI IRQ status for polling */
115 struct ehci_irq_stats {
116 /* irq usage */
117 U32 u32Normal;
118 U32 u32Error;
119 U32 u32Reclaim;
120 U32 u32LostIAA;
121
122 /* termination of urbs from core */
123 U32 u32Complete;
124 U32 u32Unlink;
125 };
126
127 #define EHCI_MAX_ROOT_PORTS 1 /* see HCS_N_PORTS */
128
129 struct ehci_hcd { /* one per controller */
130 spinlock_t tHcdLock;
131
132 /* async schedule support */
133 struct ehci_qh *stAsync;
134 struct ehci_qh *stReclaim;
135 //int iReclaimReady : 1;
136 int iScanning : 1;
137
138 /* periodic schedule support , be careful about the size of memory cleanup*/
139 //#define DEFAULT_I_TDPS 1024 /* some HCs can do less */
140 #define DEFAULT_I_TDPS 256 /* some HCs can do less */
141 U32 u32PeriodicSize;
142 U32 *pPeriodic; /* hw periodic table */
143 dma_addr_t tPeriodicDma;
144 U32 u32IThresh; /* uframes HC might cache */
145 union ehci_qh_shadow *pshadow; /* mirror hw periodic table */
146 int iNextUframe; /* scan periodic, start here */
147 U32 u32PeriodicSched; /* periodic activity count */
148
149 /* �C�Ӯڶ��u�����@�� */
150 U32 u32ResetEnd [EHCI_MAX_ROOT_PORTS];
151
152 /* EHCI ��� registers */
153 struct usb_hcd hcd;
154 struct ehci_cap_regs *cap_regs;
155 struct ehci_op_regs *op_regs;
156 U32 hcs_params; /* cached register copy */
157
158 /* EHCI ��� memory pools */
159 struct ms_mem_pool *pQhPool; /* �@�� active urb ���@�� qh*/
160 struct ms_mem_pool *pQtdPool; /* �@�� qh ���@�өΧ�h��qtd*/
161 struct timer_list stWatchdog;
162 struct timer_list stiaa_Watchdog;
163 U32 u32Actions;
164 U32 u32Stamp;
165
166 /* store EHCI IRQ status */
167 #ifdef EHCI_STATS
168 struct ehci_irq_stats stats;
169 #endif
170 //unsigned char uDontSendIAA; // NUSED
171 U32 ehci_port_not_change_cnt;
172 U32 u32MoreCSC;
173 U32 u32random_frm; // to generate random start frame
174 };
175
176 #ifdef EHCI_STATS
177 #define INCREASE(x) do { (x)++; } while (0)
178 #else
179 #define INCREASE(x) do {} while (0)
180 #endif
181
182 /* unwrap an HCD pointer to get an EHCI_HCD pointer */
183
184 //#define hcd_to_ehci(hcd_ptr) container_of(hcd_ptr, struct ehci_hcd, hcd)
hcd_to_ehci(struct usb_hcd * hcd_ptr)185 static __inline__ struct ehci_hcd *hcd_to_ehci(struct usb_hcd *hcd_ptr)
186 {
187 const struct usb_hcd *__mptr = (hcd_ptr);
188 return (struct ehci_hcd *)( (char *)__mptr - (char *)offsetof(struct ehci_hcd,hcd) );
189 }
190
191 static __inline__ void
ms_iaa_watchdog_begin(struct ehci_hcd * ehci)192 ms_iaa_watchdog_begin(struct ehci_hcd *ehci)
193 {
194 //if (ms_timer_pending(&ehci->stiaa_Watchdog))
195 // diag_printf("iaa watchdog timer pending\n");
196 //mod_timer(&ehci->iaa_watchdog,
197 // jiffies + msecs_to_jiffies(EHCI_IAA_MSECS));
198 ms_update_timer (&ehci->stiaa_Watchdog, EHCI_IAA_MSEC, 0); // 20 ms
199 }
200
201 static __inline__ void
ms_iaa_watchdog_done(struct ehci_hcd * ehci)202 ms_iaa_watchdog_done(struct ehci_hcd *ehci)
203 {
204 ms_del_timer(&ehci->stiaa_Watchdog);
205 }
206
207 enum ehci_timer_event {
208 TIMER_IO_WATCHDOG,
209 //TIMER_IAA_WATCHDOG, // NUSED
210 TIMER_ASYNC_SHRINK,
211 TIMER_ASYNC_OFF
212 };
213
214 static __inline__ void
ms_timer_action_done(struct ehci_hcd * ehci,enum ehci_timer_event eAction)215 ms_timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_event eAction)
216 {
217 //U32 u32Flags; // NUSED
218
219 //save_and_disable_firqs(&u32Flags); // NUSED
220 ms_clear_bit (eAction, &ehci->u32Actions, U32);
221 //restore_firqs(&u32Flags); // NUSED
222 }
223
224 static __inline__ void
ms_timer_action(struct ehci_hcd * ehci,enum ehci_timer_event eAction)225 ms_timer_action (struct ehci_hcd *ehci, enum ehci_timer_event eAction)
226 {
227 // new patch
228 if (ms_timer_pending(&ehci->stWatchdog)
229 && (ms_test_bit(TIMER_ASYNC_SHRINK, &ehci->u32Actions) || ms_test_bit(TIMER_ASYNC_OFF, &ehci->u32Actions)))
230 return;
231
232 if (!ms_test_and_set_bit(eAction, &ehci->u32Actions))
233 {
234 U32 u32Time;
235
236 switch (eAction)
237 {
238 case TIMER_IO_WATCHDOG:
239 u32Time = EHCI_IO_JIFFIES;
240 break;
241 case TIMER_ASYNC_OFF:
242 u32Time = EHCI_ASYNC_JIFFIES;
243 break;
244 default:
245 u32Time = EHCI_SHRINK_JIFFIES;
246 break;
247 }
248 /* Open watch dog to deal with the interrupt lost issue */
249 //ehci->stWatchdog.base_jiffies = u32Time + jiffies; // NUSED
250 ms_update_timer (&ehci->stWatchdog, u32Time, 0);
251 }
252 #if 0
253 if( eAction == TIMER_IAA_WATCHDOG )
254 if (!ms_test_and_set_bit(eAction, &ehci->u32Actions))
255 {
256 U32 u32Time;
257
258 switch (eAction)
259 {
260 case TIMER_IAA_WATCHDOG:
261 u32Time = EHCI_IAA_JIFFIES;
262 break;
263 case TIMER_IO_WATCHDOG:
264 u32Time = EHCI_IO_JIFFIES;
265 break;
266 case TIMER_ASYNC_OFF:
267 u32Time = EHCI_ASYNC_JIFFIES;
268 break;
269 default:
270 u32Time = EHCI_SHRINK_JIFFIES;
271 break;
272 }
273 // all timings except IAA watchdog can be overridden.
274 // async queue SHRINK often precedes IAA. while it's ready
275 // to go OFF neither can matter, and afterwards the IO
276 // watchdog stops unless there's still periodic traffic.
277 if (eAction != TIMER_IAA_WATCHDOG
278 && (u32Time+jiffies) > (U32) ehci->stWatchdog.base_jiffies
279 && ms_timer_pending (&ehci->stWatchdog))
280 {
281 return;
282 }
283 #if 1 //Open watch dog to deal with the interrupt lost issue
284 ehci->stWatchdog.base_jiffies = u32Time + jiffies;
285 ms_update_timer (&ehci->stWatchdog, u32Time, 0);
286 #endif
287 }
288 #endif
289 }
290
291 /*-------------------------------------------------------------------------*/
292 struct ehci_cap_regs {
293 unsigned char caplength; /* Capability Register Length */
294 unsigned char reserved; /* [01h] */
295 U16 hciversion; /* HCIVERSION : [02h] */
296 U32 hcsparams; /* HCSPARAMS : [04h] */
297 U32 hcc_params; /* HCCPARAMS : [08h] */
298 unsigned char hcsp_portroute [8]; /* Companion Port Route Description : [0Ch] */
299 } __attribute__((packed));
300
301 /* HCSPARAMS : [04h] */
302 #define HCS_DBG_PORTS(p) (((p)>>20)&0xf)
303 #define HCS_P_INDICATOR(p)((p)&(1 << 16))
304 #define HCS_N_CC(p) (((p)>>12)&0xf) /* Number of Companion Controller */
305 #define HCS_N_PCC(p) (((p)>>8)&0xf) /* Number of Ports per Companion Controller */
306 #define HCS_PORT_ROUTE(p) ((p)&(1 << 7)) /* Port Routing Rules */
307 #define HCS_PPC(p) ((p)&(1 << 4)) /* Port Power Control */
308 #define HCS_N_PORTS(p) (((p)>>0)&0xf)
309
310 /* HCCPARAMS : [08h] */
311 #define HCC_ISO_CACHE(p) ((p)&(1 << 7)) /* Cache isochronous entire frame*/
312 #define HCC_ISO_THRES(p) (((p)>>4)&0x7) /* Isochronous Scheduling Threshold */
313 #define HCC_ASPC(p) ((p)&(1 << 2)) /* Asynchronous Schedule Park Capability. */
314 #define HCC_PFLF(p) ((p)&(1 << 1)) /* Programmable Frame List Flag*/
315 #define HCC_64BIT_ADDR_CAP(p) ((p)&(1)) /* 64-bit Addressing Capability */
316
317 /* Define for EHCI Spec Host Controller Operational Registers */
318
319 struct ehci_op_regs {
320
321 U32 usbcmd; /* USB Command : [00h] */
322 U32 usbsts; /* USB Status : [04h] */
323 U32 usbintr; /* USB Interrupt Enable : [08h] */
324 U32 frindex; /* USB Frame Index : [0Ch] */
325 U32 ctrldssegment; /* 4G Segment Selector: [10h] */
326 U32 periodiclistbase; /* Frame List Base Address : [14h] */
327 U32 asynclistaddr; /* Next Asynchronous List Address : [18h] */
328 U32 reserved2; /* reserve, [1Ch] */
329 U32 portsc[1]; /* port status/control [20h], Faraday change*/
330 U32 hcmisc;
331 U32 reserved[2];
332 /* Faraday specified register */
333 U32 bus_control; /* Bus monitor control : [30h] */
334
335 U32 reserved1 [3];
336 U32 test_register; /* Configured Flag Register : [40h], Faraday's test register, yuwen */
337 } __attribute__((packed));
338
339 /* USB Command : [00h] */
340 #define USBCMD_PARK (1<<11) /* Asynchronous Schedule Park Mode Count */
341 #define USBCMD_PARK_CNT(c) (((c)>>8)&3) /* Asynchronous Schedule Park Mode Count */
342 //#define USBCMD_LRESET (1<<7) /* Light Host Controller Reset => NUSED */
343 #define USBCMD_IAAD (1<<6) /* Interrupt on Async Advance Doorbell */
344 #define USBCMD_ASE (1<<5) /* Asynchronous Schedule Enable */
345 #define USBCMD_PSE (1<<4) /* Periodic Schedule Enable */
346 #define USBCMD_RESET (1<<1) /* Host Controller Reset */
347 #define USBCMD_RUN (1<<0) /* Run/Stop HCD */
348
349 /* USB Status : [04h] */
350 #define USBSTS_ASS (1<<15) /* Asynchronous Schedule Status */
351 #define USBSTS_PSS (1<<14) /* Periodic Schedule Status */
352 #define USBSTS_RECL (1<<13) /* Reclamation */
353 #define USBSTS_HALT (1<<12) /* HCHalted */
354 #define USBSTS_IAA (1<<5) /* Interrupt on Async Advance */
355 #define USBSTS_FATAL (1<<4) /* Host System Error */
356 #define USBSTS_FLR (1<<3) /* Frame List Rollover */
357 #define USBSTS_PCD (1<<2) /* Port Change Detect */
358 #define USBSTS_ERR (1<<1) /* USB Error Interrupt (USBERRINT) */
359 #define USBSTS_INT (1<<0) /* USB Interrupt (USBINT) */
360
361 /* port status/control [20h], Faraday change*/
362 #define PORTSC_WKOC_E (1<<22) /* Wake on Over-current Enable */
363 #define PORTSC_WKDISC_E (1<<21) /* Wake on Disconnect Enable */
364 #define PORTSC_WKCONN_E (1<<20) /* Wake on Connect Enable */
365 #define PORTSC_OWNER (1<<13)
366 #define PORTSC_POWER (1<<12)
367 #define PORTSC_USBFS(x) (((x)&(3<<10))==(1<<10)) /* Indicate USB full speed device */
368 #define PORTSC_RESET (1<<8) /* Start bus reset */
369 #define PORTSC_SUSPEND (1<<7)
370 #define PORTSC_RESUME (1<<6)
371 #define PORTSC_OCC (1<<5) /* Over-current Change */
372 #define PORTSC_OC (1<<4) /* Over-current Active */
373 #define PORTSC_PEC (1<<3) /* Port Enable/Disable Change */
374 #define PORTSC_PE (1<<2) /* Port Enabled/Disabled */
375 #define PORTSC_CSC (1<<1) /* Connect Status Change */
376 #define PORTSC_CONNECT (1<<0) /* Current Connect Status */
377 #define PORTSC_RWC_BITS (PORTSC_CSC | PORTSC_PEC | PORTSC_OCC)
378
379 /* Bus monitor control : [30h] */
380 #define HALF_SPEED (1<<2)
381 #define INT_POLAR (1<<3)
382 #define VBUS_OFF (1<<4)
383
384 /*-------------------------------------------------------------------------*/
385
386 struct ehci_qtd {
387 U32 hw_next_qtd;
388 U32 hw_alt_next_qtd;
389 U32 hw_token;
390 U32 hw_buffer [5];
391
392 /* the rest is HCD-private */
393 dma_addr_t qtd_dma_addr; /* qtd address */
394 struct list_head qtd_list; /* sw qtd list */
395 struct urb *urb; /* qtd's urb */
396 size_t length; /* length of buffer */
397 #if (_USB_128_ALIGMENT)
398 } __attribute__ ((aligned (128)));
399 #else
400 } __attribute__ ((aligned (32)));
401 #endif
402
403 /* qTD Token (DWord 2) */
404 #define QTD_TOGGLE ((U32)1 << 31)
405 #define QTD_BYTES(t) (((t)>>16) & 0x7fff)
406 #define QTD_IOC ((U32)1 << 15)
407 #define QTD_CERR(t) (((t)>>10) & 0x3)
408 #define MAX_CERR_CNT 3 /* qtd error retry count is 0~3, if 0 qtd will not retry */
409 #define QTD_PID(t) (((t)>>8) & 0x3)
410 #define PID_OUT (0 << 8)
411 #define PID_IN (1 << 8)
412 #define PID_SETUP (2 << 8)
413 #define QTD_STS_ACT ((U32)1 << 7)
414 #define QTD_STS_HALT ((U32)1 << 6)
415 #define QTD_STS_DATERR ((U32)1 << 5)
416 #define QTD_STS_BABBLE ((U32)1 << 4)
417 #define QTD_STS_XACTERR ((U32)1 << 3)
418 #define QTD_STS_MISSMF ((U32)1 << 2)
419 #define QTD_STS_SPLITXST ((U32)1 << 1)
420 #define QTD_STS_PERR ((U32)1 << 0)
421
422 /* mask NakCnt+T in qh->hw_alt_next */
423 #define QTD_MASK (~0x1f)
424
425 #define IS_SHORT_READ(token) (QTD_BYTES (token) != 0 && QTD_PID (token) == 1)
426
427 /*-------------------------------------------------------------------------*/
428
429 #define Q_NEXT_TYPE(dma) ((dma) & (3 << 1))
430 #define QH_TYPE (1 << 1)
431 #define QH_NEXT(dma) ((((U32)dma)&~0x01f)|QH_TYPE)
432
433 #define EHCI_LIST_END 1
434
435 union ehci_qh_shadow {
436 struct ehci_qh *qh;
437 U32 *hw_next;
438 void *ptr; // page pointer
439 };
440
441 /*-------------------------------------------------------------------------*/
442 #define QH_MAX_XACTRTT_RETRY 32
443 struct ehci_qh {
444 U32 hw_next_qh;
445 U32 hw_ep_state1;
446 U32 hw_ep_state2;
447 U32 hw_current_qtd;
448 U32 hw_next_qtd;
449 U32 hw_alt_next_qtd;
450 U32 hw_token;
451 U32 hw_bufptr_lo [5];
452
453 /* the rest is software HCD-private */
454 dma_addr_t qh_dma_addr; /* address of qh */
455 union ehci_qh_shadow qh_next; /* ptr to qh; or periodic */
456 struct list_head qtd_list; /* sw qtd list */
457 struct ehci_qtd *pDummyQtd;
458 struct ehci_qh *pReclaimQh;
459 atomic_t tRefCnt;
460 U32 u32Stamp;
461 unsigned char qh_status;
462 U8 xacterrs;
463 unsigned char u8Usecs;
464 unsigned char u8Gap_uf;
465 unsigned char c_usecs;
466 U16 u16Period;
467 U16 u16Start;
468 #define NO_FRAME ((U16)~0)
469 struct usb_device *dev; /* for TT */
470 #if (_USB_128_ALIGMENT)
471 } __attribute__ ((aligned (128)));
472 #else
473 } __attribute__ ((aligned (32)));
474 #endif
475
476 /* QH DWORD 2 */
477 #define QH_SMASK 0x000000ff
478 #define QH_CMASK 0x0000ff00
479
480 /* QH DWORD 1 */
481 #define QH_C_BIT 0x08000000 /* bit 27 */
482 #define QH_H_BIT 0x00008000 /* bit 15 */
483 #define QH_DTC_BIT 0x00004000 /* bit 14 */
484
485 /* qh status */
486 #define QH_STS_LINKED 1
487 #define QH_STS_UNLINK 2
488 #define QH_STS_IDLE 3
489 #define QH_STS_UNLINK_WAIT 4
490 #define QH_STS_COMPLETING 5
491
492 /*-------------------------------------------------------------------------*/
493 #define writel(data, reg_adr) ( (*( (volatile MS_U32 *) (reg_adr) ) ) = ((MS_U32)data) )
494 #define readl(reg_adr) ( *( (volatile MS_U32 *) (reg_adr) ) )
495 #define writew(data, reg_adr) ( (*( (volatile MS_U16 *) (reg_adr) ) ) = ((MS_U16)data) )
496 #define readw(reg_adr) ( *( (volatile MS_U16 *) (reg_adr) ) )
497 #define writeb(data, reg_adr) ( (*( (volatile MS_U8 *) (reg_adr) ) ) = ((MS_U8)data) )
498 #define readb(reg_adr) ( *( (volatile MS_U8 *) (reg_adr) ) )
499
hcd_reg_readl(unsigned int regs)500 static inline unsigned int hcd_reg_readl( unsigned int regs)
501 {
502 regs = ( (regs & 0xffffff00) + ((regs & 0x000000ff)*2) );
503 return (readl((void*)(unsigned int)regs) & 0x0000ffff)|((readl((void*)((unsigned int)regs+4))<<16) & 0xffff0000);
504 }
505
hcd_reg_writel(const unsigned int val,unsigned int regs)506 static inline void hcd_reg_writel(const unsigned int val, unsigned int regs)
507 {
508 regs = ((regs & 0xffffff00) + ((regs & 0x000000ff)*2)) ;
509 writel(val & 0x0000ffff,(void*)regs) ;
510 writel(((val>>16) & 0x0000ffff),(void*)((unsigned int)regs+4)) ;
511 }
512
hcd_reg_readw(unsigned int regs)513 static inline unsigned short hcd_reg_readw(unsigned int regs)
514 {
515 //USB_ASSERT((regs & 0x1) == 0, "TRAP: hcd_reg_readw address not alignment !!\n");
516 regs = ( (regs & 0xffffff00) + ((regs & 0x000000ff)*2) );
517 return (readw((void*)(unsigned int)regs));
518 }
519
hcd_reg_readb(unsigned int regs)520 static inline unsigned char hcd_reg_readb(unsigned int regs)
521 {
522 if (regs & 0x1)
523 regs = ( (regs & 0xffffff00) + ((regs & 0x000000ff)*2)-1 );
524 else
525 regs = ( (regs & 0xffffff00) + ((regs & 0x000000ff)*2) );
526 return (readb((void*)(unsigned int)regs));
527 }
528
529 /*-------------------------------------------------------------------------*/
530 #ifdef EHCI_TD_DEBUG
531 extern void dbg_timeout_async(struct usb_hcd *);
532 #endif
533 #endif
534