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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: regURDMA.h 98 // Description: FAST UART DMA Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef __FAST_UART_DMA_H__ 103 #define __FAST_UART_DMA_H__ 104 105 //#if FAST_UART_DMA_ENABLE 106 107 //#include "fast_uart_dma_param.h" //halURDMA.h 108 #include "halURDMA.h" 109 110 111 #define Struct_Register __attribute__((packed)) 112 113 114 /* Warning: Little Endian */ 115 typedef struct dma_interface 116 { 117 union 118 { 119 volatile MS_U16 reg00; /* 00h */ 120 struct 121 { 122 volatile MS_U16 sw_rst : 1; /* BIT0 */ 123 volatile MS_U16 urdma_mode : 1; /* BIT1 */ 124 volatile MS_U16 tx_urdma_en : 1; /* BIT2 */ 125 volatile MS_U16 rx_urdma_en : 1; /* BIT3 */ 126 volatile MS_U16 tx_endian : 1; /* BIT4 */ 127 volatile MS_U16 rx_endian : 1; /* BIT5 */ 128 volatile MS_U16 tx_sw_rst : 1; /* BIT6 */ 129 volatile MS_U16 rx_sw_rst : 1; /* BIT7 */ 130 volatile MS_U16 reserve00 : 3; /* BIT8 ~ BIT10 */ 131 volatile MS_U16 rx_op_mode : 1; /* BIT11 */ 132 volatile MS_U16 tx_busy : 1; /* BIT12 */ 133 volatile MS_U16 rx_busy : 1; /* BIT13 */ 134 volatile MS_U16 reserve01 : 2; /* BIT14 ~ BIT15 */ 135 } Struct_Register; 136 } Struct_Register; 137 #if TWO_BYTE_SPACE 138 MS_U16 space00; 139 #endif 140 union 141 { 142 volatile MS_U16 reg01; /* 02h */ 143 struct 144 { 145 volatile MS_U16 intr_threshold : 12; /* BIT0 ~ BIT11 */ 146 volatile MS_U16 reserve02 : 4; /* BIT12 ~ BIT15 */ 147 } Struct_Register; 148 } Struct_Register; 149 #if TWO_BYTE_SPACE 150 MS_U16 space01; 151 #endif 152 union 153 { 154 volatile MS_U16 reg02; /* 04h */ 155 struct 156 { 157 volatile MS_U16 tx_buf_base_h : 11; /* BIT0 ~ BIT7 */ 158 volatile MS_U16 reserve03 : 5; /* BIT8 ~ BIT15 */ 159 } Struct_Register; 160 } Struct_Register; 161 #if TWO_BYTE_SPACE 162 MS_U16 space02; 163 #endif 164 union 165 { 166 volatile MS_U16 reg03; /* 06h */ 167 struct 168 { 169 volatile MS_U16 tx_buf_base_l : 16; /* BIT0 ~ BIT15 */ 170 } Struct_Register; 171 } Struct_Register; 172 #if TWO_BYTE_SPACE 173 MS_U16 space03; 174 #endif 175 union 176 { 177 volatile MS_U16 reg04; /* 08h */ 178 struct 179 { 180 volatile MS_U16 tx_buf_size : 13; /* BIT0 ~ BIT12 */ 181 volatile MS_U16 reserve04 : 3; /* BIT13 ~ BIT15 */ 182 } Struct_Register; 183 } Struct_Register; 184 #if TWO_BYTE_SPACE 185 MS_U16 space04; 186 #endif 187 union 188 { 189 volatile MS_U16 reg05; /* 0Ah */ 190 struct 191 { 192 volatile MS_U16 tx_buf_rptr : 16; /* BIT0 ~ BIT15 */ 193 } Struct_Register; 194 } Struct_Register; 195 #if TWO_BYTE_SPACE 196 MS_U16 space05; 197 #endif 198 union 199 { 200 volatile MS_U16 reg06; /* 0Ch */ 201 struct 202 { 203 volatile MS_VIRT tx_buf_wptr : 16; /* BIT0 ~ BIT15 */ 204 } Struct_Register; 205 } Struct_Register; 206 #if TWO_BYTE_SPACE 207 MS_U16 space06; 208 #endif 209 union 210 { 211 volatile MS_U16 reg07; /* 0Eh */ 212 struct 213 { 214 volatile MS_U16 tx_timeout : 4; /* BIT0 ~ BIT3 */ 215 volatile MS_U16 reserve05 : 12; /* BIT4 ~ BIT15 */ 216 } Struct_Register; 217 } Struct_Register; 218 #if TWO_BYTE_SPACE 219 MS_U16 space07; 220 #endif 221 union 222 { 223 volatile MS_U16 reg08; /* 10h */ 224 struct 225 { 226 volatile MS_U16 rx_buf_base_h : 11; /* BIT0 ~ BIT7 */ 227 volatile MS_U16 reserve06 : 5; /* BIT8 ~ BIT15 */ 228 } Struct_Register; 229 } Struct_Register; 230 #if TWO_BYTE_SPACE 231 MS_U16 space08; 232 #endif 233 union 234 { 235 volatile MS_U16 reg09; /* 12h */ 236 struct 237 { 238 volatile MS_U16 rx_buf_base_l : 16; /* BIT0 ~ BIT15 */ 239 } Struct_Register; 240 } Struct_Register; 241 #if TWO_BYTE_SPACE 242 MS_U16 space09; 243 #endif 244 union 245 { 246 volatile MS_U16 reg0a; /* 14h */ 247 struct 248 { 249 volatile MS_U16 rx_buf_size : 13; /* BIT0 ~ BIT12 */ 250 volatile MS_U16 reserve07 : 3; /* BIT13 ~ BIT15 */ 251 } Struct_Register; 252 } Struct_Register; 253 #if TWO_BYTE_SPACE 254 MS_U16 space0a; 255 #endif 256 union 257 { 258 volatile MS_U16 reg0b; /* 16h */ 259 struct 260 { 261 volatile MS_U16 rx_buf_wptr : 16; /* BIT0 ~ BIT15 */ 262 } Struct_Register; 263 } Struct_Register; 264 #if TWO_BYTE_SPACE 265 MS_U16 space0b; 266 #endif 267 union 268 { 269 volatile MS_U16 reg0c; /* 18h */ 270 struct 271 { 272 volatile MS_U16 rx_timeout : 4; /* BIT0 ~ BIT3 */ 273 volatile MS_U16 reserve08 : 12; /* BIT4 ~ BIT15 */ 274 } Struct_Register; 275 } Struct_Register; 276 #if TWO_BYTE_SPACE 277 MS_U16 space0c; 278 #endif 279 union 280 { 281 volatile MS_U16 reg0d; /* 1Ah */ 282 struct 283 { 284 volatile MS_U16 rx_intr_clr : 1; /* BIT0 */ 285 volatile MS_U16 rx_intr1_en : 1; /* BIT1 */ 286 volatile MS_U16 rx_intr2_en : 1; /* BIT2 */ 287 volatile MS_U16 reserve09 : 1; /* BIT3 */ 288 volatile MS_U16 rx_intr1 : 1; /* BIT4 */ 289 volatile MS_U16 rx_intr2 : 1; /* BIT5 */ 290 volatile MS_U16 reserve0a : 1; /* BIT6 */ 291 volatile MS_U16 rx_mcu_intr : 1; /* BIT7 */ 292 volatile MS_U16 tx_intr_clr : 1; /* BIT8 */ 293 volatile MS_U16 tx_intr_en : 1; /* BIT9 */ 294 volatile MS_U16 reserve0b : 5; /* BIT10 ~ BIT14 */ 295 volatile MS_U16 tx_mcu_intr : 1; /* BIT15 */ 296 } Struct_Register; 297 } Struct_Register; 298 } Struct_Register dma_interface_t; 299 300 //#endif /* #if FAST_UART_DMA_ENABLE */ 301 302 #endif /* __FAST_UART_DMA_H__ */ 303