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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _HAL_SYS_H_ 96 #define _HAL_SYS_H_ 97 98 99 //------------------------------------------------------------------------------------------------- 100 // Macro and Define 101 //------------------------------------------------------------------------------------------------- 102 #define UNUSED( var ) (void)((var) = (var)) 103 104 #define CHIPREV_U01 0x00UL 105 #define CHIPREV_U02 0x01UL 106 107 #define EFUSE_ADDRESS_MASK 0x007FUL 108 #define EFUSE_OFFSET_HDCP_FSM0 0x0010UL 109 #define EFUSE_OFFSET_HDCP_FSM1 0x0028UL 110 #define EFUSE_OFFSET_HASH_FSM0 0x0002UL // bank 2 111 112 //efuse FSM0 113 #define REG_EFUSE_FSM0_TRIG 0x2000UL 114 #define REG_EFUSE_FSM0_CTRL 0x2002UL 115 #define REG_EFUSE_FSM0_RDATA_15_0 0x2060UL 116 #define REG_EFUSE_FSM0_RDATA_31_16 0x2062UL 117 #define REG_EFUSE_FSM0_RDATA_47_32 0x2064UL 118 #define REG_EFUSE_FSM0_RDATA_63_48 0x2066UL 119 120 //efuse FSM1 121 #define REG_EFUSE_FSM1_TRIG 0x204CUL 122 #define REG_EFUSE_FSM1_CTRL 0x204EUL 123 #define REG_EFUSE_FSM1_RDATA_15_0 0x2080UL 124 #define REG_EFUSE_FSM1_RDATA_31_16 0x2082UL 125 #define REG_EFUSE_FSM1_RDATA_47_32 0x2084UL 126 #define REG_EFUSE_FSM1_RDATA_63_48 0x2086UL 127 128 //efuse 32*32 129 #define REG_RESERVED4_15_0 0x2050UL //0X28 130 #define REG_RESERVED4_31_16 0x2052UL //0X29 131 132 #define REG_EFUSE_128_RD_15_0 0x2058UL //0X2c 133 #define REG_EFUSE_128_RD_31_16 0x205AUL //0X2d 134 135 #define REG_EFUSE_32_RD_15_0 0x205CUL //0X2e 136 #define REG_EFUSE_32_RD_31_16 0x205EUL //0X2f 137 138 #define FLAG_EFUSE_DATA_BUSY 0x2000UL //0x28[13], 1: Busy, 0:Idle 139 //0x29[13], 1: Busy, 0:Idle 140 141 #define MAX_TIMEOUT_COUNT 100UL 142 143 //------------------------------------------------------------------------------------------------- 144 // Type and Structure 145 //------------------------------------------------------------------------------------------------- 146 typedef struct 147 { 148 MS_U32 u32ChipTopBase; 149 MS_U32 u32PmTopBase; // REG_PM_BASE 150 } hal_sys_base_t; 151 152 typedef enum 153 { 154 E_HALSYS_SOURCE_DTV = 0x00, 155 E_HALSYS_SOURCE_HDMI, 156 E_HALSYS_SOURCE_MM, 157 E_HALSYS_SOURCE_GOOGLE_CAST, 158 E_HALSYS_SOURCE_MAX, 159 } E_HALSYS_SOURCE_TYPE; 160 161 typedef enum 162 { 163 E_HALSYS_INPUT_FHD24_25_30 = 0x00, 164 E_HALSYS_INPUT_FHD48, 165 E_HALSYS_INPUT_FHD50_60, 166 E_HALSYS_INPUT_4K2K24_25_30, 167 E_HALSYS_INPUT_4K2K48, 168 E_HALSYS_INPUT_4K2K50_60, 169 E_HALSYS_INPUT_ALWAYS_ON, 170 E_HALSYS_INPUT_ALWAYS_OFF, 171 E_HALSYS_INPUT_FHD_UNKNOWN, 172 E_HALSYS_INPUT_4K2K120, 173 E_HALSYS_INPUT_4K2K_UNKNOWN, 174 E_HALSYS_INPUT_MAX, 175 } E_HALSYS_INPUT_TIMING; 176 177 // 178 // Input Source Mapping, 179 // Ref: mapi_types.h 180 // 181 typedef enum 182 { 183 E_HALSYS_INPUT_SOURCE_HDMI = 23, ///<HDMI 1 23 184 E_HALSYS_INPUT_SOURCE_HDMI2= 24, ///<HDMI 2 24 185 E_HALSYS_INPUT_SOURCE_HDMI3= 25, ///<HDMI 3 25 186 E_HALSYS_INPUT_SOURCE_HDMI4= 26, ///<HDMI 4 26 187 E_HALSYS_INPUT_SOURCE_DTV = 28, ///<DTV 28 188 E_HALSYS_INPUT_SOURCE_STORAGE = 34, ///<Storage 34 189 E_HALSYS_INPUT_SOURCE_DTV2 = 37, ///<DTV2 37 190 E_HALSYS_INPUT_SOURCE_DTV3 = 39, ///<DTV3 39 191 E_HALSYS_INPUT_SOURCE_GOOGLE_CAST = 44, ///<Google Cast 44 192 } E_HALSYS_INPUT_SOURCE_TYPE; 193 194 //------------------------------------------------------------------------------------------------- 195 // Function and Variable 196 //------------------------------------------------------------------------------------------------- 197 void SYS_Init(MS_PHY phy64baseaddr); 198 MS_U8 SYS_GetChipRev(void); 199 MS_U16 SYS_GetChipID(void); 200 const SYS_Info* SYS_GetInfo(void); 201 void SYS_ResetCPU(void); 202 MS_U8 SYS_VIF_ReadByteByVDMbox(MS_U32 u32Reg); 203 void SYS_VIF_WriteByteByVDMbox(MS_U32 u32Reg, MS_U8 u8Val); 204 void SYS_VIF_WriteByteMaskByVDMbox(MS_U32 u32Reg, MS_U8 u8Val, MS_U8 u8Mask); 205 void SYS_VIF_WriteRegBitByVDMbox(MS_U32 u32Reg, MS_U8 bEnable, MS_U8 u8Mask); 206 MS_U16 SYS_VIF_Read2ByteByVDMbox(MS_U32 u32Reg); 207 void HAL_SYS_RFAGC_Tristate(MS_BOOL bEnable); 208 void HAL_SYS_IFAGC_Tristate(MS_BOOL bEnable); 209 void HAL_SYS_SetAGCPadMux(SYS_AGC_PAD_SET eAgcPadMux); 210 MS_BOOL HAL_SYS_SetPadMux(SYS_PAD_MUX_SET ePadMuxType,SYS_PAD_SEL ePadSel); 211 MS_BOOL HAL_SYS_SetPCMCardDetectMode(SYS_PCM_CD_MODE ePCMCDMode); 212 MS_BOOL HAL_SYS_PadMuxTableSuspend(void); 213 MS_BOOL HAL_SYS_PadMuxTableResume(void); 214 MS_BOOL HAL_SYS_DisableDebugPort(void); 215 MS_BOOL HAL_SYS_EnableDebugPort(void); 216 MS_BOOL HAL_SYS_SetTSOutClockPhase(MS_U16 u16Val); 217 MS_BOOL HAL_SYS_SetTSClockPhase(SYS_PAD_MUX_SET ePadMuxType,MS_U16 u16Val); 218 219 void HAL_SYS_SetEfuseIOMapBase(MS_VIRT u32Base); 220 MS_U16 HAL_SYS_EfuseRead2Byte(MS_U32 u32RegAddr); 221 MS_U16 HAL_SYS_EfuseWrite2Byte(MS_U32 u32RegAddr, MS_U16 u16Val); 222 void HAL_SYS_SetOtpIOMapBase(MS_VIRT u32Base); 223 MS_U32 HAL_SYS_ReadRSAKey(MS_U16 u16ReadAddr); 224 MS_BOOL HAL_SYS_Query(E_SYS_QUERY id); 225 MS_U32 HAL_SYS_QueryDolbyHashInfo(E_SYS_DOLBY_HASH_INFO index); 226 E_SYS_CHIP_TYPE HAL_SYS_GetChipType(void); 227 void HAL_SYS_SetChipType(E_SYS_CHIP_TYPE Type); 228 MS_U16 HAL_SYS_ReadBrickTerminatorStatus(void); 229 void HAL_SYS_WriteBrickTerminatorStatus(MS_U16 u16Status); 230 void HAL_SYS_GetEfuseDid(MS_U16 *u16efuse_did); 231 MS_BOOL HAL_SYS_ReadEfuseHDCPKey(MS_U16 u16ReadAddr, MS_U32 *u32HDCPKey); 232 MS_U32 HAL_SYS_GetMemcConfg(MS_U32 eSource, MS_U32 eTiming, MS_BOOL *retEnMemc); 233 MS_U32 HAL_SYS_GetXcByPartConfg (MS_U32 eSource, MS_U32 eInputTiming, MS_U32 eOutputTiming, MS_BOOL *retEn); 234 void HAL_SYS_EnableWkEventWOL(void); 235 void HAL_SYS_DisableWkEventWOL(void); 236 void HAL_SYS_ResetStatusWOL(void); 237 MS_BOOL HAL_SYS_GetStatusWOL(void); 238 239 #endif // _HAL_SYS_H_ 240 241