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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: regAESDMA.h 98 // Description: AESDMA Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _AESDMA_REG_MCU_H_ 103 #define _AESDMA_REG_MCU_H_ 104 105 106 //-------------------------------------------------------------------------------------------------- 107 // Abbreviation 108 //-------------------------------------------------------------------------------------------------- 109 // Addr Address 110 // Buf Buffer 111 // Clr Clear 112 // CmdQ Command queue 113 // Cnt Count 114 // Ctrl Control 115 // Flt Filter 116 // Hw Hardware 117 // Int Interrupt 118 // Len Length 119 // Ovfw Overflow 120 // Pkt Packet 121 // Rec Record 122 // Recv Receive 123 // Rmn Remain 124 // Reg Register 125 // Req Request 126 // Rst Reset 127 // Scmb Scramble 128 // Sec Section 129 // Stat Status 130 // Sw Software 131 // Ts Transport Stream 132 133 134 //-------------------------------------------------------------------------------------------------- 135 // Global Definition 136 //-------------------------------------------------------------------------------------------------- 137 138 139 //-------------------------------------------------------------------------------------------------- 140 // Compliation Option 141 //-------------------------------------------------------------------------------------------------- 142 143 144 //------------------------------------------------------------------------------------------------- 145 // Harware Capability 146 //------------------------------------------------------------------------------------------------- 147 148 149 //------------------------------------------------------------------------------------------------- 150 // Type and Structure 151 //------------------------------------------------------------------------------------------------- 152 #define REG_AESDMACTRL_BASE 0x47940UL //(0x23C00/2 + 0x50) * 4 153 #define REG_SHARNGCTRL_BASE 0x47800UL //(0x23C00/2 + 0x0) * 4 154 #define REG_DMASECURE_CTRL_BASE 0x27A00UL //(0x13D00/2 + 0x00) * 4 155 #define REG_DMASECURE_BASE 0x27B40UL //(0x13D00/2 + 0x50) * 4 156 #define REG_AESDMACLK_BASE 0x1460UL //(0x0A00/2 + 0x18) * 4 157 //#define REG_AESDMAMBX_BASE 0x17F8 //(0x0B00/2 + 0x7F) * 4 158 #define REG_AESDMAMBX_BASE 0x7B84UL //(0x3D00/2 + 0x61) * 4 159 #define REG_PARSERCTRL_BASE 0x45800UL //(0x22C00/2 + 0x00) * 4 160 #define REG_CIPHERCTRL_BASE 0x45840UL //(0x22C00/2 + 0x10) * 4 161 #define REG_AESDMAEXT_BASE 0x45980UL //(0x22C00/2 + 0x60) * 4 162 #define REG_TZPC_NONPM_BASE 0x47200UL //(0x23900/2 + 0x00) * 4 163 #define REG_MIPS_OCC_CLK_BASE 0x21840UL //(0x10C00/2 + 0x10) * 4 164 165 #define RSA_E_BASE_ADDR (0x00UL) 166 #define RSA_N_BASE_ADDR (0x40UL) 167 #define RSA_A_BASE_ADDR (0x80UL) 168 #define RSA_Z_BASE_ADDR (0xC0UL) 169 #define REG_HDCP22_BASE 0xE74C0UL //(0x73A00/2 + 0x30) * 4 170 #define REG_HDCP22_SEK 0xE2538UL //(0x71200/2 + 0x4E) * 4 171 172 typedef struct _REG32 173 { 174 volatile MS_U16 L; 175 volatile MS_U16 empty_L; 176 volatile MS_U16 H; 177 volatile MS_U16 empty_H; 178 } REG32; 179 180 typedef struct _REG_CipherKey 181 { 182 REG32 Key_L; 183 REG32 Key_H; 184 } REG_CipherKey; 185 186 typedef struct _REG_InitVector 187 { 188 REG32 IV_L; 189 REG32 IV_H; 190 } REG_InitVector; 191 192 typedef struct _REG_AESDMACtrl 193 { 194 REG32 Dma_Ctrl; //0x50 195 #define AESDMA_CTRL_FILEIN_START 0x00000100UL 196 #define AESDMA_CTRL_FILEOUT_START 0x00000001UL 197 #define AESDMA_CTRL_SW_RST 0x00000080UL 198 #define AESDMA_CTRL_BURST_LENGTH 0x00001000UL 199 200 #define AESDMA_ENG_PS_RELEASE 0x00010000UL 201 #define AESDMA_ENG_PS_IN_EN 0x00100000UL 202 #define AESDMA_ENG_PS_OUT_EN 0x00200000UL 203 #define AESDMA_ENG_AES_EN 0x01000000UL 204 #define AESDMA_ENG_DES_EN 0x00040000UL 205 #define AESDMA_ENG_TDES_EN 0x00080000UL 206 #define AESDMA_ENG_DESCRYPT 0x02000000UL // 0:encrypt, 1:decrypt 207 #define AESDMA_ENG_CTR_MODE 0x10000000UL 208 #define AESDMA_ENG_CBC_MODE 0x20000000UL 209 #define AESDMA_ENG_CTS_CBC_MODE 0x40000000UL 210 #define AESDMA_ENG_CTS_ECB_MODE 0x00000002UL 211 #define AESDMA_ECO_FIX_LAST_BYTE 0x80000000UL // when (output address + length)/8=1 the last byte maybe no output 212 213 REG32 Dma_Filein_Addr; //0x52 214 REG32 Dma_Filein_Num; //0x54 215 REG32 Dma_Fileout_SAddr; //0x56 216 REG32 Dma_Fileout_EAddr; //0x58 217 REG32 Dma_PS_Pattern; //0x5a 218 REG32 Dma_PS_Pattern_Mask; //0x5c 219 REG32 Dma_Ctrl2; //0x5e 220 #define AESDMA_DMA_USE_TDES_EN 0x00000100UL // DES/TDES path switch 221 #define AESDMA_CTRL_BANK_R_H 0x00002000UL 222 #define AESDMA_CTRL_BANK_W_H 0x00004000UL 223 #define AESDMA_CTRL_BANK_R 0x00000010UL 224 #define AESDMA_CTRL_BANK_W 0x00000020UL 225 #define AESDMA_INT_EN 0x00000080UL 226 #define AESDMA_USE_SECRET_KEY 0x00001000UL 227 #define AESDMA_WADR_ERR_CLR 0x00000001UL 228 229 REG_CipherKey Dma_CipherKey_L; //0x60 230 REG_CipherKey Dma_CipherKey_H; //0x64 231 REG_InitVector Dma_InitVector_L; //0x68 232 REG_InitVector Dma_InitVector_H; //0x6C 233 REG32 Dma_Matched_Btyecnt; //0x70 234 REG32 Dma_Matched_Pat; //0x72 235 REG32 Dma_Err_Wadr; //0x74 236 REG32 Dma_Eng3_Ctrl; //0x76 237 #define AESDMA_ENG_SPEEDUP 0x043E0000UL 238 REG32 _xbf808fd8[3]; //0x78~0x7c 239 REG32 Dma_PVR_Status; //0x7e 240 #define AESDMA_IS_FINISHED 0x00010000UL 241 /* 242 #define AESDMA_PS_DONE 0x00000001 243 #define AESDMA_PS_STOP 0x00000002 244 #define AESDMA_DMA_DONE 0x00010000 245 #define AESDMA_DMA_PAUSE 0x00020000 246 #define AESDMA_STATES_GROUP (AESDMA_PS_DONE | \ 247 AESDMA_PS_STOP | \ 248 AESDMA_DMA_DONE | \ 249 AESDMA_DMA_PAUSE ) 250 */ 251 }REG_AESDMACtrl; 252 253 #define DmaCtrlSet (AESDMA_ENG_AES_EN | \ 254 AESDMA_ENG_DES_EN | \ 255 AESDMA_ENG_TDES_EN | \ 256 AESDMA_ENG_DESCRYPT | \ 257 AESDMA_ENG_CTR_MODE | \ 258 AESDMA_ENG_CBC_MODE | \ 259 AESDMA_ENG_CTS_CBC_MODE | \ 260 AESDMA_ENG_CTS_ECB_MODE) 261 262 typedef struct _REG_SHARNGCtrl 263 { 264 REG32 Rng_Ctrl; //0x00 265 #define SHARNG_CTRL_RNG_SW_RST 0x00000080UL 266 #define MOBF_IN_MIU_READ_EN 0x00010000UL 267 #define MOBF_IN_MIU_WRITE_EN 0x00020000UL 268 #define AES_FILE_IN_MIU_NS 0x00100000UL 269 #define AES_FILE_OUT_MIU_NS 0x00200000UL 270 #define MOBF_ONEWAY_EN 0x01000000UL 271 272 #define SECRET_KEY_IN_NORMAL_BANK 0x08000000UL 273 274 275 REG32 Rng_Out; //0x02 276 REG32 MOBF_KeyR; //0x04 277 REG32 MOBF_KeyW; //0x06 278 REG32 Sha_Ctrl; //0x08 279 #define SHARNG_CTRL_SHA_FIRE_ONCE 0x00000001UL 280 #define SHARNG_CTRL_SHA_CLR 0x00000040UL 281 #define SHARNG_CTRL_SHA_RST 0x00000080UL 282 #define SHARNG_CTRL_SHA_INT 0x00000100UL 283 #define SHARNG_CTRL_SHA_SEL_SHA256 0x00000200UL 284 #define SHARNG_CTRL_SHA_MSG_INVERSE 0x00040000UL 285 #define SHARNG_CTRL_SHA_MSG_BLOCK_NUM 0x00010000UL /* Always be 1 */ 286 #define SHARNG_CTRL_SPEED_MODE_N 0x00000010UL 287 #define SHARNG_CTRL_REMOVE_SCATTER_GATHER 0x00000800UL 288 289 REG32 Sha_Start; //0x0a 290 REG32 Sha_Length; //0x0c 291 REG32 Sha_Status; //0x0e 292 #define SHARNG_CTRL_SHA_BUSY 0x00020000UL 293 #define SHARNG_CTRL_SHA_READY 0x00010000UL 294 295 REG32 Sha_Out[8]; //0x10~0x1E 296 REG32 Rsa_Ind32_Start; //0x20 297 #define RSA_INDIRECT_START 0x00000001UL 298 #define RSA_IND32_CTRL_DIRECTION_WRITE 0x00020000UL 299 #define RSA_IND32_CTRL_ADDR_AUTO_INC 0x00040000UL 300 #define RSA_IND32_CTRL_ACCESS_AUTO_START 0x00080000UL 301 REG32 Rsa_Ind32_Addr; //0x22 302 #define RSA_ADDRESS_MASK 0x0000FFFFUL 303 #define RSA_WDATA_MASK_L 0xFFFF0000UL 304 REG32 Rsa_Ind32_WData; //0x24 305 #define RSA_WDATA_MASK_H 0x0000FFFFUL 306 #define RSA_RDATA_MASK_L 0xFFFF0000UL 307 REG32 Rsa_Ind32_RData; //0x26 308 #define RSA_RDATA_MASK_H 0x0000FFFFUL 309 #define RSA_EXP_START 0x00010000UL 310 #define RSA_INT_CLR 0x00020000UL 311 REG32 Rsa_Ctrl; //0x28 312 #define RSA_CTRL_RSA_RST 0x00000001UL 313 #define RSA_CTRL_SEL_HW_KEY 0x00000002UL 314 #define RSA_CTRL_SEL_PUBLIC_KEY 0x00000004UL 315 #define RSA_CTRL_KEY_LENGTH_MASK 0x00003F00UL 316 #define RSA_STATUS_RSA_BUSY 0x00010000UL 317 #define RSA_STATUS_MASK 0x00FF0000UL 318 }REG_SHARNGCtrl; 319 320 typedef struct _REG_DMASECURECtrl 321 { 322 REG32 Secure_file_st; //0x50 323 //#define AESDMA_SECURE_FILEIN_START 0x00000001 324 REG32 reserved52; //0x52 325 REG32 reserved54; //0x54 326 REG32 reserved56; //0x56 327 REG32 reserved58; //0x58 328 REG32 reserved5a; //0x5a 329 REG32 reserved5c; //0x5c 330 REG32 reserved5e; //0x5e 331 REG_CipherKey Secure_CipherKey_L; //0x60 332 REG_CipherKey Secure_CipherKey_H; //0x64 333 REG_InitVector Secure_InitVector_L; //0x68 334 REG_InitVector Secure_InitVector_H; //0x6C 335 REG32 reserved70; //0x70 336 REG32 reserved72; //0x72 337 REG32 reserved74; //0x74 338 REG32 reserved76; //0x76 339 REG32 Secure_dma3_ctrl; //0x78 340 #define AESDMA_SECURE_PROTECT_S 0x00010000UL 341 #define AESDMA_USE_SECRET_KEY0 0x00200000UL 342 #define AESDMA_USE_SECRET_KEY1 0x00400000UL 343 REG32 reserved7a; //0x7a 344 REG32 reserved7c; //0x7c 345 REG32 Secure_dma3_status; //0x7e 346 //#define AESDMA_DONE_S 0x00010000 347 }REG_DMASECURECtrl; 348 349 typedef struct _REG_CKG_AESDMA 350 { 351 REG32 Reg_Gate_Clk_AESDMA; //0x18 352 #define AESDMA_CLK_OFF_EN 0x00010000UL //0x19[0] 353 #define AESDMA_CLK_INV 0x00020000UL //0x19[1] 354 #define AESDMA_CLK_172M 0x00000000UL //0x19[3:2] 355 #define AESDMA_CLK_144M 0x00040000UL //0x19[3:2] 356 #define AESDMA_CLK_108M 0x00080000UL //0x19[3:2] 357 #define AESDMA_CLK_XTAL 0x000C0000UL //0x19[3:2] 358 359 }REG_AESDMAClk; 360 361 typedef struct _REG_MBX_AESDMA 362 { 363 REG32 Reg_Et_Rpd; //0x61 364 #define AESDMA_SEM_USED 0x00000100UL 365 #define AESDMA_CLK_USED 0x00000200UL 366 #define TSP_CLK_USED 0x00000400UL 367 }REG_AESDMAMbx; 368 369 370 typedef struct _REG_PARSERCtrl 371 { 372 REG32 Parser_Ctrl; //0x00 373 #define HDCP20_MODE 0x00000001UL 374 #define PKT192_MODE 0x00000002UL 375 #define AUTO_MODE 0x00000004UL 376 #define TRIGGER_MODE 0x00000008UL 377 #define INIT_TRUST 0x00000010UL 378 #define CLEAR_MODE 0x00000020UL 379 #define REMOVE_SCRMB 0x00000040UL 380 #define INSERT_SCRMB 0x00000080UL 381 #define SCRMB_PATTERN10 0x00000400UL 382 #define SCRMB_PATTERN11 0x00000600UL 383 #define SCRMB_INITVALUE 0x00000600UL 384 #define HW_PARSER_MODE 0x00000100UL 385 #define TS_SCRMB_MASK 0x00000800UL 386 #define TS_MODE 0x00008000UL 387 #define PARSER_PID0_MASK 0x1FFF0000UL 388 REG32 Parser_Pid1; //0x02 389 #define PARSER_PID1_MASK 0x00001FFFUL 390 #define BYPASS_PID 0x00080000UL 391 #define SCRMB_PATTERN10_ADD 0x00200000UL 392 #define SCRMB_PATTERN11_ADD 0x00300000UL 393 #define SCRMB_INITVALUE_ADD 0x00300000UL 394 #define SCRMB_ENABLE_TWO_KEY 0x00400000UL 395 #define ENABLE_LG_PATCH 0x01000000UL 396 REG32 Parser_Status; //0x04 397 398 }REG_PARSERCtrl; 399 400 typedef struct _REG_CIPHERCtrl 401 { 402 REG32 Cipher_Ctrl; //0x00 403 #define CC_CTRL_BY_ACPU 0x00000080UL 404 REG32 Cipher_len; //0x02 405 REG32 Parser_Status; //0x04 406 407 }REG_CIPHERCtrl; 408 409 #define ParserCtrlSet (HDCP20_MODE | \ 410 PKT192_MODE | \ 411 AUTO_MODE | \ 412 TRIGGER_MODE | \ 413 INIT_TRUST | \ 414 CLEAR_MODE | \ 415 HW_PARSER_MODE | \ 416 TS_MODE ) 417 418 typedef struct _REG_AESDMACtrlEx 419 { 420 REG_CipherKey Dma_CipherKey_L; //0x60 421 REG_CipherKey Dma_CipherKey_H; //0x64 422 REG_InitVector Dma_InitVector_L; //0x68 423 REG_InitVector Dma_InitVector_H; //0x6C 424 }REG_AESDMACtrlEx; 425 426 typedef struct _REG_HDCP22Data 427 { 428 REG32 Hdcp22_ContentKey[4]; 429 REG32 Hdcp22_Riv[2]; 430 }REG_HDCP22Data; 431 432 typedef struct _REG_HDCP22SEKCtrl 433 { 434 REG32 SEK; //0x9C 435 #define HDCP_SEK_BIT0 0x00000001 436 }REG_HDCP22SEKCtrl; 437 438 typedef struct _REG_GENERAL_STRUCT 439 { 440 REG32 Reg0001; //0x00 441 REG32 Reg0203; //0x02 442 REG32 Reg0405; //0x04 443 REG32 Reg0607; //0x06 444 REG32 Reg0809; //0x08 445 }REG_GENERAL_STRUCT; 446 447 //REG_TZPC_NONPM_BASE 448 typedef REG_GENERAL_STRUCT REG_TZPCCtrl; //BANK: 0x1239 449 #define REG_TZPC2NONPM_RNG_SOURCE_EN 0x000F0000UL //0x03[3:0] 450 451 //REG_DMASECURE_CTRL_BASE 452 typedef REG_GENERAL_STRUCT REG_SECUREBASECtrl; //BANK: 0x113D 453 #define REG_RNG_EN 0x00000080UL //0x00[7] 454 455 //REG_MIPS_OCC_CLK_BASE 456 typedef REG_GENERAL_STRUCT REG_MIPSOCCCLKCtrl; //BANK: 0x1103 457 458 #endif // #ifndef _AESDMA_REG_MCU_H_ 459