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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: regAESDMA.h 98 // Description: AESDMA Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _AESDMA_REG_MCU_H_ 103 #define _AESDMA_REG_MCU_H_ 104 105 106 //-------------------------------------------------------------------------------------------------- 107 // Abbreviation 108 //-------------------------------------------------------------------------------------------------- 109 // Addr Address 110 // Buf Buffer 111 // Clr Clear 112 // CmdQ Command queue 113 // Cnt Count 114 // Ctrl Control 115 // Flt Filter 116 // Hw Hardware 117 // Int Interrupt 118 // Len Length 119 // Ovfw Overflow 120 // Pkt Packet 121 // Rec Record 122 // Recv Receive 123 // Rmn Remain 124 // Reg Register 125 // Req Request 126 // Rst Reset 127 // Scmb Scramble 128 // Sec Section 129 // Stat Status 130 // Sw Software 131 // Ts Transport Stream 132 133 134 //-------------------------------------------------------------------------------------------------- 135 // Global Definition 136 //-------------------------------------------------------------------------------------------------- 137 138 139 //-------------------------------------------------------------------------------------------------- 140 // Compliation Option 141 //-------------------------------------------------------------------------------------------------- 142 143 144 //------------------------------------------------------------------------------------------------- 145 // Harware Capability 146 //------------------------------------------------------------------------------------------------- 147 148 149 //------------------------------------------------------------------------------------------------- 150 // Type and Structure 151 //------------------------------------------------------------------------------------------------- 152 #define REG_AESDMACTRL_BASE 0x47940UL //(0x23C00/2 + 0x50) * 4 153 #define REG_SHARNGCTRL_BASE 0x47800UL //(0x23C00/2 + 0x0) * 4 154 #define AESDMS_SECURED_BANK_EN 0 155 156 #define REG_DMASECURE_CTRL_BASE 0x27A00UL //(0x13D00/2 + 0x00) * 4 157 #define REG_DMASECURE_BASE 0x27B40UL //(0x13D00/2 + 0x50) * 4 158 #define REG_AESDMACLK_BASE 0x1460UL //(0x0A00/2 + 0x18) * 4 159 //#define REG_AESDMAMBX_BASE 0x17F8 //(0x0B00/2 + 0x7F) * 4 160 #define REG_AESDMAMBX_BASE 0x7B84UL //(0x3D00/2 + 0x61) * 4 161 #define REG_PARSERCTRL_BASE 0x45800UL //(0x22C00/2 + 0x00) * 4 162 #define REG_CIPHERCTRL_BASE 0x45840UL //(0x22C00/2 + 0x10) * 4 163 #define REG_AESDMAEXT_BASE 0x45980UL //(0x22C00/2 + 0x60) * 4 164 #define REG_TZPC_NONPM_BASE 0x47200UL //(0x23900/2 + 0x00) * 4 165 #define REG_AES_DSCMB6_BASE 0xE7A00UL //(0x73D00/2 + 0x00) * 4 166 #define REG_AES_DSCMB7_BASE 0xE7B00UL //(0x73D00/2 + 0x40) * 4 167 168 169 //Used for Random Number Gen, Manhattan only 170 #define REG_ANA_MISC_BASE 0x21840UL //(0x10C00/2 + 0x10) * 4 171 172 #define RSA_E_BASE_ADDR (0x00UL) 173 #define RSA_N_BASE_ADDR (0x40UL) 174 #define RSA_A_BASE_ADDR (0x80UL) 175 #define RSA_Z_BASE_ADDR (0xC0UL) 176 #define REG_HDCP22_BASE 0xE74C0UL //(0x73A00/2 + 0x30) * 4 177 #define REG_HDCP22_SEK 0xE2538UL //(0x71200/2 + 0x4E) * 4 178 #define REG_HDCP14_BASE 0xE2438UL //(0x71200 + 0x1C) * 2 179 180 typedef struct _REG32 181 { 182 volatile MS_U16 L; 183 volatile MS_U16 empty_L; 184 volatile MS_U16 H; 185 volatile MS_U16 empty_H; 186 } REG32; 187 188 typedef struct _REG_CipherKey 189 { 190 REG32 Key_L; 191 REG32 Key_H; 192 } REG_CipherKey; 193 194 typedef struct _REG_InitVector 195 { 196 REG32 IV_L; 197 REG32 IV_H; 198 } REG_InitVector; 199 200 typedef struct _REG_AESDMACtrl 201 { 202 REG32 Dma_Ctrl; //0x50 203 #define AESDMA_CTRL_FILEIN_START 0x00000100UL 204 #define AESDMA_CTRL_FILEOUT_START 0x00000001UL 205 #define AESDMA_CTRL_SW_RST 0x00000080UL 206 #define AESDMA_CTRL_BURST_LENGTH 0x00001000UL 207 208 #define AESDMA_ENG_PS_RELEASE 0x00010000UL 209 #define AESDMA_ENG_PS_IN_EN 0x00100000UL 210 #define AESDMA_ENG_PS_OUT_EN 0x00200000UL 211 #define AESDMA_ENG_AES_EN 0x01000000UL 212 #define AESDMA_ENG_DES_EN 0x00040000UL 213 #define AESDMA_ENG_TDES_EN 0x00080000UL 214 #define AESDMA_ENG_DESCRYPT 0x02000000UL // 0:encrypt, 1:decrypt 215 #define AESDMA_ENG_CTR_MODE 0x10000000UL 216 #define AESDMA_ENG_CBC_MODE 0x20000000UL 217 #define AESDMA_ENG_CTS_CBC_MODE 0x40000000UL 218 #define AESDMA_ENG_CTS_ECB_MODE 0x00000002UL 219 #define AESDMA_ECO_FIX_LAST_BYTE 0x80000000UL // when (output address + length)/8=1 the last byte maybe no output 220 221 REG32 Dma_Filein_Addr; //0x52 222 REG32 Dma_Filein_Num; //0x54 223 REG32 Dma_Fileout_SAddr; //0x56 224 REG32 Dma_Fileout_EAddr; //0x58 225 REG32 Dma_PS_Pattern; //0x5a 226 REG32 Dma_PS_Pattern_Mask; //0x5c 227 #define AESDMA_CTR_IV_LSB64 0x01000000UL //0X5d[8]: reg_ctr_iv_lsb64 228 REG32 Dma_Ctrl2; //0x5e 229 #define AESDMA_DMA_USE_TDES_EN 0x00000100UL // DES/TDES path switch 230 #define AESDMA_CTRL_BANK_R_H 0x00002000UL 231 #define AESDMA_CTRL_BANK_W_H 0x00004000UL 232 #define AESDMA_CTRL_BANK_R 0x00000010UL 233 #define AESDMA_CTRL_BANK_W 0x00000020UL 234 #define AESDMA_INT_EN 0x00000080UL 235 #define AESDMA_USE_SECRET_KEY 0x00001000UL //0x5E[12], Enable Efuse Key1 236 #define AESDMA_USE_SECRET_KEY2 0x00001200UL //0x5E[9]+0x5E[12], Enable Efuse Key2 237 #define AESDMA_WADR_ERR_CLR 0x00000001UL 238 239 REG_CipherKey Dma_CipherKey_L; //0x60 240 REG_CipherKey Dma_CipherKey_H; //0x64 241 REG_InitVector Dma_InitVector_L; //0x68 242 REG_InitVector Dma_InitVector_H; //0x6C 243 REG32 Dma_Matched_Btyecnt; //0x70 244 REG32 Dma_Matched_Pat; //0x72 245 REG32 Dma_Err_Wadr; //0x74 246 REG32 Dma_Eng3_Ctrl; //0x76 247 #define AESDMA_ENG_SPEEDUP 0x03BF0000UL 248 REG32 _xbf808fd8[3]; //0x78~0x7c 249 REG32 Dma_PVR_Status; //0x7e 250 #define AESDMA_IS_FINISHED 0x00010000UL 251 /* 252 #define AESDMA_PS_DONE 0x00000001 253 #define AESDMA_PS_STOP 0x00000002 254 #define AESDMA_DMA_DONE 0x00010000 255 #define AESDMA_DMA_PAUSE 0x00020000 256 #define AESDMA_STATES_GROUP (AESDMA_PS_DONE | \ 257 AESDMA_PS_STOP | \ 258 AESDMA_DMA_DONE | \ 259 AESDMA_DMA_PAUSE ) 260 */ 261 }REG_AESDMACtrl; 262 263 #define DmaCtrlSet (AESDMA_ENG_AES_EN | \ 264 AESDMA_ENG_DES_EN | \ 265 AESDMA_ENG_TDES_EN | \ 266 AESDMA_ENG_DESCRYPT | \ 267 AESDMA_ENG_CTR_MODE | \ 268 AESDMA_ENG_CBC_MODE | \ 269 AESDMA_ENG_CTS_CBC_MODE | \ 270 AESDMA_ENG_CTS_ECB_MODE) 271 272 typedef struct _REG_SHARNGCtrl 273 { 274 REG32 Rng_Ctrl; //0x00 275 #define SHARNG_CTRL_RNG_SW_RST 0x00000080UL 276 #define MOBF_IN_MIU_READ_EN 0x00010000UL 277 #define MOBF_IN_MIU_WRITE_EN 0x00020000UL 278 #define AES_FILE_IN_MIU_NS 0x00100000UL 279 #define AES_FILE_OUT_MIU_NS 0x00200000UL 280 #define MOBF_ONEWAY_EN 0x01000000UL 281 282 #define SECRET_KEY_IN_NORMAL_BANK 0x08000000UL 283 284 285 REG32 Rng_Out; //0x02 286 REG32 MOBF_KeyR; //0x04 287 REG32 MOBF_KeyW; //0x06 288 REG32 Sha_Ctrl; //0x08 289 #define SHARNG_CTRL_SHA_FIRE_ONCE 0x00000001UL 290 #define SHARNG_CTRL_SHA_CLR 0x00000040UL 291 #define SHARNG_CTRL_SHA_RST 0x00000080UL 292 #define SHARNG_CTRL_SHA_INT 0x00000100UL 293 #define SHARNG_CTRL_SHA_SEL_SHA256 0x00000200UL 294 #define SHARNG_CTRL_SHA_MSG_INVERSE 0x00040000UL 295 #define SHARNG_CTRL_SHA_MSG_BLOCK_NUM 0x00010000UL /* Always be 1 */ 296 #define SHARNG_CTRL_SPEED_MODE_N 0x00000010UL 297 #define SHARNG_CTRL_REMOVE_SCATTER_GATHER 0x00000800UL 298 299 REG32 Sha_Start; //0x0a 300 REG32 Sha_Length; //0x0c 301 REG32 Sha_Status; //0x0e 302 #define SHARNG_CTRL_SHA_BUSY 0x00020000UL 303 #define SHARNG_CTRL_SHA_READY 0x00010000UL 304 305 REG32 Sha_Out[8]; //0x10~0x1E 306 REG32 Rsa_Ind32_Start; //0x20 307 #define RSA_INDIRECT_START 0x00000001UL 308 #define RSA_IND32_CTRL_DIRECTION_WRITE 0x00020000UL 309 #define RSA_IND32_CTRL_ADDR_AUTO_INC 0x00040000UL 310 #define RSA_IND32_CTRL_ACCESS_AUTO_START 0x00080000UL 311 REG32 Rsa_Ind32_Addr; //0x22 312 #define RSA_ADDRESS_MASK 0x0000FFFFUL 313 #define RSA_WDATA_MASK_L 0xFFFF0000UL 314 REG32 Rsa_Ind32_WData; //0x24 315 #define RSA_WDATA_MASK_H 0x0000FFFFUL 316 #define RSA_RDATA_MASK_L 0xFFFF0000UL 317 REG32 Rsa_Ind32_RData; //0x26 318 #define RSA_RDATA_MASK_H 0x0000FFFFUL 319 #define RSA_EXP_START 0x00010000UL 320 #define RSA_INT_CLR 0x00020000UL 321 REG32 Rsa_Ctrl; //0x28 322 #define RSA_CTRL_RSA_RST 0x00000001UL 323 #define RSA_CTRL_SEL_HW_KEY 0x00000002UL 324 #define RSA_CTRL_SEL_PUBLIC_KEY 0x00000004UL 325 #define RSA_CTRL_KEY_LENGTH_MASK 0x00003F00UL 326 #define RSA_STATUS_RSA_BUSY 0x00010000UL 327 #define RSA_STATUS_MASK 0x00FF0000UL 328 }REG_SHARNGCtrl; 329 330 typedef struct _REG_DMASECURECtrl 331 { 332 REG32 Secure_file_st; //0x50 333 //#define AESDMA_SECURE_FILEIN_START 0x00000001 334 REG32 reserved52; //0x52 335 REG32 reserved54; //0x54 336 REG32 reserved56; //0x56 337 REG32 reserved58; //0x58 338 REG32 reserved5a; //0x5a 339 REG32 reserved5c; //0x5c 340 REG32 reserved5e; //0x5e 341 REG_CipherKey Secure_CipherKey_L; //0x60 342 REG_CipherKey Secure_CipherKey_H; //0x64 343 REG_InitVector Secure_InitVector_L; //0x68 344 REG_InitVector Secure_InitVector_H; //0x6C 345 REG32 reserved70; //0x70 346 REG32 reserved72; //0x72 347 REG32 reserved74; //0x74 348 REG32 reserved76; //0x76 349 REG32 Secure_dma3_ctrl; //0x78 350 #define AESDMA_SECURE_PROTECT_S 0x00010000UL 351 #define AESDMA_SECURE_PROTECT_SHA_S 0x00020000UL 352 #define AESDMA_SECURE_PROTECT_RSA_S 0x00040000UL 353 #define AESDMA_USE_SECRET_KEY0 0x00200000UL 354 #define AESDMA_USE_SECRET_KEY1 0x00400000UL 355 REG32 reserved7a; //0x7a 356 REG32 reserved7c; //0x7c 357 REG32 Secure_dma3_status; //0x7e 358 //#define AESDMA_DONE_S 0x00010000 359 }REG_DMASECURECtrl; 360 361 typedef struct _REG_CKG_AESDMA 362 { 363 REG32 Reg_Gate_Clk_AESDMA; //0x18 364 #define AESDMA_CLK_OFF_EN 0x00010000UL //0x19[0] 365 #define AESDMA_CLK_INV 0x00020000UL //0x19[1] 366 #define AESDMA_CLK_172M 0x00000000UL //0x19[3:2] 367 #define AESDMA_CLK_144M 0x00040000UL //0x19[3:2] 368 #define AESDMA_CLK_108M 0x00080000UL //0x19[3:2] 369 #define AESDMA_CLK_XTAL 0x000C0000UL //0x19[3:2] 370 371 }REG_AESDMAClk; 372 373 typedef struct _REG_MBX_AESDMA 374 { 375 REG32 Reg_Et_Rpd; //0x61 376 #define AESDMA_SEM_USED 0x00000100UL 377 #define AESDMA_CLK_USED 0x00000200UL 378 #define TSP_CLK_USED 0x00000400UL 379 }REG_AESDMAMbx; 380 381 382 typedef struct _REG_PARSERCtrl 383 { 384 REG32 Parser_Ctrl; //0x00 385 #define HDCP20_MODE 0x00000001UL 386 #define PKT192_MODE 0x00000002UL 387 #define AUTO_MODE 0x00000004UL 388 #define TRIGGER_MODE 0x00000008UL 389 #define INIT_TRUST 0x00000010UL 390 #define CLEAR_MODE 0x00000020UL 391 #define REMOVE_SCRMB 0x00000040UL 392 #define INSERT_SCRMB 0x00000080UL 393 #define SCRMB_PATTERN10 0x00000400UL 394 #define SCRMB_PATTERN11 0x00000600UL 395 #define SCRMB_INITVALUE 0x00000600UL 396 #define HW_PARSER_MODE 0x00000100UL 397 #define TS_SCRMB_MASK 0x00000800UL 398 #define TS_MODE 0x00008000UL 399 #define PARSER_PID0_MASK 0x1FFF0000UL 400 REG32 Parser_Pid1; //0x02 401 #define PARSER_PID1_MASK 0x00001FFFUL 402 #define BYPASS_PID 0x00080000UL 403 #define SCRMB_PATTERN10_ADD 0x00200000UL 404 #define SCRMB_PATTERN11_ADD 0x00300000UL 405 #define SCRMB_INITVALUE_ADD 0x00300000UL 406 #define SCRMB_ENABLE_TWO_KEY 0x00400000UL 407 #define ENABLE_LG_PATCH 0x01000000UL 408 REG32 Parser_Status; //0x04 409 410 }REG_PARSERCtrl; 411 412 typedef struct _REG_CIPHERCtrl 413 { 414 REG32 Cipher_Ctrl; //0x00 415 #define CC_CTRL_BY_ACPU 0x00000080UL 416 REG32 Cipher_len; //0x02 417 REG32 Parser_Status; //0x04 418 419 }REG_CIPHERCtrl; 420 421 #define ParserCtrlSet (HDCP20_MODE | \ 422 PKT192_MODE | \ 423 AUTO_MODE | \ 424 TRIGGER_MODE | \ 425 INIT_TRUST | \ 426 CLEAR_MODE | \ 427 HW_PARSER_MODE | \ 428 TS_MODE ) 429 430 typedef struct _REG_AESDMACtrlEx 431 { 432 REG_CipherKey Dma_CipherKey_L; //0x60 433 REG_CipherKey Dma_CipherKey_H; //0x64 434 REG_InitVector Dma_InitVector_L; //0x68 435 REG_InitVector Dma_InitVector_H; //0x6C 436 }REG_AESDMACtrlEx; 437 438 typedef struct _REG_HDCP22Data 439 { 440 REG32 Hdcp22_ContentKey[4]; 441 REG32 Hdcp22_Riv[2]; 442 }REG_HDCP22Data; 443 444 typedef struct _REG_HDCP22SEKCtrl 445 { 446 REG32 SEK; //0x9C 447 #define HDCP_SEK_BIT0 0x00000001 448 }REG_HDCP22SEKCtrl; 449 450 typedef struct _REG_GENERAL_STRUCT 451 { 452 REG32 Reg0001; //0x00 453 REG32 Reg0203; //0x02 454 REG32 Reg0405; //0x04 455 REG32 Reg0607; //0x06 456 REG32 Reg0809; //0x08 457 }REG_GENERAL_STRUCT; 458 459 typedef struct _REG_HDCP14SEKCtrl 460 { 461 REG32 REG_0001; //0x0E 462 #define HDCP14_SEK_BIT0 0x00000001 463 }REG_HDCP14SEKCtrl; 464 465 typedef REG_GENERAL_STRUCT REG_TZPCCtrl; //BANK: 0x1239 466 #define REG_TZPC2NONPM_RNG_SOURCE_EN 0x000F0000UL //0x03[3:0] 467 468 typedef REG_GENERAL_STRUCT REG_SECUREBASECtrl; //BANK: 0x113D 469 #define REG_RNG_EN 0x00000080UL //0x00[7] 470 471 typedef REG_GENERAL_STRUCT REG_ANAMISCBASECtrl; //BANK: 0x110C_10 472 #define REG_MIPSPLL_OCCCLK2_EN 0x02000000UL //0x11[9] 473 474 typedef REG_GENERAL_STRUCT REG_AES_DSCMB6Ctrl; //BANK: 0x173D_0 475 #define AESDMA_DSCRMB3_HW_PASER_EN 0x04000000UL //0x01[10] = 1:DESCRMB3/0:DESCRMB5, [11:10] reg_who_use_hwparser 476 typedef REG_GENERAL_STRUCT REG_AES_DSCMB7Ctrl; //BANK: 0x173D_40 477 #define AESDMA_ISR_CLR 0x00010000UL //0x01[0] 478 479 #endif // #ifndef _AESDMA_REG_MCU_H_ 480