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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: regAESDMA.h 98 // Description: AESDMA Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _RSA_REG_MCU_H_ 103 #define _RSA_REG_MCU_H_ 104 105 106 //-------------------------------------------------------------------------------------------------- 107 // Abbreviation 108 //-------------------------------------------------------------------------------------------------- 109 // Addr Address 110 // Buf Buffer 111 // Clr Clear 112 // CmdQ Command queue 113 // Cnt Count 114 // Ctrl Control 115 // Flt Filter 116 // Hw Hardware 117 // Int Interrupt 118 // Len Length 119 // Ovfw Overflow 120 // Pkt Packet 121 // Rec Record 122 // Recv Receive 123 // Rmn Remain 124 // Reg Register 125 // Req Request 126 // Rst Reset 127 // Scmb Scramble 128 // Sec Section 129 // Stat Status 130 // Sw Software 131 // Ts Transport Stream 132 133 134 //-------------------------------------------------------------------------------------------------- 135 // Global Definition 136 //-------------------------------------------------------------------------------------------------- 137 138 139 //-------------------------------------------------------------------------------------------------- 140 // Compliation Option 141 //-------------------------------------------------------------------------------------------------- 142 143 144 //------------------------------------------------------------------------------------------------- 145 // Harware Capability 146 //------------------------------------------------------------------------------------------------- 147 148 149 //------------------------------------------------------------------------------------------------- 150 // Type and Structure 151 //------------------------------------------------------------------------------------------------- 152 #define REG_RSACTRL_BASE (0xA1200 * 2) 153 154 #define RSA_E_BASE_ADDR (0x00) 155 #define RSA_N_BASE_ADDR (0x40) 156 #define RSA_A_BASE_ADDR (0x80) 157 #define RSA_Z_BASE_ADDR (0xC0) /// 256-64 158 159 #define RSA_MAX_SECURE_RANGE_SIZE (0x6) 160 161 typedef struct _REG32 162 { 163 volatile MS_U32 u32Reg; 164 } REG32; 165 166 typedef struct _REG_SecureRange 167 { 168 REG32 Rsa_Sec_Range_Start; 169 REG32 Rsa_Sec_Range_End; 170 171 }REG_SecureRange; 172 173 174 typedef struct _REG_RSACtrl 175 { 176 REG32 Rsa_Ind32_Start; //(REG_X32_RSA_BASE + 4 * 0) 177 #define RSA_EXP_START 0x00000001 ///exp_start 178 #define RSA_INDIRECT_START 0x00000002 /// ram start 179 #define RSA_IND32_CTRL_DIRECTION_WRITE 0x00000004 /// ram_wdata 180 #define RSA_INT_CLR 0x00000008 /// int_clr 181 #define RSA_BLOCK_RSA_KEY 0x00000010 /// block_rsa_key 182 #define RSA_ROOTKEY_SEL_PUB_NO 0x00000020 /// if public key, 0: select 1st key; 1 select 2nd key 183 #define RSA_ROOTKEY_SEL_TYPE 0x00000040 /// 1: OTP RSA key is public; 0: OTP RSA is private 184 //#define RSA_ROOTKEY_SEL_MASK 0x00000060 /// rootkey_sel:2 185 REG32 Rsa_Dummy; 186 REG32 Rsa_Ctrl; //(REG_X32_RSA_BASE + 4 * 2) 187 #define RSA_CTRL_RSA_RST 0x00000001 //RSA_SW_RESET_t sw_reset:1; 188 #define RSA_CTRL_SEL_HW_KEY 0x00000002 //RSA_HW_KEY_t hw_key:1; 189 #define RSA_CTRL_SEL_PUBLIC_KEY 0x00000004 //RSA_PUB_KEY_t pub_key:1; 190 #define RSA_CTRL_NMI 0x00000010 ///nmi:1; 191 #define RSA_CTRL_NLEN_ADJ 0x00000020 ///nlen_adj:1 192 #define RSA_CTRL_SRAM_EN 0x00000080 ///sram_en:1 193 #define RSA_CTRL_KEY_LENGTH_MASK 0x00003F00 ///nlen:6 194 #define RSA_RAM_DIR 0x00020000 ///RAM_DIR_t 195 #define RSA_IND32_CTRL_ADDR_AUTO_INC 0x00040000 196 #define RSA_IND32_CTRL_ACCESS_AUTO_START 0x00080000 197 #define RSA_RAM_MSB_FIRST 0x00100000 198 REG32 Rsa_Ind32_Addr; //(REG_X32_RSA_BASE + 4 * 3) REG_RSA_RAM_ADDR, REG_RSA_STATUS 199 #define RSA_STATUS_RSA_BUSY 0x01000000 200 #define RSA_STATUS_MASK 0x01000000 201 REG32 Rsa_Ind32_Data; //(REG_X32_RSA_BASE + 4 * 4) REG_RSA_RAM_DATA 202 203 REG_SecureRange Rsa_Sec_Range[RSA_MAX_SECURE_RANGE_SIZE]; 204 #define REG_RSA_SEC_RANGE_MASK 0xFFFF0000 205 #define REG_RSA_SEC_RANGE_SHIFT 16 206 207 REG32 Rsa_CA_Spare_Oneway0; //(REG_X32_RSA_BASE + 4 * 11) 208 REG32 Rsa_CA_Spare_Oneway1; //(REG_X32_RSA_BASE + 4 * 12) 209 REG32 Rsa_Miu_Address_Mask; //(REG_X32_RSA_BASE + 4 * 13) 210 REG32 Rsa_Xiu_Id; //(REG_X32_RSA_BASE + 4 * 14) 211 REG32 Rsa_Release_Access; //(REG_X32_RSA_BASE + 4 * 15) 212 REG32 Rsa_Hwkey_Switch; //(REG_X32_RSA_BASE + 4 * 16) 213 #define RSA_READ_HWKEY_SWITCH 0x00000001 214 #define RSA_HWKEY_SWITCH 0x00000100 215 216 }REG_RSACtrl; 217 218 219 #endif // #ifndef _RSA_REG_MCU_H_ 220